JPH02199937A - Block check system for plural received texts - Google Patents

Abstract

PURPOSE:To check the state of each text even after plural consecutive texts are entirely received by adding a check code representing the result of checking a relevant text after a check code checking each text. CONSTITUTION:A register 23 for BCC 1 receives a transmission data from a data bus DB, generates a check code BCC 1 and sends it to a gate circuit 26. A gate circuit 25 gives the content of the data bus to a transmission/ reception circuit 28 in the case of transmission but it is turned off in the case of the transmission of the BCC 1. A register 24 for BCC 2 receives a reception data via the data bus DB and sends the generated BCC 2 to a gate circuit 27. The gate circuit 25 is turned off in the case of receiving,the BCC 2 to disconnect the transmission/reception circuit 28 and the data bus DB. Finally the gate circuit 25 is switched from the data bus DB into the transmission/reception circuit 28 at the transmission and switched from the transmission/reception circuit 28 to the data bus DB at the reception. The transfer of the BCC 1, BCC 2 is realized by the operation as above.

Description

[Detailed Description of the Invention] [Summary] Regarding the block check method when receiving a plurality of continuous messages, the present invention makes it possible to check each message received so far after receiving all of the plurality of messages, thereby reducing the burden on the CPU. In order to reduce the number of messages, the start code (STX) that indicates the start of the message, the code (TEXT) that indicates the content, the end code (ETX) that indicates the end of the message, and the check code that checks the message.
In the block check method for multiple message reception in which messages consisting of a code (BCC) are continuously received, a check code indicating the result of checking the message is added after the check code (BCC) that checks each message. (BCC2), and the state of each message can be checked by searching for the check code (BCC2) even after all of the plurality of continuous messages have been received.

[Industrial application field]

The present invention relates to a block check method when receiving a plurality of messages.

Data communication is typically digital communication performed between a host computer and a plurality of terminal devices via a transmission line.

Various transmission control codes have been defined for this purpose; for example, TEXT is a code indicating the content of the message, S T
Start of Text) is text (block)
Start code indicating the start of ET
of, Text) is the end code indicating the end of the block, B CC (Block Check Co.
de) indicates a block check code for checking the state of the block. 0 Usually, STX, ETX
, BCC consists of 8 bits (1 byte).

[Conventional technology]

Figure 6 is a diagram showing the configuration of a conventionally used message. - Consists of code ETX and check code BCC that checks this block.

FIG. 7 shows a message structure when a plurality of messages having the structure shown in FIG. 6 are transmitted and received in succession. Generally, a plurality of messages (TEXTl=n) are sent and received as shown in this figure.

FIG. 5 is a system configuration diagram in which a plurality of terminal devices (#l to #n) are connected to a control device C in a daisy chain. In such a system, the control device C performs polling P for each terminal device, and data D is returned from the corresponding terminal device to the control device C. Bit errors in this message are detected by inputting this message into a check circuit in the channel device, storing the check result in a register, and reading this register after reception is complete to determine whether the message is good or bad. . That is, to check the BCC of each message, a register for BCC is usually prepared in the channel device, and the CPU checks the value of the register after completion of reception.

[Problem to be solved by the invention]

In the above-mentioned conventional system, a problem arises especially when receiving continuous messages as shown in FIG. That is, the BCC generation range of the terminal device #l is the range of “l”, but when the BCC generation range of the terminal device #2 is continuously transmitted from #l to #2, the BCC generation range of the terminal device #2 is the range of “l”.
The C generation range is “1+2”, and the BCC generation range of the terminal device #n is “l+2+−−−+n” after all.
This is the CC generation range. Therefore, even if the contents of the register are checked after reception is completed, the check will be made within the BCC generation range of terminal device #n, so even if a bit error is detected, it will be checked in which message (TEXTI~n) it occurred. I can't.

To deal with this problem, the BC of each block is
It is possible to check by having the channel device issue an interrupt when a C is received and the CPU reading the BCC register, but if the CPU starts receiving the next message before reading it from the register, the BCC It is difficult to execute because the contents of the BCC will change.Furthermore, CPLJ can also calculate the BCC by software after receiving the BCC, but in this case there is a problem that the CPU is overloaded.

SUMMARY OF THE INVENTION An object of the present invention is to provide a block check method for receiving multiple messages that enables BCC checking of any message without placing a burden on the CPU even when multiple messages are received in succession.

[Means to solve the problem]

FIG. 1 is a diagram showing the structure of a message according to the present invention. The present invention provides a start code (STX) indicating the start of a message, a code (TEXT) indicating the content, and an end code indicating the end of the message.
In the block check method for receiving multiple messages in which messages consisting of a code (ETX) and a check code (BCC) that checks the messages are continuously received, a check code (BCCI) that checks each message is , a check code (BCC2) indicating the result of checking the message is added, and the status of each message can be checked by searching for the check code (BCC2) even after receiving the entire plurality of consecutive messages. It is characterized by being able to be checked.

[For production]

In the message structure according to the present invention, as described above, a check code BCC indicating the check result is added after the check code BCC of each message. That is, the end of the message is composed of ETX, BCCI, and BCC2. Here, BCCl is a conventional BCC, and BCC2 is a check code added according to the present invention.

As mentioned above, BCC2 indicates the check result of the message. Therefore, the sending side can add any value and the receiving side channel generates the result and writes it to the memory. With this configuration, the CPU is It is possible to check each message by simply checking each BCC2 after receiving the message.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the BCC transfer circuit according to the present invention. This circuit is provided within the channel device. In the figure, 21 is the STX detection circuit, 22 is the ETX
Detection circuit, 23 is BCCl register, 24 is BCC2
registers, 25 to 27 are gate circuits, 28 is transmission/reception (
T/R) circuit, DB is the internal data bus of the channel device.

Figures 3 and 4 are signal time charts of the circuit in Figure 2,
FIG. 3 shows the time of transmission, and FIG. 4 shows the time of reception.

The operation of the circuit shown in FIG. 2 will be explained below with reference to FIGS. 3 and 4.

At the time of transmission, the STX detection circuit 21 detects the STX at the time of transmission.
When the ETX detection circuit 22 detects ETX, the signal ■ turns on (ON), and when the ETX detection circuit 22 detects ETX, the signal ■ turns on (ON). As shown in FIG. 3, the signal (2) turns off (OFF) when the signal (2) turns on, and the signal (2) turns off at the timing described later after the signal (2) turns off. These signals are synchronized with the rise of the write signal (2) input to the transmitter/receiver circuit 28.

The gate circuit 26 to which the signals ■ and ■ are input is the signal ■.

Transmission data is input from the BCCI register 23 tabus DB, which turns on (gate opens) only when both of (2) are on, generates a check code BCCI, and sends it to the gate circuit 26. When the gate circuit 26 is on as described above, the BCCI cash register 23 is transferred to the transmitter/receiver circuit 28.
Send to. Gate circuit 26 is BCC1 register 23
It is a one-way gate that sends out the contents of . Furthermore, during transmission, the gate circuit 25 transmits the contents of the data bus to the transmitting/receiving circuit 28.
However, it is turned off when BCCl is sent.

At the time of reception, the STX detection circuit 21. When the ETX detection circuit 22 detects STX and ETX during reception, the signals ■ and ■ are turned on. As shown in Figure 4, the signal ■ turns on when STX is detected, turns off when the signal ■ is on, and the signal ■ turns on when ETX is detected, and turns off when the signal ■ is off. . And the signal ■,
The timing of (2) is synchronized with the read signal RD input to the transmitting/receiving circuit 28. The read signal TT5'- is used to switch the direction of the gate circuit 25. The BCC2 register 24 inputs received data via the data bus DB and sends the generated BCC2 to the gate circuit 27.

The gate circuit 27 is a one-way gate from the BCC2 register 24 to the data bus DB, and is turned on when BCC2 is received. When the gate circuit 25 receives BCC2, it turns off and disconnects the transmitting/receiving circuit 28 from the data bus DB.In the end, the gate circuit 25 switches from the data bus DB to the transmitting/receiving circuit 28 when transmitting, and when receiving, it switches from the transmitting/receiving circuit 28 to the transmitting/receiving circuit 28. Switches to data bus DB.

Transfer of BCCI and BCC2 can be realized by the above-described operation.

〔Effect of the invention〕

As explained above, according to the present invention, even when receiving multiple messages in succession, it is possible to check the BCC of each message received so far after receiving the entirety of the multiple messages, thereby reducing the burden on the CPU. can do.

[Brief explanation of the drawing]

FIG. 1 is a message configuration diagram according to the present invention, FIG. 2 is a BCC transfer circuit diagram of an embodiment of the present invention, FIG. 3 is a signal time chart of the present invention (at the time of transmission), and FIG. 4 is a signal time chart of the present invention. (At the time of reception) FIG. 5 is a system configuration diagram, and FIGS. 6 and 7 are conventional message configuration diagrams. (Explanation of symbols) 21... STX detection circuit, 22... ETX detection circuit, 23... BCCI register, 24... BCC2 register, 25.26.27... Gate circuit, 28. ...Transmission/reception circuit.

Claims (1)

[Claims] 1. A start code (STX) indicating the start of a message;
A block check method for receiving multiple messages that continuously receives messages consisting of a code (TEXT) indicating the content, an end code (ETX) indicating the end of the message, and a check code (BCC) for checking the message. , the said check code (BCC) that checks each message
is followed by a check mark indicating the result of checking the message.
Even after adding the check code (BCC2) and receiving the entire plurality of continuous messages, the check code (BCC2)
2) A block check method for receiving multiple messages, characterized in that the status of each message can be checked by searching.