JPH02199845A - Heterojunction type field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To accurately form a plurality of threshold values inside one wafer face by a method wherein a gate electrode containing a metal material reacting with a nonconductive-type semiconductor layer is formed on the nonconductivity- type semiconductor layer. CONSTITUTION:An undoped GaAs layer 3, an Si-doped high-concentration n-type GaAs layer 5 and an undoped GaAlAs layer 7 are formed on a semiinsulating substrate 1. Then, one pair of n<+> ion implantation regions 8 are formed; after that, AuGe/Ni/Au ohmic electrodes 9, 11 are formed. Then, an opening is made in a part in which a gate electrode is formed; the gate electrode 15 which reacts with the undoped GaAlAs layer 7 and which is composed of Pt (platinum) of a predetermined amount is deposited on the undoped GaAlAs layer 7. Then, this assembly is heated at a prescribed temperature; a solid-phase reaction is caused between the Pt gate electrode 15 and the undoped GaAlAs layer 7; a solid-phase reaction part 17 is formed near the Pt gate electrode 15 in the undoped GaAlAs layer 7.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a heterojunction field effect transistor having a Schottky gate electrode, and particularly to a heterojunction field effect transistor having a Schottky gate electrode. This invention relates to a heterojunction field effect transistor that can be used.

(Prior art) In recent years, GaAs MESFETs and heterojunction FETs have been used to speed up processing in computers and communication equipment.
GaAs compound semiconductor integrated circuits having ET (HEMT) as a basic element are used.

In order to speed up the integrated circuit, each M
It is necessary to improve the characteristics of ESFETs and HEMTs. In order to improve the characteristics of a GaAsFET, there is a method of making the channel layer (n-type GaAs layer) of the FET highly doped and thin, but in the above method, the gate electrode consisting of a Schottky junction and the high concentration Concentration n-type Ga
There was a problem in that the gate breakdown voltage was significantly deteriorated between the gate and the As layer.

Therefore, when a FET with the thinned channel layer described above is used in a tC circuit, especially a DCFL circuit suitable for high speed, the noise margin, which is one of the important characteristics, will decrease. there were.

As a method of improving the gate breakdown voltage of the FET according to the above method, there is a method of providing an undoped GaAs layer as a barrier layer on top of the channel layer of the FET, and the structure of the heterojunction FET is shown in FIG. Fourth
In the conventional example shown in the figure, a semi-insulating GaAs substrate 1
An undoped GaAs layer 3 is formed on the undoped GaAs layer, and a Sl-doped heavily doped n-type Ga layer is formed on the undoped GaAs layer.
The As layer 5 is formed as a thin layer, and the undoped GaAlAs layer 7 is formed as a barrier layer on the n-type GaAs layer. And the above undoped Ga
Source electrode 9 and drain electrode 1 on the As layer 7
A gate electrode 13 made of a heat-resistant gate metal WSI is disposed between the gate electrode 1 and the gate electrode 1 .

In the conventional example, the thickness of the undoped GaAs layer 3 is 5000, the thickness of the n-type GaAs layer 5 is 80A1, the concentration is 2X10'8Cffi3, and the thickness of the undoped GaAlAs layer 7 is 200A1. It becomes.

In the GaAs heterojunction FET having the structure as described above, the threshold voltage vth can be approximated by the following equation.

vth φB − ΔE − qNDdD (2d o +d D ) / 2E where, φB Barrier height of the Nijimittsky junction ΔE: Band discontinuity energy of the conduction band q: Charge ND, d,: of the n-type GaAs layer Concentration and thickness do: Thickness of undoped GaAlAs layer E: Dielectric constant As is clear from the above formula, the heterojunction type Ga of the above structure
In the As FET, in its manufacturing process, the thickness of the undoped GaAS layer 3 within one wafer surface,
Since the thickness and concentration of the n-type GaAs layer 5 and the thickness of the undoped GaAlAs layer 7 are constant, the threshold voltage of each FET in one wafer is uniquely constant. It was something that would become.

Therefore, it is not possible to achieve two threshold voltages within the wafer surface with GaAs heterojunction FETs having the above configuration, and it is not possible to achieve two threshold voltages in a circuit that requires two threshold voltages, such as a DCFL circuit. had the disadvantage that it was difficult to use.

Another possible method is to control the threshold voltage by etching the undoped GaAs layer 7 to realize two threshold voltages.

However, since the undoped GaA, 1jAs layer 7 has a thickness of 200 and is at most 500 Å or less,
Etching control is difficult, and when two threshold values are achieved by etching, there is a problem that each threshold voltage becomes non-uniform.

(Problems to be Solved by the Invention) As described above, in the conventional heterojunction FET shown in FIG. There was a problem in that it was not possible to obtain multiple threshold values.

The present invention has been made in view of the above-mentioned problems.
The objective is to provide a heterojunction FET that can have multiple thresholds that are uniform within one wafer plane. The second purpose is to develop such a heterojunction type FE.
It is an object of the present invention to provide a manufacturing method that can form T with good controllability.

[Structure of the Invention] (Means for Solving the Problems) A heterojunction field effect transistor according to the first invention includes a conductive type semiconductor layer formed on at least a semi-insulating substrate, and a conductive type semiconductor layer formed on the conductive type semiconductor layer. a non-conductive semiconductor layer formed on the non-conductive semiconductor layer;
The gate electrode includes a metal material that reacts with the non-conductive semiconductor layer.

A second invention provides a method for manufacturing at least two heterojunction field effect transistors having different threshold voltages, including the steps of: forming a conductive semiconductor layer on a semi-insulating substrate; forming a non-conductive semiconductor layer on the non-conductive semiconductor layer, and forming first and second gate electrodes each having a different predetermined amount of a metal material that reacts with the non-conductive semiconductor layer. a step of heating the field effect transistor on which the gate electrode is formed at a predetermined temperature to form first and second solid phase reaction regions having different thicknesses in the non-conductive semiconductor layer; The present invention provides a method for manufacturing a heterojunction field effect transistor comprising:

(Function) By providing on the non-conductive semiconductor layer a gate electrode having a metal material that reacts with the non-conductive semiconductor layer,
A solid phase reaction occurs in the vicinity of the gate electrode of the non-conductive semiconductor layer, and the reaction changes the thickness of the non-conductive semiconductor layer and also changes the threshold voltage. Therefore, by individually controlling the amount of reaction between the non-conductive semiconductor layer and the metal material of the gate electrode in each FET within one wafer, multiple threshold values can be adjusted accurately within one wafer. can be achieved well.

(Example) FIG. 1 is a manufacturing process diagram of a heterojunction field effect transistor according to the present invention.

A heterojunction field effect transistor according to the present invention will be explained with reference to FIG. 1 above.

First, as shown in FIG. 1(a), an undoped GaAs layer 3 having a thickness of 200 OA is formed on a semi-insulating substrate 1 as a buffer layer. Here, the above undoped G
a The As layer 3 has an impurity concentration of about 1×10 15 CI −3 as a result of not actively adding impurities.

On top of the undoped GaAs layer, deposit S with a thickness of 50 nm.
l A heavily doped n-type GaAs layer 5 is formed. This layer is heavily doped with 81 with a concentration of 2 x 10'''C''3 and becomes the channel region.

On the n-type GaAs layer, an undoped GaAlAs layer 7 of 400 A is further formed as a high resistivity layer.

Next, as shown in FIG. 1(b), n+ ions are implanted to form a pair of n+ ion implanted regions 8. and,
After performing roughed thermal annealing (rapid heating) at 900°C for 5 seconds, Au Ge /Nl /Au was formed as the source and drain electrodes by lift-off method.
An ohmic electrode 9°11 is formed.

Next, as shown in FIG. 1(C), the gate electrode 15 made of a predetermined amount of Pt (platinum) that reacts with the undoped GaA1As layer 7 was placed on 200 people. The above undoped GaA thickness
Deposit on uAs layer 7.

Next, as shown in FIG. 1(d), the FET with the Pt agate electrode 15 formed thereon is heated at a predetermined temperature of, for example, 350° C. for a predetermined time.
The Pt agate electrode 15 and the undoped GaAlAs
A solid phase reaction occurs between the undoped GaAu layer 7 and the undoped GaAu layer 7.
A solid phase reaction portion 17 is generated in the vicinity of the Pt agate electrode 15 in the As layer 7 . Therefore, by increasing the thickness do of the vapor solid phase reaction section 17, the undoped GaA
The thickness d of the lAs layer 7 becomes narrower, and thereby the absolute value of the threshold voltage changes greatly.

Thickness cio and threshold voltage Vth of the solid phase reaction section 17
The relationship with is expressed by the following formula.

■ Δvth−ΔaO d.

Here, when the solid phase reaction is completely completed, the undoped GaAlAs layer 7 is consumed in an amount approximately twice the amount of Pt. In this way, a heterojunction type F with a MIS type gate
ET is completed. The relationship between the solid phase reaction amount and the amount of change in the absolute value of the threshold voltage is shown in FIG.

According to the manufacturing method described above, in a plurality of heterojunction FETs within one wafer surface, by changing the amount of Pt in the gate electrode of each FET, FETs having different threshold voltages can be formed. can do.

Further, the amount of solid phase reaction can be controlled by the heating temperature and heating time during the solid phase reaction, and the threshold voltage can be controlled. Here, an n-type GaAs layer is used as the channel region, but a p-type GaAs layer may also be used.

In addition, the heating temperature during the solid phase reaction is 350 to 4
A range of 50°C is appropriate.

Next, another embodiment according to the present invention will be described with reference to FIG.

In this other embodiment, as shown in FIG. 3, a gate electrode 23 in which Pt 19 and W (tungsten) 21 are sequentially stacked is provided on an undoped GaA1As layer. Since it is similar to that of the first embodiment, detailed explanation will be omitted.

When the gate electrode 23 having the Pt layer and W layer as described above is provided, in addition to the effects of the first embodiment, after the solid phase reaction,
The upper W layer 21 has effects such as improving thermal stability and improving gate resistance by about 50%.

Although Pt was used as the reactive metal material in the above embodiment, Pd (palladium) may also be used.

Furthermore, the present invention is not limited to the combinations of semiconductor layers shown in the embodiments, but may also be combined with other semiconductors, such as AILlnAs as a non-conductive semiconductor layer, GaInAs as an n-type or P-type semiconductor layer, etc. . In this case, an InP substrate may be used.

Furthermore, instead of the upper W layer, tungsten silicide (WS
iX), tungsten nitride (WNx), tungsten silicon nitride (WSiN), etc. may also be used.

Note that the present invention can be implemented with various modifications without departing from the spirit thereof.

[Effect of the invention] As described above, each heterojunction FE in one wafer plane
At T, a predetermined amount of gate electrodes having a metal material that undergoes a solid phase reaction with the undoped GaAlAs layer are disposed on the undoped GaAlAs layer, and heated to control the amount of the solid phase reaction. A plurality of threshold values can be achieved with high precision within the wafer plane.

[Brief explanation of the drawing]

Figure 1 is a manufacturing process diagram of a heterojunction field effect transistor according to the present invention. Figure 2 is a graph showing the relationship between the amount of solid phase reaction and the amount of change in threshold voltage. Structural diagram of another embodiment of the heterojunction FET according to the invention. FIG. 4 is a structural diagram of a conventional heterojunction FET. 1... Semi-insulating Ga As substrate 3... Undoped Ga As layer 5... Si doped high concentration n-type Ga As layer 7...
・On undoped GaA1As layer 17...Solid phase reaction part

Claims (5)

[Claims] (1) a conductive semiconductor layer formed on at least a semi-insulating substrate, a non-conductive semiconductor layer formed on the conductive semiconductor layer, and a conductive semiconductor layer formed on the non-conductive semiconductor layer; A heterojunction field effect transistor comprising a gate electrode having a metal material that reacts with a non-conductive semiconductor layer. (2) The conductive type semiconductor layer is a GaAs layer or a GaAs layer.
2. The heterojunction field effect transistor according to claim 1, wherein the non-conductive semiconductor layer is an undoped G2AlAs layer. (3) The metal material of the gate electrode is Pt or Pd.
The heterojunction field effect transistor according to claim 1, characterized in that it is any one of the following. (4) A method for manufacturing at least two heterojunction field effect transistors having different threshold voltages,
forming a conductive semiconductor layer on a semi-insulating substrate; forming a non-conductive semiconductor layer on the conductive semiconductor layer; and forming a non-conductive semiconductor layer on the non-conductive semiconductor layer. forming first and second gate electrodes each having a different predetermined amount of a reactive metal material; and heating the field effect transistor with the gate electrodes formed thereon at a predetermined temperature to form the non-conductive type. 1. A method for manufacturing a heterojunction field effect transistor, comprising the step of forming first and second solid phase reaction portions having different thicknesses in a semiconductor layer. (5) The method for manufacturing a heterojunction field effect transistor according to claim 4, wherein the threshold value of the field effect transistor is controlled according to the amount of metal material of the gate electrode.