JPH02196332A - Information processor - Google Patents

Abstract

PURPOSE:To perform the patching jobs without changing the CSROM itself even in the case the firmware instruction stored in the CSROM has a defect or a function is changed by replacing the address to the CSROM with the output of a patch RAM having the same number of words as the CSROM. CONSTITUTION:A patch RAM 4 has the same number of a words as a CSROM 2, and '1' is written into a word of the RAM 4 corresponding to the address of the CSROM 2 to be patched in the case a partial patch is required for the defect of the CSROM 2. Furthermore a pacthed firmware instruction is stored in a word of a CSRAM 3 which is shown by an address where the most signifi cant bit of the address of the CSROM 2 is replaced with '1'. Thus the firmware instruction stored in the CSRAM 3 can be sent to a CPU 1 in place of the firmware instruction stored in the CSROM 2. Then the firmware instruction stored in the CSROM 2 can be patched.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and particularly to a firmware-controlled information processing device.

BACKGROUND TECHNOLOGY Conventionally, in this type of information processing device, a control memory in which firmware instructions are stored is a ROM (Read 0
nly MeIIlory) Teal Kotka Ta Katta. Therefore, if there is a problem with the firmware instructions stored in the ROM or a function change is required, the ROM
There was only a batch (Patcl+) method of replacing the unit itself.

Therefore, there is a drawback that it is expensive to replace the ROM in order to change the firmware instructions stored in the ROM. In particular, there has been a drawback that a large amount of cost is spent on maintenance of the information processing apparatus after it has been shipped to the user.

OBJECTS OF THE INVENTION An object of the present invention is to provide an information processing device that can deal with problems with firmware instructions without replacing the ROM itself.

Structure of the Invention An information processing device according to the present invention includes a first storage means having a plurality of areas in which firmware is stored in advance, and a first storage means provided corresponding to each of the plurality of areas of the first storage means, and A storage means for storing flag information indicating whether the area is valid or invalid, a second storage means, and flag information corresponding to an area of the first storage means to be accessed according to address information from a host device. means for generating address information for the second storage means using information obtained by replacing a part of the address information with the flag information when the address information indicates that the address information is invalid; The present invention is characterized in that the storage area of the second storage means is used in place of the invalid area of the first storage means.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of an information processing apparatus according to the present invention. In the figure, 1 is a CPU, 2 is a CS ROM (Control Storage R
OM), 3 is CS RAM (Control
5 toraque R N), 4 is a patch RAM for patching, 5 is a register that holds the address of C5RAM, 6 is a register that holds the address of C5ROM, and 7 is a selector that selects either register 5 or register 6. be.

Also, in the figure, 8 is an address bus that sends addresses to C5ROM2 and C8RAM3, and 9 is a bus that sends addresses from CPU1 to C8RA.
Address bus that outputs the address for M3, 10 is an address bus that outputs the address from CPU1 to C5ROM2, 11 is an instruction path to CPU1, 12 is C
This is a path for outputting firmware instructions from 5ROM2 or C8RAM3.

C5ROM2 and C5RAM3 are control memories, and the second
As shown in the figure, it constitutes a continuous memory space. Incidentally, FIG. 2 is an address map of control storage in one practical example of the present invention.

Hatsuchi RAM4 has the same number of words as C8ROM2,
One word is one bit of auxiliary memory.

The initial value of this patch RAM 4 is assumed to be "0" for all words.

This means that the address to be patched to C5ROM2 is 1.
It shows that it does not always exist.

The selector 7 operates to select register 5 when the CPUI outputs an address to path 9, and selects register 6 when the CPU does not output an address to path 1o.

In such a configuration, in the initial state, the path 9 is
The address that is not output to C5RAM3 via
is held in register 5, and is held in register 5 by selector 7.
The output of is selected and sent to the control storage via path 8.

On the other hand, from CPU 1 through path 1o (csR.

The address issued to M2 is input to patch RAM4. The most significant bit of the input address of patch RAM 4 is replaced with 1 bit output from patch R and AM 4, and then held in register 6.
The address is sent to the control memory by selecting the appearance of the address.

Next, a case will be described in which a part of the C5ROM2 is patched due to a defect or the like.

In this case, "1" is written in the word in the patch RAMd corresponding to the address of the C8ROM2 to be patched.

Furthermore, the CSR indicated by the address with the most significant bit of the C5ROM2 address replaced with "1"
Store the patched firmware instructions in the word in AMB. Referring to FIG. 2, the patch area for C3RO,M is the broken line portion (A) on C5RAM in the figure.

Again, when the address is output from the CPUI, the corresponding word in the patch RAM 4 is "1", so
The topmost pin 1 of that address is replaced with "1", and C
After the address for 5ROM2 is converted into an address for C8RAM3, it is output via path 8 to the control store. Then, from the control memory, the patched firmware instructions are output from C3 and RAM 3 instead of the firmware instructions in C8ROM2.

Through the above operations, the firmware instructions in the CS RAM B can be sent to the CPUI instead of the firmware instructions in the C5ROM2, making it possible to patch the firmware instructions stored in the C5ROM.

Note that in this embodiment, address conversion is performed by replacing the most significant bit of the address; however, the same effect can be obtained by converting other bits. it is obvious. In other words, all you have to do is replace part of the address.

DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention provides a patch RAM having the same number of words as the CSR, OM, and replaces the address for the C5ROM with the output of this patch RAM, thereby updating firmware instructions stored in the C5ROM. Even if there is a problem with the C or there is a change in the function, the
5ROM itself can be patched without replacing it, and R
This has the effect of reducing costs related to OM replacement.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a memory map of the control storage shown in FIG. Explanation of symbols of main parts 1...CPU 2...C5ROM 3...C8RAM 4...Patch RAM 5.6...Register 7 ······selector

Claims (1)

[Claims] (1) A first storage means having a plurality of areas in which firmware is pre-stored, and a first storage means provided corresponding to each of the plurality of areas of the first storage means, and a memory device for determining whether the area is valid or invalid. a storage means for storing flag information indicating the flag information;
storage means, and information in which a part of the address information is replaced with flag information when flag information corresponding to an area of the first storage means to be accessed according to address information from a host device indicates invalidity. means for generating address information for the second storage means using the address information, and a storage area of the second storage means designated by this address information in place of an invalid area of the first storage means. An information processing device characterized in that it is used as an information processing device.