JPH02192757A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH02192757A JPH02192757A JP1012921A JP1292189A JPH02192757A JP H02192757 A JPH02192757 A JP H02192757A JP 1012921 A JP1012921 A JP 1012921A JP 1292189 A JP1292189 A JP 1292189A JP H02192757 A JPH02192757 A JP H02192757A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- shielding material
- semiconductor
- frame
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 104
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000463 material Substances 0.000 claims abstract description 46
- 238000007789 sealing Methods 0.000 claims description 7
- 230000000903 blocking effect Effects 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 abstract description 4
- 239000009719 polyimide resin Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 description 24
- 238000000034 method Methods 0.000 description 9
- 239000002184 metal Substances 0.000 description 7
- 238000005219 brazing Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000005260 alpha ray Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000003566 sealing material Substances 0.000 description 3
- 230000005574 cross-species transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子の表面に遮蔽材が塗布されてなる半
導体装置およびその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a shielding material is coated on the surface of a semiconductor element, and a method for manufacturing the same.
従来、半導体装置にはα線ソフトエラ一対策として半導
体素子上に遮蔽材が塗布され、能動領域がこの遮蔽材に
よって被覆されていた。この種の半導体装置を第３図に
よって説明する。Conventionally, in semiconductor devices, a shielding material is coated on the semiconductor element as a countermeasure against α-ray soft error, and the active region is covered with this shielding material. This type of semiconductor device will be explained with reference to FIG.
第３図は従来の半導体装置の製造方法を説明するための
図で、同図（ａ）はウェハ基板上に能動領域等の回路部
が形成された状態を示す断面図、同図（ｂ）はウェハ基
板から分断された半導体素子を示す断面図、同図（ｃ）
は半導体素子が容器内に装着された状態を示す断面図、
同図（ｄ）は封止後の状態を示す断面図である。これら
の図において、■はウェハ基板、２は半導体素子で、こ
の半導体素子２は前記ウェハ基板１に複数並設されてお
り、各半導体素子２には回路部としての能動領域２ａお
よび電極部２ｂがそれぞれ形成されている。３は前記半
導体素子２を収納するためのパッケージとしての半導体
容器で、この半導体容器３には半導体素子２の電気信号
を外部に取り出すための外部す−ド４が設けられている
。５はこの半導体容器３内に半導体素子２をダイボンデ
ィングするためのろう材で、このろう材５は半田、ある
いはＡｕ−５ｔ等によって形成されている。６は前記半
導体素子２の電極部２ｂと半導体容器３の外部リード４
とを接続するための金属細線、７はα線遮断用の遮蔽材
で、この遮蔽材７はポリイミド樹脂等からなり、半導体
素子２上に塗布されている。８は前記半導体容器３内に
ボンディングされた半導体素子２．金属細線６および遮
蔽材７等を外部雰囲気から保護するための金属蓋で、こ
の金属蓋８は半導体容器３の上部開口部にシール材９を
介して固定されている。FIG. 3 is a diagram for explaining a conventional method for manufacturing a semiconductor device, in which (a) is a cross-sectional view showing a state in which circuit parts such as active regions are formed on a wafer substrate, and (b) is a cross-sectional view showing a semiconductor element separated from a wafer substrate, (c)
is a cross-sectional view showing a state in which a semiconductor element is installed in a container,
FIG. 4(d) is a sectional view showing the state after sealing. In these figures, ■ is a wafer substrate, and 2 is a semiconductor element. A plurality of semiconductor elements 2 are arranged in parallel on the wafer substrate 1, and each semiconductor element 2 has an active area 2a as a circuit part and an electrode part 2b. are formed respectively. Reference numeral 3 denotes a semiconductor container as a package for accommodating the semiconductor element 2, and the semiconductor container 3 is provided with an external card 4 for taking out the electrical signals of the semiconductor element 2 to the outside. Reference numeral 5 denotes a brazing material for die-bonding the semiconductor element 2 into the semiconductor container 3, and the brazing material 5 is made of solder, Au-5t, or the like. Reference numeral 6 denotes the electrode portion 2b of the semiconductor element 2 and the external lead 4 of the semiconductor container 3.
7 is a shielding material for blocking alpha rays, and this shielding material 7 is made of polyimide resin or the like and is coated on the semiconductor element 2. Reference numeral 8 denotes a semiconductor element 2.8 bonded within the semiconductor container 3. A metal lid 8 is used to protect the thin metal wire 6, shielding material 7, etc. from the external atmosphere, and is fixed to the upper opening of the semiconductor container 3 via a sealing material 9.
次に、このように構成された従来の半導体装置を製造す
る方法について説明する。先ず、第３図（ａ）に示すよ
うに、ウェハ基板１に能動領域２ａおよび電極部２ｃを
形成し、次いで、同図（ｂ）に示すように、半導体素子
２をダイシングによりウェハ基板ｌから分断させる。そ
して、同図（ｃ）に示すように、半導体素子２を半導体
容器３内にダイボンディングさせる。このダイボンディ
ングはろう材５を介し加熱処理して行われる。ダイボン
ディング後、半導体素子２の電極部２ｂと外部リード４
とを金属細線６を介して接続する。次いで、同図（ｄ）
に示すように、半導体素子２上にα線ソフトエラ一対策
のために遮蔽材７を塗布して加熱処理後、最後に、外部
雰囲気から半導体素子２等を遮断するために半導体容器
３と金属蓋８とを加熱処理してシール材９で固定する。Next, a method for manufacturing the conventional semiconductor device configured as described above will be described. First, as shown in FIG. 3(a), active regions 2a and electrode portions 2c are formed on a wafer substrate 1, and then, as shown in FIG. 3(b), semiconductor elements 2 are diced from the wafer substrate 1. divide. Then, as shown in FIG. 3(c), the semiconductor element 2 is die-bonded into the semiconductor container 3. This die bonding is performed by heat treatment through the brazing material 5. After die bonding, the electrode portion 2b of the semiconductor element 2 and the external lead 4
and are connected via a thin metal wire 6. Next, the same figure (d)
As shown in the figure, after coating the semiconductor element 2 with a shielding material 7 to prevent α-ray soft error and heat treatment, a semiconductor container 3 and a metal lid are finally installed to shield the semiconductor element 2, etc. from the external atmosphere. 8 are heat treated and fixed with a sealing material 9.
このようにして半導体装置が組み立てられることになる
。In this way, the semiconductor device is assembled.
しかるに、このように構成された従来の半導体装置にお
いては、半導体素子２の能動領域２ａが遮蔽材７で完全
に覆われるように遮蔽材７を塗布しなければならないに
も係わらず、量産時には塗布量を一定に保つことが困難
であるために塗布量のばらつきが生じる。遮蔽材７が所
定量より多く塗布された場合には第３図（ｄ）中７８に
示すように遮蔽材７が半導体素子２外に流れ出してしま
う。However, in the conventional semiconductor device configured in this way, although the shielding material 7 must be coated so that the active region 2a of the semiconductor element 2 is completely covered with the shielding material 7, it is necessary to apply the shielding material 7 during mass production. Variations in the amount of application occur because it is difficult to keep the amount constant. If the shielding material 7 is applied in an amount larger than the predetermined amount, the shielding material 7 will flow out of the semiconductor element 2 as shown at 78 in FIG. 3(d).
このような場合には遮蔽材７がろう材５と反応して飛散
されたり、金属細線６が断線されたりするという問題が
生じる。In such a case, a problem arises in that the shielding material 7 reacts with the brazing material 5 and is scattered, or the thin metal wire 6 is broken.
本発明に係る半導体装置は、半導体素子上に、回路部を
囲みかつ回路部の表面より上方へ突出する枠体を設け、
この枠体によって囲まれた範囲内に遮蔽材を塗布したも
のである。また、本発明に係る半導体装置の製造方法は
、半導体素子を半導体ウェハから分断する前に、回路部
を囲みかつ回路部の表面より上方へ突出する枠体を半導
体素子上に設け、しかる後、この半導体素子を、前記枠
体によって囲まれた範囲内にα線遮断用の遮蔽材が塗布
された状態でパンケージによって封止するものである。A semiconductor device according to the present invention includes, on a semiconductor element, a frame that surrounds a circuit section and projects upward from a surface of the circuit section;
A shielding material is applied within the area surrounded by this frame. Furthermore, in the method for manufacturing a semiconductor device according to the present invention, before cutting the semiconductor element from the semiconductor wafer, a frame body that surrounds the circuit section and projects upward from the surface of the circuit section is provided on the semiconductor element, and then, This semiconductor element is sealed with a pan cage with a shielding material for blocking alpha rays applied within the area surrounded by the frame.
遮蔽材が半導体素子上から零れるのを枠体が阻止するこ
とになり、塗布量を厳格に調整しなくとも確実に半導体
素子の回路部を遮蔽材で覆うことができる。The frame prevents the shielding material from spilling over the semiconductor element, and the circuit portion of the semiconductor element can be reliably covered with the shielding material without strictly adjusting the amount of application.
以下、本発明の一実施例を第１図によって詳細に説明す
る。Hereinafter, one embodiment of the present invention will be described in detail with reference to FIG.
第１図は本発明に係る半導体装置の製造方法を説明する
ための図で、同図（ａ）はウェハ基板上に能動領域等の
回路部が形成された状態を示す断面図、同図（ｂ）はウ
ェハ基板上に枠状パターンが形成された状態を示す断面
図、同図（ｃ）はウェハ基板から分断された半導体素子
を示す断面図、同図（ｄ）は半導体素子が容器内に装着
された状態を示す断面図、同図（ｅ）は封止後の状態を
示す断面図である。これらの図において前記第３図（ａ
）ないし第３図（ｄ）で説明したものと同一もしくは同
等部材については同一符号を付し、ここにおいて詳細な
説明は省略する。第１図において、１１は遮蔽材７が半
導体素子２から零れるのを阻止するための枠状パターン
で、この枠状パターン１１はポリイミド樹脂からなり、
半導体素子２の能動領域２ａを囲む部位に途切れること
なく一連に突設されている。また、前記枠状パターン１
１は突出端部が能動領域２ａの表面より十分に高くなる
ように設定されている。FIG. 1 is a diagram for explaining the method of manufacturing a semiconductor device according to the present invention, and FIG. b) is a cross-sectional view showing a frame pattern formed on a wafer substrate, (c) is a cross-sectional view showing a semiconductor element separated from a wafer substrate, and (d) is a cross-sectional view showing a semiconductor element separated from a wafer substrate. A sectional view showing the state in which the device is attached to the device, and FIG. 3(e) is a sectional view showing the state after sealing. In these figures, the above-mentioned figure 3 (a
) to FIG. 3(d), the same or equivalent members are given the same reference numerals, and detailed explanations are omitted here. In FIG. 1, 11 is a frame-shaped pattern for preventing the shielding material 7 from spilling from the semiconductor element 2, and this frame-shaped pattern 11 is made of polyimide resin.
A series of protrusions are provided at a portion surrounding the active region 2a of the semiconductor element 2 without interruption. In addition, the frame pattern 1
1 is set so that the protruding end portion is sufficiently higher than the surface of the active region 2a.
次に、本発明に係る半導体装置の製造方法を説明する。Next, a method for manufacturing a semiconductor device according to the present invention will be explained.
先ず、第１図（ａ）に示すように、ウェハ基板Ｉに能動
領域２ａおよび電極部２ｃを形成し、次いで、同図（ｂ
）に示すように、ウェハ基板１上に枠状パターン１１を
形成する。そして、同図（ｃ）に示すように、半導体素
子２をダイシングによりウェハ基板１から分断させる。First, as shown in FIG. 1(a), an active region 2a and an electrode portion 2c are formed on a wafer substrate I, and then, as shown in FIG.
), a frame pattern 11 is formed on a wafer substrate 1. Then, as shown in FIG. 2C, the semiconductor element 2 is separated from the wafer substrate 1 by dicing.
次に、同図（ｄ）に示すように、半導体素子２を半導体
容器３内にダイボンディングさせる。このダイボンディ
ングはろう材５を介し加熱処理して行われる。ダイボン
ディング後、半導体素子２の電極部２ｂと外部リード４
とを金属細線６を介して接続する。そして、同図（ｅ）
に示すように、半導体素子２上に形成された枠状パター
ン１１内にα線ソフトエラ一対策のために遮蔽材７を塗
布して加熱処理する。この際、遮蔽材７は枠状パターン
１１内に溜められることになり、半導体素子２外に零れ
にくくなる。しかる後、外部雰囲気から半導体素子２等
を遮断するために半導体容器３と金属蓋８とを加熱処理
してシール材９で固定する。このようにして半導体装置
が組み立てられることになる。Next, as shown in FIG. 3(d), the semiconductor element 2 is die-bonded into the semiconductor container 3. This die bonding is performed by heat treatment through the brazing material 5. After die bonding, the electrode portion 2b of the semiconductor element 2 and the external lead 4
and are connected via a thin metal wire 6. And the same figure (e)
As shown in FIG. 2, a shielding material 7 is applied within a frame pattern 11 formed on a semiconductor element 2 to prevent α-ray soft error, and then heat-treated. At this time, the shielding material 7 is collected within the frame pattern 11, making it difficult to spill out of the semiconductor element 2. Thereafter, the semiconductor container 3 and the metal lid 8 are heat-treated and fixed with a sealing material 9 in order to isolate the semiconductor element 2 and the like from the external atmosphere. In this way, the semiconductor device is assembled.
したがって、このように構成された半導体装置において
は、遮蔽材７が枠状パターン１１内に溜められることと
なり、半導体素子上から零れにくくなるため、遮蔽材７
の塗布量を厳格に調整しなくとも確実に半導体素子２の
能動領域２ａが遮蔽材７で覆われることになる。Therefore, in the semiconductor device configured in this way, the shielding material 7 is accumulated in the frame-shaped pattern 11 and is difficult to spill over the semiconductor element.
The active region 2a of the semiconductor element 2 is reliably covered with the shielding material 7 without strictly adjusting the application amount.
なお、本実施例では枠状パターン１１をポリイミド樹脂
によって形成した例を示したが、本発明はこのような限
定にとられれることなく、枠状パターン１１はどのよう
な材料によって形成してもよい。Although this embodiment shows an example in which the frame pattern 11 is made of polyimide resin, the present invention is not limited to this, and the frame pattern 11 can be made of any material. good.
また、枠状パターン１１の形成方法も写真製版法。Further, the method of forming the frame pattern 11 is also a photolithography method.
スクリーン印刷法、蒸着法等様々な方法を採用すること
ができる。Various methods such as screen printing, vapor deposition, etc. can be used.
また、本実施例では半導体素子２を半導体容器３内に搭
載させてから遮蔽材７を塗布した例を示したが、本発明
では遮蔽材７を塗布する時期は何時でもよく、例えば、
第２図に示すように半導体素子２をウェハ基板１から分
断させる前であってもよい。Further, although this embodiment shows an example in which the shielding material 7 is applied after the semiconductor element 2 is mounted in the semiconductor container 3, in the present invention, the shielding material 7 may be applied at any time.
It may be done before the semiconductor element 2 is separated from the wafer substrate 1 as shown in FIG.
第２図は他の実施例による半導体装置の製造方法を説明
するための図で、同図（ａ）はウェハ基板上に能動領域
等の回路部が形成された状態を示す断面図、同図（ｂ）
はウェハ基板上に枠状パターンが形成された状態を示す
断面図、同図（ｃ）は枠状パターン内に遮蔽材が塗布さ
れた状態を示す断面図、同図（ｄ）はウェハ基板から分
断された半導体素子を示す断面図、同図（ｅ）は半導体
素子が容器内に装着された状態を示す断面図、同図（ｆ
）は封止後の状態を示す断面図である。これらの図にお
いて前記第１図で説明したものと同一もしくは同等部材
については同一符号を付し、ここにおいて詳細な説明は
省略する。このように遮蔽材７をウェハプロセス中で塗
布しても前記実施例と同等の効果が得られる。FIG. 2 is a diagram for explaining a method of manufacturing a semiconductor device according to another embodiment, and FIG. (b)
is a cross-sectional view showing a frame pattern formed on a wafer substrate, (c) is a cross-sectional view showing a shielding material coated inside the frame pattern, and (d) is a cross-sectional view showing a frame pattern formed on a wafer substrate. A cross-sectional view showing the divided semiconductor device, (e) a cross-sectional view showing the semiconductor device mounted in the container, and (f)
) is a sectional view showing the state after sealing. In these figures, the same or equivalent members as those explained in FIG. Even if the shielding material 7 is applied during the wafer process in this manner, the same effect as in the embodiment described above can be obtained.
以上説明したように本発明に係る半導体装置は、半導体
素子上に、回路部を囲みかつ回路部の表面より上方へ突
出する枠体を設け、この枠体によって囲まれた範囲内に
遮蔽材を塗布したものであり、また、本発明に係る半導
体装置の製造方法は、半導体素子を半導体ウェハから分
断する前に、回路部を囲みかつ回路部の表面より上方へ
突出する枠体を半導体素子上に設け、しかる後、この半
導体素子を、前記枠体によって囲まれた範囲内にα線遮
断用の遮蔽材が塗布された状態でパッケージによって封
止するものであるため、遮蔽材が半導体素子上から零れ
るのを枠体が阻止することになり、塗布量を厳格に調整
しなくとも確実に半導体素子の回路部を遮蔽材で覆うこ
とができる。したがって、半導体装置を量産するにあた
り遮蔽材の塗布量の調整が容易になるから生産性を向上
させることができ、しかも、遮蔽材が半導体素子上から
零れ難くなるために信頼性の高い半導体装置が得られる
。As explained above, in the semiconductor device according to the present invention, a frame body surrounding a circuit section and projecting upward from the surface of the circuit section is provided on a semiconductor element, and a shielding material is provided within an area surrounded by the frame body. Furthermore, in the method for manufacturing a semiconductor device according to the present invention, a frame body surrounding the circuit portion and protruding upward from the surface of the circuit portion is coated on the semiconductor device before the semiconductor device is separated from the semiconductor wafer. The semiconductor element is then sealed in a package with a shielding material for blocking alpha rays applied within the area surrounded by the frame, so that the shielding material does not overlap the semiconductor element. The frame prevents the shielding material from spilling, and the circuit portion of the semiconductor element can be reliably covered with the shielding material without strictly adjusting the amount of application. Therefore, when mass producing semiconductor devices, productivity can be improved because it is easier to adjust the amount of the shielding material applied, and moreover, the shielding material is less likely to spill over the semiconductor elements, resulting in highly reliable semiconductor devices. can get.
第１図は本発明に係る半導体装置の製造方法を説明する
ための図で、同図（ａ）はウェハ基板上に能動領域等の
回路部が形成された状態を示す断面図、同図（ｂ）はウ
ェハ基板上に枠状パターンが形成された状態を示す断面
図、同図（ｃ）はウェハ基板から分断された半導体素子
を示す断面図、同図（ｄ）は半導体素子が容器内に装着
された状態を示す断面図、同図（ｅ）は封止後の状態を
示す断面図、第２図は他の実施例による半導体装置の製
造方法を説明するための図で、同図（ａ）はウェハ基板
上に能動領域等の回路部が形成された状態を示す断面図
、同図（ｂ）はウェハ基板上に枠状パターンが形成され
た状態を示す断面図、同図（ｃ）は枠状パターン内に遮
蔽材が塗布された状態を示す断面図、同図（ｄ）はウェ
ハ基板から分断された半導体素子を示す断面図、同図（
ｅ）は半導体素子が容器内に装着された状態を示す断面
図、同図（ｆ）は封止後の状態を示す断面図、第３図は
従来の半導体装置の製造方法を説明するための図で、同
図（ａ）はウェハ基板上に能動領域等の回路部が形成さ
れた状態を示す断面図、同図（ｂ）はウェハ基板から分
断された半導体素子を示す断面図、同図（ｃ）は半導体
素子が容器内に装着された状態を示す断面図、同図（ｄ
）は封止後の状態を示す断面図である。
１・・・・ウェハ基板、２・・・・半導体素子、２ａ・
・・・能動領域、３・・・・半導体容器、７・・・・遮
蔽材、１１・・・・枠状パターン。FIG. 1 is a diagram for explaining the method of manufacturing a semiconductor device according to the present invention, and FIG. b) is a cross-sectional view showing a frame pattern formed on a wafer substrate, (c) is a cross-sectional view showing a semiconductor element separated from a wafer substrate, and (d) is a cross-sectional view showing a semiconductor element separated from a wafer substrate. (e) is a cross-sectional view showing the state after sealing, and FIG. 2 is a diagram for explaining a method of manufacturing a semiconductor device according to another embodiment. (a) is a cross-sectional view showing a state in which circuit parts such as active areas are formed on a wafer substrate, and (b) is a cross-sectional view showing a state in which a frame pattern is formed on a wafer substrate. (c) is a cross-sectional view showing a state in which the shielding material is applied within the frame-shaped pattern, (d) is a cross-sectional view showing a semiconductor element separated from a wafer substrate, (
Fig. 3(e) is a cross-sectional view showing the state in which the semiconductor element is installed in the container, Fig. 3(f) is a cross-sectional view showing the state after sealing, and Fig. 3 is a cross-sectional view showing the state after the semiconductor device is sealed. In the figure, (a) is a cross-sectional view showing a state in which circuit parts such as active regions are formed on a wafer substrate, and (b) is a cross-sectional view showing a semiconductor element separated from the wafer substrate. (c) is a cross-sectional view showing the state in which the semiconductor element is installed in the container, and (d)
) is a sectional view showing the state after sealing. 1... Wafer substrate, 2... Semiconductor element, 2a.
. . . Active area, 3 . . . Semiconductor container, 7 . . . Shielding material, 11 . . . Frame pattern.
Claims (2)
塗布されてなる半導体装置において、前記半導体素子上
に、回路部を囲みかつ回路部の表面より上方へ突出する
枠体を設け、この枠体によって囲まれた範囲内に前記遮
蔽材を塗布したことを特徴とする半導体装置。(1) In a semiconductor device in which a shielding material that blocks alpha rays is coated on a circuit portion of a semiconductor element, a frame body that surrounds the circuit portion and projects upward from the surface of the circuit portion is provided on the semiconductor element. . A semiconductor device, wherein the shielding material is applied within an area surrounded by the frame.
路部を囲みかつ回路部の表面より上方へ突出する枠体を
半導体素子上に設け、しかる後、この半導体素子を、前
記枠体によって囲まれた範囲内にα線遮断用の遮蔽材が
塗布された状態でパッケージによって封止することを特
徴とする半導体装置の製造方法。(2) Before cutting the semiconductor element from the semiconductor wafer, a frame that surrounds the circuit section and projects upward from the surface of the circuit section is provided on the semiconductor element, and then the semiconductor element is surrounded by the frame. 1. A method of manufacturing a semiconductor device, which comprises sealing the semiconductor device with a package in a state in which a shielding material for blocking alpha rays is coated within the range.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1012921A JPH02192757A (en) | 1989-01-20 | 1989-01-20 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1012921A JPH02192757A (en) | 1989-01-20 | 1989-01-20 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02192757A true JPH02192757A (en) | 1990-07-30 |
Family
ID=11818799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1012921A Pending JPH02192757A (en) | 1989-01-20 | 1989-01-20 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02192757A (en) |
-
1989
- 1989-01-20 JP JP1012921A patent/JPH02192757A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3287346B2 (en) | Semiconductor device | |
| KR100298563B1 (en) | Semiconductor Package and Formation Method | |
| US20060205117A1 (en) | Solder masks used in encapsulation, assemblies including the solar mask, and methods | |
| US20030109077A1 (en) | Method for fabricating surface acoustic wave filter packages | |
| US20060125085A1 (en) | Semiconductor device which prevents light from entering therein | |
| JP2000323614A (en) | Image sensor.ball grid array.package and manufacture thereof | |
| JPH11121507A (en) | Semiconductor device and its manufacture | |
| US6876090B2 (en) | Semiconductor chip and method for producing housing | |
| GB2067354A (en) | Mounting for a s.c. device | |
| US3874072A (en) | Semiconductor structure with bumps and method for making the same | |
| US4883773A (en) | Method of producing magnetosensitive semiconductor devices | |
| CN113594051A (en) | Semiconductor packaging method | |
| JPH02192757A (en) | Semiconductor device and manufacture thereof | |
| JPH043450A (en) | Resin sealed semiconductor device | |
| US4183135A (en) | Hermetic glass encapsulation for semiconductor die and method | |
| US20020030248A1 (en) | Process for producing BGA type semiconductor device, TAB tape for BGA type semiconductor device, and BGA type semiconductor device | |
| JPH04103142A (en) | Glass plate package and semiconductor device | |
| JP2532496B2 (en) | Semiconductor device mounting method | |
| US4151638A (en) | Hermetic glass encapsulation for semiconductor die and method | |
| JP2000286366A (en) | Semiconductor device and manufacture thereof | |
| JPH027453A (en) | Glass cap method | |
| JPH08184608A (en) | Microcavity for semiconductor device and manufacture thereof | |
| KR20030046941A (en) | Surface acoustic wave device package and method | |
| JPH05326618A (en) | Semiconductor device | |
| JPS6224650A (en) | Semiconductor device |