JPH0219025A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To realize a phase locked loop circuit with higher resolution more than that of an integral number of multiple of a reference frequency without lowering a reference frequency by controlling the change quantity per unit time of a phase difference signal. CONSTITUTION:An A/D converter 5 and control circuit 6 constitute a differentiating circuit 7 applying differentiation equivalent to an output of a phase difference signal 4. When an output frequency f0 of a voltage controlled oscillator(VCO) 1 is not an integral number of multiple of the reference signal frequency fr, an output of a phase comparator 4 is a sawtooth waveform. Then phase lock is applied by the differentiating circuit 7 so as to apply feedback to the VCO 1 in a way that a differentiating value of the sawtooth waveform is made constant, the A/D converter 5 samples the sawtooth waveform at a proper time interval in the differentiating circuit 7 to apply A/D conversion and the control circuit 6 outputs a control voltage to the VCO 1 so that a difference of a digital output for each sample is made constant. Thus, the phase locked loop circuit with higher resolution more than an integral number of multiple of the reference frequency and with fast response is realized with simple constitution without lowering the reference frequency.

Description

Detailed Description of the Invention A. Objective of the Invention [Field of Industrial Application] The present invention provides a high-resolution PLI (phase 1ocked 1oop
) relates to improvements in the characteristics of circuits.

[Conventional technology]

FIG. 5 shows an example of a conventional phase-locked loop circuit.

Voltae Control Oscillator
d 0scillat.

r = hereinafter referred to as VCO) 21 is divided by an integer frequency by a frequency divider 22 (dividing the frequency by a fraction of an integer), and a signal is compared with a reference signal from a reference oscillator 23 by a phase comparator 24. , by feeding back a control voltage corresponding to the phase difference to the VCO 21 via the low-pass filter 25, the VCO
The output frequency ro of 21 is phase-locked to the reference frequency fr.

[Problem that the invention seeks to solve]

However, in the above method, it is not possible to set the output frequency fO to a value other than an integral multiple of the reference frequency fr.If the frequency of the reference oscillator 23 is lowered and the division ratio of the frequency divider circuit 22 is increased, the resolution can be improved. Although this can be improved, the time required for phase locking becomes longer and the response speed becomes slower.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to realize a phase-locked loop circuit with higher resolution than an integral multiple of the reference frequency without lowering the reference frequency.

``Structure of the Invention'' [Means for Solving Problems] The present invention divides the output of a voltage controlled oscillator using a frequency dividing circuit, and calculates the phase difference between the output of the frequency divider and a reference signal using a phase comparator. This circuit is related to a phase-locked loop circuit that controls the output frequency of a voltage-controlled oscillator using a signal that is detected by a signal that corresponds to the output of a phase comparator. The present invention is characterized in that it includes a control means for controlling the voltage controlled oscillator so that the amount of change in winning is constant.

[Effect]

Since the difference in frequency between the reference signal and the frequency dividing circuit output corresponds to the amount of change in the phase difference signal per unit time, the frequency can be changed continuously by controlling the amount of change.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing an embodiment of a phase-locked loop circuit according to the present invention. 1 is a frequency dividing circuit in which the VCO 52 divides the output frequency of the VCol by an integer, 3 is a reference oscillator that outputs a reference signal of frequency fr, and 4 is a phase comparison circuit that outputs the phase difference between the reference signal and the output of the frequency dividing circuit 2 as a voltage. 5 is an A/D converter that A/D converts the output of the phase comparator 4; 6 is an A/D converter;
This is a control circuit that inputs the digital output of the converter 5 and controls the VCOI. The A/D converter 5 and the control circuit 6 include a differentiation circuit 7 that performs an isometric differentiation operation on the output of the phase comparator 4.
Configure.

When the output frequency f of the VCOI is not an integral multiple of the frequency fr of the reference signal, the output of the phase comparator 4 becomes a sawtooth wave as shown in FIG. This is because the output of the phase ratio axis device 4 returns to 0 again every time the phase difference between the reference signal and the output of the frequency dividing circuit 2 becomes 2π. Since the slope θ and period T of the sawtooth wave shown in FIG. 2 are determined by the magnitude of the difference in frequency between the two signals input to the phase comparator 4, the differential value of this sawtooth wave is made constant by the differentiating circuit 7. Like VCOl
By applying feedback to , phase lock can be applied even when the output frequency fo is not an integral multiple of the frequency fr of the reference signal. 19 & branch circuit 7, the A/D converter is connected to the second
Sample the sawtooth wave in the figure at appropriate time intervals and use A/
After D conversion, the control circuit 6 outputs a control voltage to vcot so that the difference in digital output for each sample is constant. Therefore, by changing the target value of the above-mentioned difference, the output frequency fO can be changed with high resolution without changing the reference frequency fr. When the output frequency fo is an integral multiple of the frequency ff of the reference signal, the change in the phase difference output of the phase comparator and the output of the control circuit 6 becomes O, and the phase is locked at an appropriate frequency division ratio as in the conventional case. .

According to the phase-locked loop circuit having such a configuration, a high-resolution PLL circuit can be realized without lowering the reference frequency, and high resolution and short lock time can be achieved at the same time.

FIG. 3 is a block diagram showing a second embodiment of the phase-locked loop circuit according to the present invention. The same parts as in FIG. 1 are given the same symbols and the explanation is omitted.

Unlike the case in FIG. 1, the phase comparator 14 outputs a pulse width corresponding to the phase difference, such as an edge trigger type, and this pulse width is measured by a pulse width measuring circuit 15. In the pulse width measuring circuit 15, the pulse width signal from the phase comparator 14 and the short period clock generator 1 are connected to each other.
51 is input to an ANDlff circuit 152, and a counter 153 counts the clocks while the pulse width signal is being generated. The contents of counter 153 are reset at the beginning of each cycle at the rising edge of the pulse width signal. FIG. 4 is a time chart showing the relationship between the pulse width output of the phase comparator 14 and the output of the AND circuit 152.

The control circuit 6
The point of control is the same as in the case of FIG. 1, and the pulse width measuring circuit 15 and the control circuit 6 constitute an approximate differentiating circuit.

Note that in each of the above embodiments, the differentiating circuit is implemented by a digital circuit, but an analog differentiating circuit can also be used without using an A/D converter.

C. Effects of the present invention J As described above, according to the present invention, a phase-locked loop circuit with a high-speed response and a resolution higher than an integer multiple of the reference frequency can be realized with a simple configuration without lowering the reference frequency. can do.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing an embodiment of the phase-locked loop circuit according to the present invention, FIG. 2 is a time chart showing the operation of the device shown in FIG. 1, and FIG. 3 is a block diagram of the phase-locked loop circuit according to the present invention. FIG. 4 is a time chart showing a part of the operation of the device shown in FIG. 3, and FIG. 5 is a block diagram showing a conventional phase locked loop circuit.

Claims (1)

[Claims] The output of the voltage controlled oscillator is divided by a frequency dividing circuit, the phase difference between the output of this frequency divider and the reference signal is detected by a phase comparator, and the output frequency of the voltage controlled oscillator is determined by the signal corresponding to the output of the phase comparator. A phase-locked loop circuit to be controlled, comprising a control means for controlling a voltage-controlled oscillator so that the amount of change per unit time of the phase difference signal output from the phase comparator is constant. .