JPH02190043A - Sampling phase error detection circuit - Google Patents

Abstract

PURPOSE:To detect a phase error with high accuracy by obtaining an absolute value of a signal at a signal point with a phase error detected at it and obtaining the mean value and the absolute value so as to extract an output by both adjacent points of the signal point only and including the signal information before and after the signal point to the said extracted output. CONSTITUTION:An input signal string to detect its phase error is inputted to a shift register 1, an absolute value (b) of a data (a) of the 2nd stage of the shift register 1 is obtained by an absolute value circuit 2, a means value (c) is obtained by an averaging circuit 3 and a subtractor 4 obtains a difference (d) between the absolute value (b) and the mean value (c). On the other hand, the data (a) of the 2nd stage of the shift register 1 is multiplied with the data of the 1st stage by a multiplier 5, its product is inputted to a multiplier 6, where the said product is multiplied with the difference (d) outputted from the subtractor 4, and the resulting product (e) is inputted to an output control circuit 8. Moreover, the data of the 1st stage of the shift register 1 is multiplied with the data of the 3rd stage at a multiplier 7, its product is inputted to an output control circuit 8, an output (e) of the multiplier 6 is outputted to an output side according to the product or interrupted therefrom. Thus, a clock phase error is detected with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase error detection circuit for a sampling clock in a demodulator for digital communications.

[Conventional technology]

Conventionally, as a circuit for detecting the phase error of a sampling clock required in a demodulator for digital communication, etc., a zero cross point when a signal changes from +1 to =1,
In other words, a circuit is provided that calculates the phase of the zero-crossing point by calculating information obtained from the signs of the signal points on both sides of the data at the midpoint of the signal, and estimates the phase of the signal point from this. .

[Problem to be solved by the invention]

The conventional sampling phase error detection circuit described above performs double sampling and estimates the phase difference between signal points from the phase difference between the clock and the zero-crossing point. Therefore, if the eye pattern of the signal is distorted due to imperfections in the filter or the like, there is a problem in that the phase of the estimated signal point shifts as shown in FIG.

SUMMARY OF THE INVENTION An object of the present invention is to provide a sampling phase error detection circuit that solves these problems and makes it possible to detect phase errors with high precision.

[Means to solve the problem]

The sampling phase error detection circuit of the present invention includes a three-stage shift register that accumulates a human input signal sequence, an absolute value circuit that takes the absolute value of the data in the second stage of this shift register,
an averaging circuit that takes the average value of the output of the absolute value circuit; a subtracter that calculates the difference between the output of the absolute value circuit and the output of the average value circuit; and each data in the first and second stages of the shift register. a first multiplier that multiplies the outputs of the subtracter, a second multiplier that multiplies each output of the first multiplier and the subtracter, and a third multiplier that multiplies each data of the second and third stages of the shift register. and an output control circuit that passes or blocks the output of the second multiplier depending on the output of the third multiplier.

[Effect]

In the configuration described above, by finding the absolute value of the signal at the signal point where the phase error is detected and finding the difference between the average value and the absolute value, it is possible to extract the output only from both sides of the signal point. By adding the signal information before and after the signal point to the output, the signal is always equal to the phase shift.
This can be obtained only when the signals on both sides have opposite signs, realizing highly accurate phase error detection.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a signal waveform diagram of each part of FIG. 1 a'' to e.

In Figure 1, the input signal sequence for which the phase error is detected is 3.
The signal is input to a shift register 1 configured in stages. and,
The absolute value of the data a in the second stage of the shift register 1 is determined in an absolute value circuit 2, and averaged in an averaging circuit 3 to obtain an average value C. Then, in the subtracter 4, the difference d between the output of the absolute value circuit 2 and the average value C of the averaging circuit 3 is determined.

On the other hand, the second stage data of the shift register 1 is multiplied by the first stage data in the first multiplier 5, and the product is inputted to the second multiplier 6. The second multiplier 6 then multiplies the difference d output from the subtracter 4 and inputs the product e to the output control circuit 8 .

Further, the data in the first stage and the data in the third stage of the shift register 1 are multiplied in a third multiplier 7, the product is manually inputted to the output control circuit 8 as a gate signal, and the multiplier is multiplied according to this value. It is configured to allow the output e of the device 6 to pass through to the output side or to block it.

FIG. 3 shows an example of a signal whose phase error is to be detected. In this figure, for the sake of simplification, the spread beyond one bit from the center of the signal is ignored because it is small. Furthermore, although the waveform actually output is a superposition of each waveform as shown by the broken line in the figure, the individual impulse waveforms are shown by solid lines.

Consider the signal point at point A in the figure. If the clocks are out of phase, the actual sample point will be shifted to the left or right of the point. Since the waveform of the signal centered at point A is symmetrical with respect to point A, it is impossible to estimate the clock phase from this signal.

This also applies to other points B, C, and D in the figure.

Therefore, it is necessary to consider the influence of signals on both sides of each signal point, that is, code amount interference. However, when the signals on both sides have the same sign as at points A and C, the waveforms of the signals on both sides are line-symmetrical with respect to the signal point, so it is still impossible to estimate the clock phase. As in the case of points B and D, when the signs of the signals on both sides are opposite, the waveforms of the signals on both sides become point symmetrical with respect to the signal point. Therefore, phase estimation is possible only in such cases.

Therefore, it can be seen that it is sufficient to realize a circuit that extracts only the waveforms of the signals on both sides when the signs of the signals on both sides are opposite.

Therefore, in the circuit of FIG. 1, first, all combinations (1, 1, 1) (1°-
1, -1) (-1, -1, 1) (-1, 1, 1) in the range of ±T before and after the signal point as shown in Figure 2 a.
Shown below. T is the period of the signal. The three-stage shift register 1 can store signal information of samples before and after a sample point, and uses the output point of the second stage as a sample point. The absolute value of the signal at this sample point is taken by the absolute value circuit 2, resulting in the signal shown in the figure.

From a in Figure 2, in the range of ±T/2, the sign of the signal at the sample point is equal to the sign of the signal at the signal point, so if we take the absolute value of the signal at the sample point, the output due to the signal at the signal point is Even if we look at it alone, it always takes the absolute value. Therefore, if the output of the absolute value circuit 2 is averaged by the averaging circuit 3, the output values due to the signals on both sides will be averaged and become zero, and the output based on only the signal at the signal point will be obtained as shown in C in the same figure. .

Therefore, by subtracting the output of the averaging circuit 3 from the absolute value circuit 2 in the subtracter 4, it is possible to extract outputs based on only the adjacent signals on both sides, as shown in d of FIG. However, in this output d, there are still two types of waveforms, so the first multiplier 5 calculates the product of the sign of the sample point and the sign of the previous sample, and the value is sent to the output of the subtracter 4. When multiplied by the second multiplier 6, the output becomes as shown in the figure e, and the output is always equal to the phase shift, making it possible to detect the sampling phase error with high precision. Become. here,
The time interval T corresponds to the phase 2π.

However, in order to output only when the signals on both sides have opposite signs, the third multiplier 7 calculates the product of the signs before and after the sample point, and only when the value is negative, the gate of the output control circuit 8 is activated. It is opened to output the output of the second multiplier 6.

〔Effect of the invention〕

As explained above, since the phase of a signal point can be directly determined, the present invention has the advantage of being able to detect clock phase errors with high accuracy even when the eye pattern is distorted due to imperfections in the filter. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a waveform diagram of a signal whose phase error is to be detected, and FIG. 4 is an eye pattern for explaining problems in a conventional detection circuit. ■...Shift register, 2...Absolute value circuit, 3...
- Average circuit, 4... Subtractor, 5... First multiplier, 6
. . . second multiplier, 7 . . . third multiplier, 8 . . . output control circuit. Figure 1 r -------d'"'' D Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. A three-stage shift register that accumulates an input signal string, an absolute value circuit that takes the absolute value of the data in the second stage of this shift register, and an averaging circuit that takes the average value of the output of this absolute value circuit, a subtracter that calculates the difference between the output of the absolute value circuit and the output of the average value circuit; a first multiplier that multiplies each data in the first and second stages of the shift register; a second multiplier that multiplies each output of the subtracter; a third multiplier that multiplies each data in the second and third stages of the shift register; and a third multiplier that multiplies the output of the second multiplier. 1. A sampling phase error detection circuit comprising: an output control circuit that passes or cuts off the output depending on the output of the sampling phase error detection circuit.