JPH0218951A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH0218951A JPH0218951A JP63169606A JP16960688A JPH0218951A JP H0218951 A JPH0218951 A JP H0218951A JP 63169606 A JP63169606 A JP 63169606A JP 16960688 A JP16960688 A JP 16960688A JP H0218951 A JPH0218951 A JP H0218951A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- die
- wire
- pattern
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 12
- 230000017525 heat dissipation Effects 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 12
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims 3
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 230000005855 radiation Effects 0.000 abstract description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052733 gallium Inorganic materials 0.000 abstract description 2
- 101150015217 FET4 gene Proteins 0.000 abstract 1
- 230000005685 electric field effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- IHWJXGQYRBHUIF-UHFFFAOYSA-N [Ag].[Pt] Chemical compound [Ag].[Pt] IHWJXGQYRBHUIF-UHFFFAOYSA-N 0.000 description 1
- 230000002730 additional effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01031—Gallium [Ga]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は混成集積回路でのび化ガリウム電界効果トラ
ンジスタ（以下ＧａＡａ ＦＥＴという）を取り付ける
放熱ブロックの形状に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the shape of a heat dissipation block for mounting a stretched gallium field effect transistor (hereinafter referred to as GaAa FET) in a hybrid integrated circuit.
第３図は、従来の混成集積回路において、放熱ブロック
上に取り付けられたＧａＡａ ＦＥＴ部分を示す平面図
であり、第４図は第３図に示すＹ・Ｙ線における断面図
である。FIG. 3 is a plan view showing a GaAa FET portion mounted on a heat dissipation block in a conventional hybrid integrated circuit, and FIG. 4 is a sectional view taken along the YY line shown in FIG. 3.
＠３図及び第４図において、（１）はアルミナ基板、（
２１はアルミナ基板（１）上に設けられた銀−白金や、
銀−パラジウムの材質から成るダイポンド用パターン、
ｆ３１ｉダイポンド用パターン（２）上に取り付けられ
た放熱ブロック、１４１ｉ放熱ブロツク（３）上に取り
付けられたＧａＡａ ＦＥＴ、 （５１はＧａＡｓＦＥ
Ｔ ｔ４１のドレインが接続されるアルミナ基板＋１１
上のドレインパターン、［６１Ｇ”ｒ、 ＧａＡ１ Ｐ
ＥＴ ［４）のゲートが接続されるアルミナ基板（１）
上のゲートパターン、（７）はＧａＡｓ ＦＥＴ（４）
の電極と、ｌ＆ｉＴｈブロック（３）、ドレインパター
ン＋５１ 、 ケートパターン（６）全接続するワイヤ
、＋８１Ｈアルミナ基板ｆｉ＋の下面に設けられた接地
導体である。@ In Figures 3 and 4, (1) is an alumina substrate, (
21 is silver-platinum provided on the alumina substrate (1),
Dipond pattern made of silver-palladium material,
A heat dissipation block mounted on the f31i diepond pattern (2), a GaAa FET mounted on the 141i heat dissipation block (3), (51 is a GaAsFE
Alumina substrate +11 to which the drain of T t41 is connected
Upper drain pattern, [61G”r, GaA1P
Alumina substrate (1) to which the gate of ET [4] is connected
Upper gate pattern (7) is GaAs FET (4)
These are the electrodes, the l&iTh block (3), the drain pattern +51, the gate pattern (6), the wires that connect all of them, and the ground conductor provided on the bottom surface of the +81H alumina substrate fi+.
次に動作について説明する。ｌＧａＡｍ ＦＥＴ ｆ４
１はワイヤ（７）ニより、アルミナ基板＋１１上のドレ
インパターン（５）、ゲートパターン（６）及び放熱ブ
ロック（３）を通してダイポンド用パターン（２）に接
続され動作する。このときＧａＡｓＦＥＴ ｆ４１で発
生した熱に、放熱ブロック（３）により熱の流れる断面
積を広げられ、アルミナ基板（１）を通り放熱される。Next, the operation will be explained. lGaAm FET f4
1 is connected to the die pond pattern (2) through the drain pattern (5), gate pattern (6) and heat dissipation block (3) on the alumina substrate +11 through the wire (7) and operates. At this time, the heat generated by the GaAsFET f41 is expanded in its cross-sectional area by the heat radiation block (3), and is radiated through the alumina substrate (1).
従来の混成集積回路は以上のように構成されているので
、放熱ブロック上にＧａＡｓ ＦＥＴ ｆｒダイポンド
し念上で、ソースのワイヤボンドをする必要がある。し
かし、この場合にダイボンドのはんだが流れるとソース
のワイヤボンドができなくなるという問題点があり之。Since the conventional hybrid integrated circuit is constructed as described above, it is necessary to mount the GaAs FET fr die on the heat dissipation block and wire-bond the source. However, in this case, there is a problem that if the die bond solder flows, the source wire bond cannot be formed.
この発明は上記のような問題点を解消するためになされ
念もので、同一の放熱ブロック上にダイボンド、ワイヤ
ボンドを行う場合にダイボンドのほんたが流れても、ワ
イヤボンド用の放熱ブロック表面まで流れない構造の混
成集積回路を得ること全目的とする。This invention was made to solve the above-mentioned problems, and even if die bonding and wire bonding are performed on the same heat dissipation block, even if the die bond flows, it will not reach the surface of the heat dissipation block for wire bonding. The overall objective is to obtain a hybrid integrated circuit with a structure that does not flow.
この発明に係る混成集積回路に、放熱ブロックのＧａＡ
ｓ ＦＥＴが取り付けられる面に突の段差を設け、その
上にソースのワイヤボンドをしたものである。In the hybrid integrated circuit according to the present invention, the heat dissipation block is made of GaA.
A protruding step is provided on the surface on which the s-FET is attached, and the source is wire-bonded on top of the step.
この発明における混成集積回路では、放熱ブロックのＧ
ａＡｓ ＰＥＴが取り付けられる面に突の段差を設けた
ため、 ＧａＡｓ ＦＥＴのダイボンド団とソースのワ
イヤボンド面を別にすることが可能となり、そのためダ
イボンドのはんだが流れてもワイヤボンド面に広がる可
能性が非常に小さくなる。In the hybrid integrated circuit according to the present invention, the G of the heat dissipation block is
By creating a sharp step on the surface where the aAs PET is attached, it is possible to separate the die bond group of the GaAs FET from the wire bond surface of the source, which greatly reduces the possibility that even if the die bond solder flows, it will spread to the wire bond surface. becomes smaller.
以下、この発明の一実施例を図について説明する。第１
図はこの発明における混成集積回路のＧａＡａ ＦＥＴ
部分の平面図で、第２図は第１図に示すＸ−Ｘ線におけ
る断面図である。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a GaAa FET of the hybrid integrated circuit in this invention.
FIG. 2 is a plan view of the portion, and FIG. 2 is a sectional view taken along the line X--X shown in FIG.
第１図及び第２図において、（１）〜（８）に′＠３図
の従来例に示したものと同等であるので、説明を省略す
る。（９）はこの発明のｔ！ｌ：、熱ブロック（３）の
ＧａＡｓＦＥＴ［４］が取り付けられた面に設けられた
突の段差である。In FIGS. 1 and 2, (1) to (8) are the same as those shown in the conventional example shown in FIG. 3, so their explanation will be omitted. (9) is the t! of this invention! 1: This is a protruding step provided on the surface of the heat block (3) on which the GaAsFET [4] is attached.
次に動作について説明する。Next, the operation will be explained.
この発明による混成集積回路に第３図の従来例と同様に
ＧａＡｓＦＥＴ ｆ４）にワイヤ（７）によりドレイン
パターン（５）、ソースパターン（６１及び放熱ブロッ
ク（３）を通してダイボンド用パターン（２）に接続さ
れている。また、ＧａＡｓ ＦＥＴ （４）で発生する
熱に放熱ブロック（３）により熱の流れる断面積が広が
る点は同様である。しかし、放熱ブロック（３）に突の
段差（９）を設は念ためにＧａＡｓＦＥＴ （４１を放
熱ブロック（３）へダイボンドする場合に、はんだが流
れても、ソースからのワイヤ（７１は突の段差（９；の
上面に接続される之め、はんだ流れによる問題点が解消
される。In the hybrid integrated circuit according to the present invention, the GaAsFET f4) is connected to the die bonding pattern (2) by wire (7) through the drain pattern (5), source pattern (61) and heat dissipation block (3), as in the conventional example shown in FIG. In addition, the heat dissipation block (3) expands the cross-sectional area through which the heat generated by the GaAs FET (4) flows.However, the heat dissipation block (3) has a protruding step (9). To be sure, when die-bonding the GaAsFET (41) to the heat dissipation block (3), even if the solder flows, the wire from the source (71 is connected to the top surface of the protruding step (9), so the solder flow will not occur). The problems caused by this will be resolved.
また、付加的な効果として、突の段差（９）へソースか
らのワイヤ（７）が接続されるため、ワイヤ（７）の長
さが短くで浅、ＧａＡｓ ＦｇＴ １４１を高周波で動
作させる混成集積回路の場合に、ワイヤ（７）によるイ
ンダクタンス成分による特性への悪影響が小さくできる
と共に、量産時のバラツキを小さくすることも可能とな
る。In addition, as an additional effect, since the wire (7) from the source is connected to the step (9) of the protrusion, the length of the wire (7) is short and shallow, and the hybrid integration that allows GaAs FgT 141 to operate at high frequency is achieved. In the case of a circuit, it is possible to reduce the adverse effect on the characteristics due to the inductance component due to the wire (7), and it is also possible to reduce variations during mass production.
なお、上記実施例では、混成集積回路としてアルミナ基
板ｔｉｎ使用したが、他の材質の基板としても、得られ
る効果は同様である。In the above embodiment, an alumina substrate (tin) was used as the hybrid integrated circuit, but the same effect can be obtained by using a substrate made of other materials.
以上のようにこの発明によれば、放熱ブロックに突の段
差を設けたので、ダイボンド時のはんだ流れによりワイ
ヤボンドができなくなるといったことが完全に避けられ
るなどの効果がある。As described above, according to the present invention, since the heat dissipation block is provided with a protruding step, it is possible to completely avoid wire bonding from being impossible due to solder flow during die bonding.
第１図はこの発明の一実施例における混成集積回路のＧ
ａＡ＠ＰＥＴ部分の平面図、第２図は第１図に示すＸ−
Ｘ線におげろ断面図、第３図に従来の混成集積回路のＧ
ｍＡａ ＦＥＴ部分の平面図、第４図は第３図に示すＹ
−Ｙ線における断面図である。
図中、（１）はアルミナ基板、ｔ２１ｉダイボンド用パ
ターン、（３）は放熱ブロック、（４）はＧａＡａ Ｆ
ＥＴ 、 （５はドレインパターン、（６）にゲートパ
ターン、（７）はワイヤ、（８）は接地導体、（９）は
突の段差である。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 shows the G of a hybrid integrated circuit in one embodiment of the present invention.
aA@PET part plan view, Figure 2 is the X- shown in Figure 1.
A cross-sectional view taken along the X-ray, and Figure 3 shows the G of a conventional hybrid integrated circuit.
A plan view of the mAa FET part, Figure 4 is the Y shown in Figure 3.
It is a sectional view taken along the -Y line. In the figure, (1) is an alumina substrate, a t21i die bonding pattern, (3) is a heat dissipation block, and (4) is a GaAa F
ET, (5 is the drain pattern, (6) is the gate pattern, (7) is the wire, (8) is the ground conductor, and (9) is the protrusion step. In addition, the same symbols in the figure are the same or equivalent. Show parts.
Claims (1)
上記ＧａＡｓ ＦＥＴと上記アルミナ基板の間に放熱ブ
ロックを有する混成集積回路において、上記放熱ブロッ
クの上記ＧａＡｓ ＦＥＴの取り付けられる面に突の段
差を設けたことを特徴とする混成集積回路。A gallium arsenide field effect transistor and an alumina substrate,
A hybrid integrated circuit having a heat dissipation block between the GaAs FET and the alumina substrate, characterized in that a protruding step is provided on a surface of the heat dissipation block to which the GaAs FET is attached.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63169606A JPH0218951A (en) | 1988-07-07 | 1988-07-07 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63169606A JPH0218951A (en) | 1988-07-07 | 1988-07-07 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0218951A true JPH0218951A (en) | 1990-01-23 |
Family
ID=15889614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63169606A Pending JPH0218951A (en) | 1988-07-07 | 1988-07-07 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0218951A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6062726A (en) * | 1996-03-18 | 2000-05-16 | The Board Of Trustees Western Michigan University | Method of identifying a substance by infrared imaging |
-
1988
- 1988-07-07 JP JP63169606A patent/JPH0218951A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6062726A (en) * | 1996-03-18 | 2000-05-16 | The Board Of Trustees Western Michigan University | Method of identifying a substance by infrared imaging |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1057411A (en) | Through-substrate source contact for microwave fet | |
| US4684975A (en) | Molded semiconductor package having improved heat dissipation | |
| JPH07312405A (en) | Semiconductor device | |
| US5583371A (en) | Resin-sealed semiconductor device capable of improving in heat radiation characteristics of resin-sealed semiconductor elements | |
| JPH04229643A (en) | High-frequency power semiconductor device and its manufacture | |
| JPH05218283A (en) | Semiconductor device | |
| JP2857648B2 (en) | Electronic component manufacturing method | |
| JPH0218951A (en) | Hybrid integrated circuit | |
| US3723833A (en) | Heat sinking of semiconductor integrated circuit devices | |
| JP2970693B2 (en) | Semiconductor device | |
| JP3003617B2 (en) | Resin-sealed semiconductor package | |
| JPS6180842A (en) | Semiconductor device | |
| JPH06112674A (en) | Heat sink for electronic part mounter | |
| JPS60154652A (en) | Semiconductor device | |
| JPH01293548A (en) | Semiconductor device | |
| TWI234853B (en) | Quad flat flip chip packaging process and lead frame | |
| JP2680110B2 (en) | Package for semiconductor device having heat radiator | |
| US20210175200A1 (en) | Semiconductor Die being Connected with a Clip and a Wire which is Partially Disposed Under the Clip | |
| JP2758888B2 (en) | Semiconductor device | |
| JPH01282846A (en) | Hybrid integrated circuit | |
| JP3302811B2 (en) | Microwave semiconductor device | |
| JPH07130932A (en) | Semiconductor device and its manufacture | |
| JP2692904B2 (en) | Semiconductor device with built-in diode chip and manufacturing method thereof | |
| JPH04207062A (en) | Semiconductor device and lead frame therefor | |
| JPH01165133A (en) | Semiconductor device |