JPH02188127A - Switchgear controller - Google Patents

Abstract

PURPOSE:To improve inertia characteristic by employing the average of data taken in within a predetermined time upon elapse of predetermined time after detection of zero-cross for switching control. CONSTITUTION:Zero-phase current and zero-phase voltage signals are full-wave rectified through filter/full-wave rectifiers 24, 25 thence fed through a level converter 26 to a CPU 4, and a zero-cross point is detected through a phase pulse circuit 27 and fed to the CPU 4. The CPU 4 samples the outputs from the level converter 26 for a time T2 upon elapse of time T1 after the zero-cross point, then the average value thereof is employed for switching control.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial application field This invention is applicable to 30G (Storage 0vert
The present invention relates to a currentG round ) type switching control device, particularly to a switch control device with improved inertial characteristics.

(b) Conventional technology In general, the device is connected to a three-phase load, detects excessive current and ground fault current, and when the ground fault current exceeds a predetermined level, current is applied to the trip coil to disconnect the switch. There is also an SOG type switch control device which, when an overcurrent is detected, causes a current to flow through a trip coil to disconnect the switch on the condition that the power is cut off.

Conventionally, this type of switch control device detects a ground fault using a ground fault signal detector such as a zero-sequence current detector or a zero-sequence voltage detector, and inputs the detected ground fault signal to a filter circuit. , high-frequency noise is removed, and the signal is further rectified using, for example, a full-wave rectifier circuit, smoothed using an effective value smoothing circuit, and taken into the CPU, and the taken-in detection signal is compared with a set value.

(c) Problems to be Solved by the Invention In the conventional switch control device described above, in order to input the input signal, that is, the ground fault signal, to the CPU, it is rectified by a rectifier circuit and smoothed by an effective value smoothing circuit. A/D conversion is being performed. This effective value smoothing circuit is equipped with an integration function including a capacitor. For example, if the signal shown in a of Figure 6 is input from the filter circuit to the rectifier circuit, this input signal is rectified by the rectifier circuit, and the effective value is The smoothing circuit outputs a signal shown in b in FIG. Here, a case is shown in which a ground fault occurs at time t1 and disappears at time t8. When a ground fault occurs, the output of the effective value smoothing circuit exceeds the set value 10 due to the ground fault signal.

In Fig. 6, when the ground fault disappears at time t2 (T,:
(the time when the ground fault existed), the output of the effective value smoothing circuit starts discharging, and immediately becomes less than or equal to summer, and after a further time TL, its output becomes ■. The following is true. In other words, it has inertia. Therefore, even though the ground fault has disappeared at TI, the output of the effective value smoothing circuit exceeds (2) over the period Ta +Tt. Therefore, the detection signal exceeds the set value 10. Therefore, for example, if T = 0.15 seconds, that is, the settling operation time is 0.15 seconds.
For example, when the ground fault occurrence period is TR = 0.10 seconds, which is actually shorter than the settling operation time,
Even if there is no need to shut off the switch, TL-0,0
In the case of 8 seconds, TI +Tt becomes 0.18 seconds, which causes the problem that the settling operation time T is exceeded and the switch control device operates.

This invention was made in view of the above-mentioned problems, and an object thereof is to provide a switch control device with small inertia.

(d) Means and operation for solving the problems The switch control device of the present invention includes a ground fault signal detector for detecting ground fault current of a three-phase bus, and a high-frequency component that receives the output of this ground fault signal detector. A filter circuit for removing the ground fault signal, a rectifier circuit for rectifying the output signal of this filter circuit, and a rectifier circuit that smooths the output of this rectifier circuit and takes in this ground fault signal as data, and and means for shutting off the bus switch in response to a determination output that the determination result by the determination means is equal to or higher than a set value, wherein the output of the rectifier circuit is zero cross detection means for detecting a zero cross; first timer means for counting a predetermined first time after the zero cross is detected by the zero cross detection means; a second timer means for timing a second time of the second time;
and a smoothing calculation means for calculating an average of sampling data of the output of the rectifier circuit taken in during a time period of , and the data calculated by the smoothing calculation means is used as discrimination data for the discrimination means.

In this switch control device, a ground fault signal detected by a ground fault signal detector passes through a filter circuit and is rectified by a rectifier circuit. Then, the zero cross of the output of the rectifier circuit is detected by the zero cross detecting means. After detection, wait for the first time to elapse, and then wait for the second time to elapse.
The output of the rectifier circuit is sampled and taken in a plurality of data within a time period of , and the plurality of data are averaged and the calculated signal is used as ground fault signal data for operation determination.

Since this device averages the sampling data of several times, as soon as the ground fault signal disappears, the data also becomes zero, which shortens the inertia. Furthermore, since data only within the second period of the half-period bone is used to perform the smoothing process, the memory capacity may be small.

(E) Examples The present invention will be explained in more detail with reference to Examples below.

FIG. 2 is a block diagram of an SOG type switch control device in which the present invention is implemented. In the figure, a zero-sequence current detector (zero-sequence current transformer) 2 and a zero-sequence voltage detector 3 are connected to a 6600V power supply system l, and zero-sequence current and zero-sequence voltage are detected, respectively. It looks like this. The zero-sequence current detected by the zero-sequence current detector 2 is converted into a voltage signal,
The signal is input to the CPU 4 via an input transformer 21 , an over-input protection circuit 22 , a test switching circuit 23 , a filter circuit 24 , a full-wave rectification circuit 25 and a level conversion circuit 26 .

Similarly, the zero-phase voltage detected by the zero-phase voltage detector 3 is transmitted to the voltage converter 3a, the input voltage transformer 31, the over-input protection circuit 32, the test switching circuit 33, the filter 34, the full-wave rectifier circuit 35, and the level converter 3a. It is input to the CPU 4 via the circuit 36.

The over-input protection circuit 22.32 is a circuit that has a function to suppress the detected zero-sequence current and zero-sequence voltage when they exceed a certain level, and the test switching circuit 23.33
input the zero-sequence current detection signal and zero-sequence voltage detection signal from the over-input protection circuits 22.32 to the filter circuits 24.34 during normal monitoring, and input the test signal in place of the detection signal during self-testing to the filter circuits 24.34. 34. Filter circuits 24 and 34 are provided to remove harmonic components. The full-wave rectifier circuits 25.35 are circuits for converting detection signals etc. into DC components, and the level conversion circuits 26.35 are circuits for converting detection signals etc. into DC components.
36 is a circuit for converting the signal into a signal suitable for import into the CPU 4. The rectified signal taken into the CPU 4 via the level conversion circuits 26 and 36 is sampled at short intervals, A/D converted, and smoothed by averaging. Then, it is used as input data for determining whether or not the average calculation result is greater than or equal to a set value. The phase pulse circuits 27 and 37 each input a pulse signal corresponding to the zero cross point of the output of the filter circuit 24 and 34 to the CPU 4 as a phase pulse signal, and calculate the phase in each of the zero-phase current detection system and the zero-phase voltage detection system. In addition, when detecting phase difference,
It is used for timing detection to calculate the average of detection signals. FIG. 3 shows the ground fault signal A containing harmonic components input to the filter circuit 24, the output B of the full-wave rectifier circuit 25, and the output C1 of the level converter circuit 26, which has level-converted this output B, the full-wave rectifier circuit. Each waveform of the output of the phase pulse circuit 27 which rises at the zero cross of the output of the phase pulse circuit 25 is shown.

The CPU 4 has a function of detecting the rising edge of a phase pulse, a function of measuring a first time from the rising edge of the pulse, and a function of measuring a second time, and a function of measuring the output of the level conversion circuit 26 in short cycles within the second time. It has the functions of sampling and A/D conversion, importing data, and calculating the average of data.

The setting circuit 5 has a setting value of zero-sequence current I0, zero-sequence current ■. This is a circuit for setting the setting value and setting time T of D.
The C test switch 6a is a manual switch for performing a ground fault test, and the SO test switch 6b is a manual switch for performing an overcurrent test. The display section 7 shows ■. Equipped with level display, power display, and forecast display. The output section 8 is equipped with a DG display due to ground fault detection and an SO display due to overcurrent, and also includes a relay for tripping in the event of a ground fault, a relay for tripping in the event of overcurrent, a relay for forecasting, an abnormality relay, etc. It is equipped with

The CPU 4 also includes a test signal generation circuit 9 and a test circuit.
A diagnostic circuit IO is attached. The test signal generation circuit 9 is
For example, a four-stage self-test current signal 10 and a self-test voltage signal v0 are generated.

Current signal ■. is input to the test switching circuit 23, and the voltage signal v0 is input to the test switching circuit 33.

The test circuit/diagnostic circuit 10 is a general term for various diagnostic/test functions executed by the CPU 4, such as a constant voltage check function, a contact check function, a TC check function, and an inertia function check.

In addition, this switch control device includes a filter circuit 11, a constant voltage circuit 12, and constant voltage level conversion circuits 13 and 14 as its own power supply section.

Note that a commercial power supply voltage is applied to the terminals P+ and Pg, and a trip coil for interrupting the switch of the power supply system I is connected between the terminals V, , and V. The TC detection circuit 15 is a circuit for detecting that a trip coil is connected to the terminals V, , V,.

Next, the smoothing processing operation of the detection signal in the switch control device will be explained with reference to the flowchart shown in FIG.

When the operation starts, first, it is detected whether the output of the phase pulse circuit 27 has risen (step 5TI). When the rising edge of the phase pulse is detected, this time point indicates the zero-crossing point of the detection signal, and at this point, timer T is started (step 5T2), and a time wait is performed until timer TI times up (step 5T2). Step 5T3
), the setting time of timer T+ is a period in which the waveform changes sharply from the zero cross point of the detection signal, as shown in FIG. is not loaded.

Eventually, when timer T times out, step S
The determination at T3 becomes YES, and timer Tz is started (step 5T4). This timer T! The setting time is set to define the vicinity of the peak of the detection signal, as shown in FIG. During the period from when the timer Tt starts until it times up, that is, during the period T2, the output of the level conversion circuit 26, that is, the detection signal, is sampled, A/D converted, and taken in by the CPU 4. The captured data is then stored in the memory within the CPUd (step S
T5.5T6). During period T8, sampling is performed several times (n times) as shown in FIG. 5, and n pieces of data are stored in the memory. When Kuima T Yuki's time is up, n
The average calculation is performed for each piece of data, the calculation result is used as detection signal data, and the process returns (step 5T7). When this detection signal data is calculated, the current setting value ■. compared to
Detection signal! . Similarly, in the case of the voltage signal system, if the detection signal exceeds the set value v0 and this state exceeds the operation establishment time T, the switch of the power supply system I will be cut off. Furthermore, the operation of the voltage signal processing system is
This is the same as the current signal processing system described above.

(F) Effects of the Invention According to the present invention, the zero cross detection means detects the zero cross of the output of the rectifier circuit, and only within the second time period after the first time has elapsed from this zero cross point, the rectifier circuit detects the zero cross of the output of the rectifier circuit. The output is sampled and captured, the average value of the plurality of level data captured within the second time period is determined by the average value calculation means, and the calculation result is used as the detection signal signal. As soon as it becomes zero, subsequent level data also becomes zero, and the average calculation result also becomes zero in response, resulting in good inertial characteristics. Furthermore, since the detection signal data is obtained by sampling only at the second time near the peak of the half cycle of the detection signal, the memory capacity for data storage is small, making it possible to obtain an inexpensive switch control device. can.

[Brief explanation of the drawing]

FIG. 1 is a flow diagram for explaining the smoothing process of a detection signal of an SOG type switch control device showing an embodiment of the present invention, and FIG. The overall block diagram, FIG. 3 is a diagram for explaining the input and output waveforms of the main circuit of the same SOG type switch control device, and FIG. 4 shows the half cycle of the detection signal, the first time TI, second time T
FIG. 5 is an enlarged view of the second time T: portion of the waveform diagram showing the relationship between wealth. FIG. 6 is an explanation of a problem in the effective value smoothing circuit used in a conventional switch control device. FIG. 1: Power supply system, 2: Zero-phase current detector, 3: Zero-phase voltage detector, 4: CPU, 24/34: Filter circuit, 25/35: Full-wave rectifier circuit, 27/37: Phase pulse circuit.

Claims (1)

[Claims] (1) A ground fault signal detector that detects the ground fault signal of the three-phase bus, a filter circuit that receives the output of this ground fault signal detector and removes high frequency components, and rectifies the output signal of this filter circuit. A rectifier circuit, a means for smoothing the output of the rectifier circuit, taking in the ground fault signal as data, and determining whether or not the ground fault signal is equal to or higher than a preset value, and a determination result by the determination means being set. In the switch control device, the switch control device includes means for shutting off the switch of the bus bar in response to a determined output that the output is greater than or equal to a value, and a zero cross detection means for detecting a zero cross of the output of the rectifier circuit; first timer means for timing a predetermined first time after a zero cross is detected by the means;
second timer means for counting a predetermined second time after the first time has elapsed; and smoothing calculation means for calculating an average of sampling data of the output of the rectifier circuit taken within the second time. A switch control device characterized in that the data calculated by the smoothing calculation means is used as discrimination data for the discrimination means.