JPH02186280A - Integrated circuit apparatus - Google Patents

Abstract

PURPOSE:To facilitate a self test by a method wherein a testing signal is stored into a memory while a desired processing is performed by a first processing means and an output thereof is compared with a data of the memory after effecting an opposite processing by a second processing means. CONSTITUTION:A testing signal generated by a pattern generation means 117 is stored into a memory means 115 while undergoing a desired processing, for example, a series-parallel conversion by a first processing means 111 to output. The resulting output signal is inputted into a second processing means 113, there it undergoes a processing opposite to that by the first processing means 111, namely, a parallel-series conversion to output. An output thus obtained is compared with a data of a memory means 115 by a discrimination means 119 and when both the data coincide, the output is determined good and otherwise, it is determined to be bad. A circuit apparatus thus obtained is ideal for the testing of an integrated circuit.

Description

[Detailed Description of the Invention] [Summary] For the purpose of easily testing an integrated circuit device used for 16-channel multiplex transmission, for example, the first input signal is subjected to desired processing and the first output signal is a first processing means for outputting as a signal; a second processing means for performing processing opposite to the processing of the first processing means on the second input signal and outputting the resultant as a second output signal; and storing input data. A predetermined relationship is established between the storage means for performing the self-test, the pattern generation means for generating test data for the self-test and supplying it to the first processing means and the storage means, the output data of the second processing means, and the data stored in the storage means. a discriminating means for discriminating whether or not the test data is processed by the first processing means, and comparing the processed data by the first processing means with the reprocessed output data obtained via the second processing means and the test data stored in the storage means. Configure the system so that it can be identified and self-tested.

[Industrial application field]

The present invention relates to an integrated circuit device, and more particularly, to an integrated circuit device used for 16-channel multiplex transmission, for example.

[Conventional technology]

FIG. 3 shows an example of a conventional integrated circuit device having a transmission function and a self-test function. In the figure, the conventional device consists of a transmission processing section 311 and a self-test processing section 321.
The self-test processing section 321 includes a pattern generator 323. It consists of a memory circuit 325 and a discrimination circuit 327.

The pattern generator 323 transmits the test data to the transmission processing unit 3.
11 and a storage circuit 325 in common. In addition to transmitting data, which is the original function of the device, the transmission processing section 311 also receives data supplied from the pattern generator for self-testing and sends it to the discrimination circuit 327. Discrimination circuit 3
In step 27, the data to be transmitted when the transmission processing section 311 operates correctly is determined from the test data stored in the storage circuit 325, and the data is compared and determined with the data actually transmitted by the transmission processing section 311. Judge your own good or bad.

[Problem to be solved by Invention C] By the way, since integrated circuit devices that have both transmitting and receiving functions do not have a self-test function, it is necessary to provide a complicated tester to test such devices. there were. In addition, there was a problem in that the test results for abnormal data had little credibility because the generated data were not clear.

The present invention was created in view of these points, and an object of the present invention is to provide an integrated circuit device that facilitates testing.

[Means to solve the problem]

FIG. 1 shows a principle block diagram of an integrated circuit device according to the invention.

In the figure, the first processing means Ill performs desired processing on the first input signal and outputs it as a first output signal.

The second processing means 113 performs processing opposite to that of the first processing means 111, and processes the second input signal and outputs it as a second output signal.

Storage means 115 stores data input therein.

The pattern generation means 117 generates test data for self-testing, and the first processing means 111 and the storage means 11
Supply to 5.

The determining means 119 determines whether a predetermined relationship is established between the output data of the second processing means 113 and the data stored in the storage means 115.

Therefore, as a whole, the test data is processed by the first processing means 11.
After processing in step 1, the data is processed again in second processing means 113 and compared with test data.

C Effect] When performing a self-test, test data (for example, parallel data) is generated from the pattern generation means 117 and supplied to the first processing means 111 and the storage means 115. The storage means 115 stores this test data. Further, the first processing means 111 performs desired processing (for example, parallel-serial data conversion processing), and the output data is sent to the second processing means 111.
Processing in step 13 (e.g. serial-parallel data conversion processing)
be done. Furthermore, the output data of the second processing means 113 is compared with the test data stored in the storage means 115 to determine whether a predetermined relationship (for example, both data match) is established between the two data. Discern.

In the present invention, test data is continuously processed by the first processing means 111 and the second processing means 113, which perform mutually contradictory processing, and if normal, the output of the second processing means 113 Since the data has been restored to test data, self-testing can be easily performed with a simple configuration.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an integrated circuit device in one embodiment of the present invention.

1, and 1 Here, the correspondence between the embodiments of the present invention and FIG. 1 will be shown.

The first input signal corresponds to data to be transmitted sent from the CPU (not shown).

The first output signal corresponds to the transmission data transmitted by the transmission data processing section 223.

The first processing means 111 includes the transmission control section 221. It corresponds to the transmission data processing section 223.

The second input signal corresponds to reception target data sent to the reception data processing unit 233 from the outside (not shown).

The second output signal corresponds to received data sent to the CPU.

The second processing means 113 includes the reception control section 231. This corresponds to the received data processing section 233.

The storage means 115 corresponds to the storage circuit 241.

The pattern generating means 117 corresponds to the pattern generator 243.

The determining means 119 corresponds to the determining circuit 245.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

The integrated circuit device shown in FIG. 2 performs parallel-to-serial conversion of one byte of data, and has transmission and reception functions. In the figure, the integrated circuit device according to the embodiment is
An ink face section 211 that exchanges data with a CPU (not shown), a transmission control section 221 that measures the timing of transmission, and a transmission data processing section 223 that performs parallel-to-serial conversion of data and transmits the data. A reception jlil control unit 231 that measures reception timing, a reception data processing unit 233 that performs serial-parallel conversion of data and receives data, and a storage circuit 241 that stores test data.
and a pattern generator 243 that generates test data.
It is composed of a discrimination circuit 245 for obtaining test results.

The interface unit 211 supplies data to be transmitted to the transmission data processing unit 223, and conversely, the data to be transmitted is supplied to the reception data processing unit 2.
33 supplies the received data to the CPU.

The signal line through which the transmission data processing unit 223 transmits data and the signal line through which the reception data processing unit 233 receives data are common, and a half-duplex bidirectional buffer (not shown) is connected to the end of the signal line. There is.

A clock signal is commonly supplied to the transmission control section 221 and the reception control section 231. The transmission control section 22 has an interface section 211. A processing timing signal is sent to the transmission data processing section 223 and the reception data processing section 233. The reception control section 231 controls the interface section 2 and 1. A processing timing signal is sent to the received data processing section 245.

The pattern generator 243 supplies data to the transmission data processing section 223 and the storage circuit 241 in common.

The transmission data processing unit 223 supplies data to the outside of the device (not shown) or to the reception data processing unit 233.

The received data processing section 233 supplies the received data to the interface section 211 or the discrimination circuit 245. Further, when a transmission/reception is performed, a confirmation signal representing the transmission/reception is sent to the outside (not shown).

The determination circuit 245 compares and determines the data supplied from the storage circuit 241 and the received data processing section 233, and outputs the result.

The operation of the integrated circuit device of the f-needle 1 embodiment consists of a transmission/reception function, which is the original function of the circuit, and a self-test function for the circuit.

Furthermore, all components of the integrated circuit device of the embodiment are reset by a reset signal (not shown) when power is turned on.

-Lilu Original operation ■ Transmission operation The interface unit 211 transfers the 8-bit transmission target data sent from CP tJ to the transmission data processing unit 223. The transmission data processing unit 223 performs parallel-to-serial conversion on the data and outputs it as transmission data. At this time, the transmission data is not transmitted to the reception data processing section 233.

■Reception operation The reception data processing unit 233 converts the reception target data sent from the outside into serial-parallel data and sends it to the interface unit 21.
Send to 1. The interface unit 211 sends the received data to the CPU. At this time, the received data processing unit 233 does not transmit the received data to the determination circuit 245.

ii) The self-test function is performed, for example, immediately after ta is turned on and the circuit enters the reset state, and before the circuit's original operation is started.

First, the pattern generator 243 generates test data and supplies it to the transmission data processing section 223 and the storage circuit 241 in common. At this time, the transmission data control section 241 notifies the reception data processing section 233 that the test data has been received.

The data processing unit 223 transmits the supplied data in parallel.
The data is serially converted and supplied to the received data processing section 233. The reception data processing unit 233 performs serial-parallel conversion on the data supplied from the transmission data processing unit 223 to restore the original data and supplies it to the discrimination circuit 245 . The determination circuit 245 compares the data stored in the storage circuit 241 with the data transmitted by the received data processing unit 233 to determine whether it is good or bad, and outputs the result. Since the received data processing unit 233 performs serial-parallel conversion on the data that has been parallel-to-serial converted by the transmission data processing unit 223, the device is determined to be normal when the two values match.

Note that during the self-test, the transmission data processing section does not output transmission data to the outside, and the reception data processing section does not transmit reception data to the interface section 211.

In this way, since the integrated circuit device performs a self-test on both the transmitting and receiving functions, testing of the device becomes easy.

Note that in the embodiment of the present invention described above, data transmitted and received in one byte is handled, but the data is not limited to this.

Note that the present invention is also applicable to devices having opposite functions, for example, the function of the transmission data processing section 223 is modulation processing and the function of the reception data processing section 233 is demodulation processing.

Furthermore, in "1. Correspondence between Examples and FIG. 1",
Although the correspondence between FIG. 1 and the present invention has been described, those skilled in the art will easily imagine that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As mentioned above, the present invention facilitates testing of the device by providing a self-test function in one device with two diametrically opposed functions, which is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the integrated circuit device of the present invention, and FIG.
The figure is a block diagram of the structure of an integrated circuit device according to an embodiment of the present invention, and FIG. 3 is an explanatory diagram of a conventional example. In the figure, 111 is a first processing means, 113 is a second processing means, 115 is a storage means, 117 is a pattern generation means, 119 is a discrimination means, 1 is an interface section, 1 is a transmission control section, 3 is a transmission data processing section , 1 is a reception control section, 3 is a reception data processing section, 1.325 is a storage circuit, 5.327 is a discrimination circuit, 3323 is a pattern generator, 1 is a transmission processing section, and l is a self-test section. Read the book 7 days a week! , 哩7゛ro 7

Claims (1)

[Claims] (1) A first processing means (111) that performs desired processing on a first input signal and outputs it as a first output signal; and processing of the first processing means (111) on a second input signal. a second processing means (113) for performing processing opposite to the above and outputting it as a second output signal; a storage means (115) for storing input data; a pattern generating means (117) that supplies the first processing means (111) and the storage means (115);
a determining means (119) for determining whether a predetermined relationship is established between the output data of the test data (113) and the data stored in the storage means (115);
111) is processed by the second processing means (113).
) and the test data stored in the storage means (115),
An integrated circuit device characterized in that it is configured to perform a self-test.