JPH0630078A - Line connection information readout circuit - Google Patents

Abstract

PURPOSE:To efficiently check the connection information of a line when abnormality occurs in the line connecting state of a device by adding a circuit which reads out a connection destination address from a connection origin address on a line connection information readout circuit. CONSTITUTION:The readout of connection destination address information 13 is performed by outputting a control origin address signal 9 by a control part 1. A comparator 10 compares the signal 9 with a connection origin address 8 outputted from control memory 2, and outputs a coincidence pulse 12 to a data holding circuit 11 only when coincidence is obtained between them. At this time, the connection destination address 7 generated by a counter 6 represents the connection destination address desired to read out. The data holding circuit 11 holds the connection destination address 7 at the generating timing of the coincidence pulse 12, and sends it out to the control part 1 as the connection destination address information. Thereby, it is possible to read out the connection destination address from the connection origin address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication function of monitoring / control information in an interface between software and hardware in the fields of digital communication, data transmission and the like.

[0002]

2. Description of the Related Art A conventional line connection information read circuit generates a connection destination address signal 3 and a CM (control memory) read control signal 4 and inputs connection source address information 5 as shown in FIG. It has a section 21 and a control memory (CM) 22 which receives the connection destination address signal 3 and the CM read control signal 4 and outputs the connection source address information 5. The control unit 21 reads the connection source address information 5 which is the CM data from the CM 22 by giving the connection destination address signal 3 which is the access address of the CM 2 together with the CM read control signal 4.

[0003]

This conventional line connection information read circuit has a circuit configuration in which the connection source address information 5 is read by giving a connection destination address signal 3 from the control unit 21 to the CM 22. . Therefore, when trying to read the connection status of the line during maintenance and operation of the device, the connection source can be read from the connection destination, but conversely, the connection destination cannot be read from the connection source, which is efficient. There is a problem that can not be investigated.

[0004]

SUMMARY OF THE INVENTION A line connection information reading circuit according to the present invention comprises a connection destination address representing a connection destination of a line connection, a counter which is sequentially generated while going round, and each address corresponding to the connection destination address. Control memory for sequentially reading and outputting the connection source address, a control unit for transmitting a connection source address signal to be accessed and receiving connection destination address information corresponding thereto, and each of the control memory and the control unit for transmitting. A comparator that outputs a match pulse only when both of them match when receiving a connection source address signal, and a data holding that holds the connection destination address generated from the counter at the timing of the match pulse and outputs it as the connection destination address information And a circuit.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the interface between the control unit 1 and the control memory (CM) 2, the connection destination address signal 3 from the control unit 1 to the CM 2 is the same as in the conventional circuit of FIG.
Then, the CM read control signal 4 is supplied and the connection source address information 5 is read from the CM 2. In the present embodiment, in addition to this, by adding the circuit described below, the connection destination address can be read from the connection source address.

The counter 6 sequentially supplies the CM 2 with a connection destination address 7 which is an address that advances and circulates as a CM address, and the CM 2 sequentially outputs a connection source address 8 which is CM data of each address. Here, the connection destination address 7 is also a data write address for the data holding circuit 11 which is a data memory, and the connection source address 8 is also for reading data from the data holding circuit 11.

When reading the connection destination address information, the control unit 1 first outputs the connection source address signal 9. The comparator 10 compares the connection source address signal 9 with the connection source address 8 output from the CM 2, and outputs the coincidence pulse 12 to the data holding circuit 11 only when they coincide with each other. At that time, the connection destination address 7 generated by the counter 6 represents the connection destination address to be read. The data holding circuit 11 holds the connection destination address 7 at the generation timing of the coincidence pulse 12 and sends it as the connection destination address information 13 to the control unit 1.

As a result, the connection destination address can be read from the connection source address.

[0010]

As described above, according to the present invention, a circuit for reading the connection destination address from the connection source address is added to the conventional line connection information reading circuit, so that the connection source can be connected from the connection destination during maintenance and operation of the device. It is possible not only to read the connection destination, but also to read the connection destination from the connection source. Therefore, when an abnormality occurs in the line connection state in the device for some reason, the connection information of the line can be investigated very efficiently. Further, in the present invention, since the connection destination is read while directly monitoring the connection source address which the control memory (CM) constantly gives to the data holding circuit (DM), the reliability of the read data is high, and the CM at the time of reading is high. Since there is no need for access to the DM, there is an advantage that the influence on the connection source address transmitted to the DM can be completely ignored.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional circuit.

[Explanation of symbols]

 1, 21 Control unit 2, 22 Control memory (CM) 3 Connection destination address signal 4 CM read control signal 5 Connection source address information 6 Counter 7 Connection destination address 8 Connection source address 9 Connection source address signal 10 Comparator 11 Data holding circuit 12 Match pulse 13 Destination address information

Claims (1)

[Claims] 1. A counter that sequentially generates a connection destination address that represents a connection destination of a line connection while stepping, and a control memory that sequentially reads and outputs a connection source address of each address according to the connection destination address. Matches only when the control unit that transmits the connection source address signal to be accessed and receives the corresponding connection destination address information and the connection source address signals sent by the control memory and the control unit are matched. A line connection information read circuit, comprising: a comparator that outputs a pulse; and a data holding circuit that holds the connection destination address generated from the counter at the timing of the matching pulse and outputs the data as the connection destination address information. .