JPH0425955A - Bus interface diagnosis device - Google Patents

Abstract

PURPOSE:To obtain a bus interface diagnosis device where the diagnosis of a bus interface and the specification of a suspected device and a suspected chip become easy by comparing the value of arbitrary data held in a holding part and that of data in a comparison part. CONSTITUTION:In the bus interface diagnosis device 30, a control part 5 supplies a clock pulse from a clock pulse supply part 1 to a reception-side device 10 one pulse by one, a reception register 14 is caused to transmit and set the value of a transmission register 25 through a bus driver 21, a bus 40 and a bus receiver 16. Then, the value of the reception register 14 is fetched into the holding part 3 (scan register) in the diagnosis device 30 from a scan path 39 and the fetched value of the reception register 14 is compared with the value which is set in the transmission register 25 of a transmission-side device 20, which is fetched into the holding part 3 in a scan path line 39 and which is recognized in the comparison part 4. Thus, there is an effect that the diagnosis of the bus interface and the specification of the suspected device and the suspected chip become easy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device comprising a receiving device and a transmitting device, and more particularly to a bus interface diagnostic device for diagnosing a bus interface.

[Conventional technology]

In conventional information processing devices, when diagnosing a bus interface, a device that outputs log information is connected to the bus of the information processing device, and the information processing device is actually operated.

If there is a failure in the bus interface, the clock is stopped in response to notification of the failure occurrence, and the status values of storage elements such as registers of each device are output as log information.

[Problem to be solved by the invention]

In the conventional information processing device described above, bus interface diagnosis is performed by operating a device that outputs log information and based on the log information output when a failure occurs. There was a drawback that it was difficult to identify the location, that is, the suspect chip.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a bus interface diagnostic device that eliminates the above-mentioned drawbacks and allows easy diagnosis of bus interfaces, suspect devices, and suspect chips.

[Means to solve the problem]

The present invention is a bus interface diagnostic device for diagnosing a bus interface of an information processing device in which a sending device and a receiving device transfer data via a bus, the device providing clock pulses to the sending device and the receiving device. a clock pulse supply unit for setting specific data and arbitrary data to the transmitting side device and the receiving side device;
It has a holding section that holds data, a comparison section that compares the values of the held data, and a control section that controls the clock pulse supply section, the data setting section, the comparison section, and the holding section. The setting section sets specific data in the registers of the sending device and the receiving device to enable transmission and reception, and the arbitrary data set in the sending device from the data setting section and the clock pulse transfer the arbitrary data to the sending device. The bus interface is diagnosed by holding the data transmitted from the storage unit to the receiving device in a holding unit, and comparing the values of the arbitrary data held in the holding unit and the data in a comparing unit. do.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing one embodiment of the present invention.

This bus interface diagnostic device includes a clock pulse supply section 1, a data setting section 2, a holding section 3, a comparison section 4, and a control section 5.

The clock pulse supply section 1 supplies clock pulses for operating an information processing apparatus consisting of a receiving side device and a transmitting side device.

The data setting unit 2 sets arbitrary data for checking the bus interface in the register of the sending device. Further, specific data such as "1" is transmitted to enable the bus driver of the transmitting device and to always set the reception register of the receiving device to a valid state. Then, the receiving side device and the sending side device are placed in a state where they can transmit and receive data.

The holding unit 4 holds arbitrary data set in the sending device and scan-out data transmitted from the sending device to the receiving device and taken in from the receiving device after setting in the sending device. Send to.

The comparing unit 4 compares arbitrary data set in the transmitting side device from the holding unit 3 and data fetched from the receiving side device,
Detect discrepancies. Since the arbitrary data set in the sending device and the data transmitted from the sending device to the receiving device and retrieved from the receiving device have the same value, it is possible to prevent a failure at the bus interface from a mismatch in these data. Can be judged.

The control section 5 includes a clock pulse supply section 1. Data setting section 2
．． Holding part 3. Comprehensively controls the comparison section 4.

FIG. 2 is a diagram showing the connection of specific devices for bus interface diagnosis according to this embodiment.

The bus interface diagnostic device 30 is connected to the receiving device 10, the transmitting device 20, a clock pulse distribution line 3233, a shift mode line 34, and a scan line 35.3839. The receiving device 10 includes a receiving register control circuit 11, a selector 12, a register 13, a receiving register 14, and a bus receiver 15, and the transmitting device 2
0 is a bus driver 21, a selector 22, a bus driver control circuit 23, a register 24, and a sending register 2.
4. Although not shown, it is assumed that there are a plurality of transmitter devices 2o.

The transmitting side device 20 and the receiving side device 1o are the bus driver 2
The output of I and the input of bus receiver 15 are connected via bus 4o. Further, the receiving register 14 and register 13 of the receiving unit ff1o and the register 24 and sending register 25 of the transmitting side device 20 are connected by scan lines 36 and 37. The scan line 35 of the bus interface diagnostic device 30 is connected to the receiving device 10.
The receiving register 14 of the transmitting device 20 and the register 24 of the transmitting device 20
is connected to. Also, the bus interface diagnostic device 3
The 0 scan canvas line 39 is connected to the output of the register 3 of the receiving device 10, and the scan canvas line 38 is connected to the output of the sending register 25 of the transmitting device 20.

In addition, the clock distribution lines 32 and 33 supply clock pulses for transmitting and receiving operations from the clock pulse supply unit 1 to the receiving side device IO and the transmitting unit W20, and
5 sets arbitrary data and specific data from the data setting unit 2 to the sending device 20 and the receiving device 10, and scan lines 38 and 39 set arbitrary data and specific data from the data setting unit 2 to the sending device 10 and the sending device 2.
The data set in the 0 register is taken into the holding unit 3.

Next, the operation in bus interface diagnosis of this embodiment will be explained with reference to FIGS. 1 and 2.

When diagnosing the bus interface, in the bus interface diagnostic device 30, the control unit 5 scans arbitrary data into the sending register 25 of the sending unit ff20 and specific data, for example, °゛1' into the register 24, from the data setting unit 2. Setting via bus lines 35.37.

Furthermore, any data set in the transmission register 25 is fed back via the scan line 38 to the holding unit 3.
to hold. Then, it is confirmed whether the arbitrary data is correctly set in the transmission register 25. At this time, the sending device 2
0. The receiving device 10 is in a state where the external clock is stopped during the scan operation.

From the bus interface diagnostic device t30 to the sending device 2
Since the specific data "l" is set in the register 24 of 0, the selector 22 selects the value of the register 24, and the bus driver 21 becomes enabled.

On the other hand, in the bus interface diagnostic device 30, the control unit 5
The scan line 35 is stored in the register 13 of the receiving device 10.
．． By setting the specific data "'1111" through 36, selector 2 is moved to the register 13 side,
The reception register 14 is always set to a valid state. Then, the receiving device 10 and the transmitting device 20 become ready for transmission and reception.

In the bus interface diagnostic device 30, the control section 5 supplies clock pulses one by one from the clock pulse supply section 1 to the receiving side device 10, and transmits the value of the sending register 25 to the receiving register 14 through the hash driver 21. Bus 40. It is transmitted and set via the bus receiver 16. Then, the value of the reception register 14 is taken into the holding unit 3 (scan register) in the diagnostic device 30 from the scan canvas line 39, and the value of the reception register 14 and the transmission side device 2 are taken in.
0 in the sending register 25 and fetched into the holding unit 3 via the scan canvas line 39 f! The comparator 4 compares the detected value with the recognized value.

The above operation is performed multiple times with different data patterns, and the same operation is also performed for other sending devices. For example, the sending register 25. Assuming that the reception register 14 is 4-bit data, the setting data is "'0001'",
"0010", oioo'", and "1000", for example, are combined with the four sending devices by changing the data pattern. As a result, if only "1000" is a mismatch between each device, Bus 40. Bass receiver 16. any bin of the reception register 14)
If the fault is fixed at "1'" in O, and if the mismatch is only for a specific sending device, the fault is fixed at "1" in bit 0 of the bus driver 21 of that sending device. can be determined.

[Effects of the Invention] As explained above, the present invention sets arbitrary data in the sending register of an arbitrary sending device when diagnosing a bus interface, advances the clock pulse, and transfers this data to the receiving register of the receiving device. By comparing this value with the value of the data set in the sending register while changing the setting data pattern and the sending device, it is easy to diagnose the bus interface and identify the suspect device and suspect chip. There is a certain effect.

[Brief explanation of the drawing]

FIG. 1 is a functional plot diagram according to an embodiment of the present invention, and FIG. 2 is a diagram showing specific connections in bus interface diagnosis using the device of FIG. 1. 1... Clock pulse supply section 2...; Data setting section 3... Holding section 4... Comparison section 5... Control section

Claims (1)

[Claims] (1) A bus interface diagnostic device for diagnosing a bus interface of an information processing device in which a sending device and a receiving device transfer data via a bus, the device supplying clock pulses to the sending device and the receiving device. a clock pulse supply unit; a data setting unit that sets specific data and arbitrary data to the sending device and the receiving device;
It has a holding section that holds data, a comparison section that compares the values of the held data, and a control section that controls the clock pulse supply section, the data setting section, the comparison section, and the holding section. The setting section sets specific data in the registers of the sending device and the receiving device to enable transmission and reception, and the arbitrary data set in the sending device from the data setting section and the clock pulse transfer the arbitrary data to the sending device. The bus interface is diagnosed by holding the data transmitted from the storage unit to the receiving device in a holding unit, and comparing the values of the arbitrary data held in the holding unit and the data in a comparing unit. bus interface diagnostic equipment.