JPH0218615A - Dividing circuit - Google Patents

Abstract

PURPOSE:To perform the non-recovery type division at a high speed via a logic circuit that decides the quotient by securing a circuit constitution where an adder is set outside a process loop which decides the quotient. CONSTITUTION:A multiple circuits 101 and 104 produce the multiples of a divisor 110 and the adders 105 are prepared every multiples produced by the circuits 101 and 104 respectively. The output of a logic circuit 107 that decides the quotient does not exist in the processes up to the output of an adder group 109. Thus the arithmetic results of the group 109 can be obtained before the output of the circuit 107. One of the outputs of the group 109 is selected by a selector circuit 106 and used as the input of the circuit 107. In such a case, the circuit 106 is controlled by the output of the circuit 107 and therefore the group 109 is not included in a process loop that decides the quotient. Thus the non-recovery type division is carried out by the circuit 107 at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a non-recovery division circuit, and more particularly to a non-recovery division circuit in which logic for determining a quotient has redundancy.

[Conventional technology]

When performing division using a digital circuit, the following method is basically used.

When Ro is the dividend and D is the divisor, the division RO:D sequentially executes the following arithmetic processing.

R1,=r (Ro −Qo D) R2=r (R+ −(h D) R3=r (R2−q2 D) 2° (n is an integer). R1, R2, R3, ..., Ri, ... are called partial remainders. Qo, Ql, Q2, ..., qi.

... represents the quotient. Ra must take a value within a certain defined range, and at the same time this constraint is a condition for determining qi.

In the case of a division method where there is redundancy in the logic that determines the quotient (
For example, the division method of RObertSOn), Ri and D do not require full bit length precision. This is because R1 and D are allowed to have errors within a redundant range.

FIG. 2 is a block diagram showing the basic configuration of a conventional division circuit of this type.

A multiple generation circuit 201 manually generates a divisor (D) 206 and generates a multiple 207. The selector circuit 202 selects a multiple (q
zD) 208 and output it. Output (qiD) 208 of selector circuit 202 and partial remainder (fault) 209
enters the adder 203, where Rz - qJ D is calculated. Although this operation is a subtraction, the circuit that performs the subtraction is essentially an adder. Nothing special is said below. The addition result RjQzD is shifted to the next partial remainder (Rt-
+)210 and is output. Partial remainder (Rt÷1)
Of 210, bits 211 necessary to determine the quotient
is input manually to the logic circuit 204 that determines the quotient, and the quotient (qi
++) 212 is generated. Quotient 212 is high storage circuit 2
05, it simultaneously becomes a selector circuit 2020 control signal.

[Problem to be solved by the invention]

In the conventional division circuit described above, after qi-+ is determined,
Before the next Qi is determined, arithmetic processing is performed by the adder and the logic circuit that determines the quotient, but both the adder and the logic circuit that determines the quotient are circuits that require a lot of processing time. Moreover, since the adder and the logic circuit that determines the quotient are included in the processing loop, delays cannot be absorbed by the previous or next stage circuit, which limits the processing speed of the entire system. There is a drawback.

[Failure to solve the problem]

The division circuit of the present invention includes: a first multiple generation circuit that inputs a divisor and generates a multiple of the divisor; and a first selector circuit that selects a quotient from among the multiples and outputs the specified multiple. an adder that inputs the output of the first selector circuit and the partial remainder, adds them together, shifts them, and outputs the next partial remainder; and bits necessary for determining the quotient of the divisor. and a second multiple generation circuit that generates a multiple by inputting a plurality of adders that input the dots necessary to determine the quotient and add them; and a second selector circuit that selects the addition result specified by the quotient from among the addition results of the plurality of adders. , and a logic circuit that receives the output of the second selector circuit and generates the liquid.

(Operation) The division circuit of the present invention has an adder for each multiple generated by the circuit that generates multiples of the divisor.In the processing process up to the output of this adder group, the output of the logic circuit that determines the quotient is There is no intervention.Therefore, the result of the operation by the adder group can be obtained without waiting for the output of the logic circuit that determines the quotient.The output of the adder group, one of which The selector circuit is selected and becomes the input to the logic circuit that determines the quotient.However, this selector circuit is (VI11'@) by the output of the logic circuit that determines the quotient.Therefore, the adder group is included in the processing loop that determines the quotient. Not included.

Note that the circuit for generating the multiple of the divisor, the adder group, and the selector circuit mentioned here will only require 1 minute if they can handle data of the bit length necessary to determine the quotient.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the division circuit of the present invention.

A multiple generation circuit 101 manually generates a divisor (D) 110 and generates a multiple 111 of D. The selector circuit 102 is a multiple of 11
The multiple (q) specified by the quotient (insect) 121 from 1
zD) and output it. Selector circuit 102
The output (qzD) 112 and the partial remainder (Rz) 113 enter the adder 103, where R,jQtD is calculated.

The addition result RiQLD is shifted to the next partial remainder (R
ob) 114. At the same time, the divisor <D>
Bits 115 of 110 necessary for determining the quotient are input to the multiple generation circuit 104, where a multiple 116 is generated. This multiple 116 becomes the human power of the adder 105 prepared for each multiple. Also, partial remainder (RJ,)1
Among the bits 13 and 117 necessary for determining the quotient, the bit 117 is also input to the adder 105.

In the adder 105, respectively...RJI-2D, R-10.

Fu, Rj, -D, Rj-2D, . . . are calculated. Among these addition results, the addition result Fu −Qt D specified by the quotient (QJ) 121 is the selector circuit 106
selected by Output 119 of selector circuit 106
is input to the logic circuit 107 that determines the quotient, where the quotient (
Qi÷+)120 is generated. The quotient 120 is stored in the quotient storage circuit 108 and at the same time becomes a control signal for the selector circuit 102 and the selector circuit 106.

Note that it is effective to use a C8A (an adder that does not propagate carry) as the addition circuit used in the adder 103 when the bit length of the data to be handled is long. However, if the adder 105 is configured with only C8A, the logic circuit 107 that determines the quotient will become large-scale, so it is more realistic to use a CPA (adder that propagates carry) in addition. It is. In addition, the logic circuit 1 that determines the quotient
07 is PLA (Programmable
LogicArray) or ROM (Read
0nly Memory) etc. are used. The multiple generation circuits 101 and 104 consist of a shift circuit and an inverter circuit.

〔Effect of the invention〕

As explained above, the present invention has a circuit configuration in which the adder is outside the processing loop that determines the quotient. This has the effect of allowing division to be executed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the division circuit of the present invention, and FIG. 2 is a block diagram of a conventional example. 101...Multiple generation circuit for the divisor, 102.106...Selector circuit, 103.105...Adder, 104...Multiple generation circuit for the divisor, 107...Logic circuit for determining the quotient , 108... Quotient accumulation circuit, 109... Adder group, 11
0...divisor, 111...multiple of divisor, 1
12...qshiD, 113...partial remainder RJ
,,114... Partial remainder Rt++= r (Ri-q
tD ), 115...bits necessary to determine the quotient of the divisor, 116...bits necessary to determine the quotient among the multiples of the divisor, 117...bits of the partial remainder Of these, bits necessary to determine the quotient; 118... Output of adder 105; 119... RJ QλD; bits necessary to determine the quotient;

Claims (1)

[Claims] 1. A first multiple generation circuit that inputs a divisor and generates a multiple of the divisor; and selects a multiple specified by a quotient from among the multiples;
a first selector circuit that outputs an output; an adder that inputs the output of the first selector circuit and a partial remainder, adds the two, shifts them, and outputs the next partial remainder; and determines the quotient of the divisor. A second multiple generation circuit that inputs the necessary bits to generate multiples, and a second multiple generation circuit that is prepared for each multiple generated by the second multiple generation circuit, and a plurality of adders that input bits necessary for determining the quotient of the partial remainder and add the two; and a second adder that selects the addition result specified by the quotient from among the addition results of the plurality of adders. a logic circuit that inputs the output of the second selector circuit and generates the quotient;