JPH0214727B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD OF THE INVENTION The present invention relates to a residue generation circuit used for determining the quality of an operation result. Conventional technology and problems Carry save adder CSA (Carry Save Adder)
A high-speed multiplier using the CSA tree method, which connects multiplicands in a tree-like manner, calculates the residue before and after the multiplication in parallel with the multiplication of the multiplicand and the multiplier, and compares them to help determine the quality of the multiplication result. Parity checking is widely used for error checking, but performing this using multiplication is quite complicated, so a method of comparing recipes is used. A general residue is the remainder when a target numerical value is divided by 3 (or a multiple thereof). Therefore, if the numerical values take the values 0, 1, 2, 3, 4, 5, ..., the recipe will be 0, 1, 2, 0, 1, 2,
...and changes periodically. This recipe 0, 1, 2, 0, ... is calculated by adding a weight of 2 to the even bit and a weight of 1 to the odd bit of the n-bit binary number (however, for the bit that is 1 in each case),
It is found as the remainder by dividing the sum by 3. There are three types of numerical values to be generated: the input multiplicand, the multiplier, and the operation result.The former two residues are multiplied to become the pre-operation residue, which is compared with the operation result residue. As a recipe check method, if the comparison results match, it is determined that the calculation result is correct. By the way, the recipe of the calculation result was conventionally called CSA.
SUM (sum), CARRY (carry) obtained by tree
Since it is generated from the terms, there is a drawback that the configuration of the residue generation circuit is complicated. Purpose of the Invention The present invention provides a G/P of a carry propagation adder (CPA) used for high-speed addition.
This is intended to simplify the circuit configuration by generating a recipe of the calculation result from the G/P term generated by the unit. Here, G stands for carry generation (Generate) and P stands for carry propagation (Propagate). Structure of the Invention The present invention provides a recipe generation circuit for a result of an arithmetic device using a carry propagation adder, in which a result is generated from a carry generation function G and a carry propagation function P obtained by a G/P unit of the adder. The present invention is characterized in that a recipe is generated, and this will be explained in detail below with reference to the illustrated embodiment. Embodiment of the Invention Figure 1 shows a CSA tree type multiplier, where 1 is a register in which the multiplicand CAND is set, and 2 is a multiplier.
Register where iER is set, 3 is recorder, 4
is the multiple gate, 5 is the CSA tree, 6 is the register where the SUM of the intermediate operation result (partial product) is set, and 7 is its CARRY.
are the registers that are set, and these registers 6,
The contents of 7 are the carry propagation adder CPA (Carry
Propagate Adder) 8 is input, and
Loop back to the input of CSA tree 5
Back) CCPA8 is input stage G/P unit 9, carry look logic (Carry Look-
Consists of 10 Ahead Logic (CLA), 11 Half Sum Logic (HS), and 12 Full Sum Logic (FS).
The final result (Product) is obtained from FS12. A recipe check system is provided in parallel with this calculation system. 13 and 14 are residue generators that generate residues from the input CAND and IER, and 15 is a residue multiplier that multiplies two residues.
Multiplier), 16 is a recipe comparator that compares the recipe of the multiplier 15 with the recipe obtained from the operation result, and generates an error ERR when they do not match. Conventionally, as shown by the broken line, intermediate calculation results were
Since the resulting recipe is created using circuits 21 and 22 that generate the recipe from SUM and CARRY, and a recipe adder 23 that adds them together, the configuration becomes complicated (described later). On the other hand, in the present invention, the G/P obtained from the G/P unit 9
Generates a recipe using terms as input. 17 is its recipe generation circuit. Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 2 to 4. Assuming that the two inputs of the G/P unit 9 are A and B, and that they are both 4 bits to simplify the explanation, the i-th bit of each input A and B is
The carry generation function Gi and carry propagation function Pi regarding Ai and Bi have the following relationship. Gi=Ai・Bi...(1) Pi=Ai+Bi...(2) The carry raw function Gi is such that if the two inputs Ai and Bi are both 1, a carry will always occur at the i-th digit. In order to distinguish this from other combinations, we perform a logical product as shown in equation (1). On the other hand, the carry propagation function Pi
is a logical expression that predicts this carry propagation since the carry of the lower digit is transmitted to the higher digit when either of the two inputs Ai or Bi is 1. Generally Pi and Ai
Although it is the exclusive OR of Bi, there is a carry even when Ai = Bi = 1 (correctly, this is due to Gi), so in the G/P unit in Figure 1, equation (2) is used. as a simple logical sum. Now, considering 4-bit addition as an example, the relationship between inputs A and B and outputs G and P can be expressed as shown in FIG. 2a. Here, the recipes of inputs A and B are odd bits (i = 1, 3) and even bits (i
=0, 2), respectively, by a unique value, that is, by multiplying the odd numbered bits by 1 and the even numbered bits by 2, as described above. Therefore, the recipe of each bit of inputs A and B (when it is 1) can be expressed as shown in FIG. 2b. As is clear from this figure, there are 2 combinations of recipes at the same bit position (bits with equal i) in inputs A and B.
and 2 (case ○A: even numbered bits) or 1 and 1 (case ○B: odd numbered bits). So, if we consider the recipe for case ○i, this is G ₀
RES (G ₀ ) when = 1 and RES when P ₀ = 1
(P ₀ ) is as follows. RES (G ₀ ) = RES (2 + 2) = RES (1) ... RES (P ₀ ) = RES (2 + 0) = RES (2) ... Here, the formula is G ₀ = 1, so A ₀ = B ₀ When = 1, the recipe RES (G ₀ ) is the sum of the recipes 2 and 2 at ○A in Figure 2 (b) RES (2 + 2)
Since this is RES(4), dividing by 3 means that it becomes RES(1). One method is
P ₀ = 1 Therefore, when either A ₀ or B ₀ is 1 (excluding cases where both are 1, which is represented by G ₀ ), the recipe RES (P ₀ ) is as shown in Figure 2(b). It becomes the sum of recipe 2 and 0 in A (this 0 is A ₀ ,
B ₀ is 0), therefore, the residue RES (P ₀ ) becomes RES(2). Similarly, the recipe for odd-numbered bit case ○ is as follows: RES (G ₁ ) = RES (1 + 1) = RES (2) ... RES (P ₁ ) = RES (1 + 0) = RES (1) .... The above is a case where G ₀ , P ₀ and G ₁ , P ₁ are 1, but there are also cases where G ₀ = 0, P ₀ = 0,
Since there are cases where G ₁ = 0 and P ₁ = 0 (both result in RES (0)), the resultant RES obtained from G/P of i = 0 bits is classified as shown in Table 1, and i The recipe RES obtained from =1 bit G/P is classified as shown in Table 2.

【table】

[Table] In the above table, the RES values are listed and the formula used to calculate them is added. Also, X of P ₀ and P ₁
is used in the sense that the numerical value does not matter. This is because when G ₀ and G ₁ are 1, from equations (1) and (2) above,
This is because P ₀ and P ₁ are always 1. Note that Table 1 is also applied to the second bits G ₂ and P ₂ , and Table 2 is also applied to the third bits G ₃ and P ₃ . By combining Tables 1 and 2 above, an intermediate recipe shown in Table 3 below can be obtained.

【table】

[Table] FIG. 3 shows the arrangement of gates that generate the residue RES in Table 3. In this circuit, Table 3
Assuming that X is not handled, the logic is composed of a gate group with a maximum of 4 inputs and a minimum of 2 inputs, and as shown in Table 3, RES = 0 means that G ₀ P ₀ G ₁ P ₁ is 0000 and 0101.
Since it is generated at 1X1X, the gate outputs are combined to generate Residue + RESO, and RES1 is 0001,
Since it occurs at 011X and 1X00, the outputs of the gates are combined to generate Residue+RES1, and RES2 occurs at 001X, 0100, and 1X01, so the outputs of the gates are combined to generate Residue+RES2. Here, the symbols + and - of the residue mean non-inversion and inversion of the signal level indicating the residue. For the 4-bit numbers A and B in Figure 2, this 9
The fourth gate block GB consists of gates.
As shown in the figure, by using two gate blocks GB ₀ and GB ₁ and further combining them with a nine-gate gate block GB ₂ to be described later, a recipe generation circuit, for example, 17 in FIG. 1 is constructed. Gate block in Figure 4
Since GB ₀ to _{GB 2} each have 9 gates, 27 gates in total are sufficient. On the other hand, the conventional recipe generation circuit (collectively referred to as 21 to 23 in Fig. 1), as shown in Fig. 5a,
In front of the 9-gate gate block GB ₀ to GB ₂ ,
Since it is necessary to obtain RES of 2 bits each using 4 2-gate blocks GB ₃ to _{GB 6} , each of which receives 2 bits of 2 inputs A and B to the G/P unit 9, the total number is 2×4+9× 3 = 35 gates. Although FIG. 1b shows the configuration of gate block GB ₃ , the same applies to other gate blocks GB ₄ to _{GB 6} . The primary recipe RES obtained by this gate block _GB3 is shown in Table 4 below.

[Table] Table 4 above also applies to the remaining gate blocks GB ₄ to _{GB 6} . The logic of the 9-gate gate blocks GB ₀ to GB ₃ is shown in the table below.

[Table] Shows two inputs to the floor.
In short, the present invention has the advantage that the recipe can be generated from the output of the G/P circuit 9 without generating it from the input number of the adder 8 using the gate blocks GB ₃ to GB ₆ as shown in FIG. 5a. By doing so, the number of gates in the residue generation circuit 17 is saved. However, although gate block GB ₂ in Fig. 4 is the same as the conventional one, GB ₀ and GB ₁ have the configuration shown in Fig. 3, so GB ₀ and GB ₁ in Fig. 5 a differ depending on the type of gate used. different. Note that the present invention is applicable not only to multipliers but also to other arithmetic devices (for example, adders). Effects of the Invention As described above, according to the present invention, the recipe of the operation result is generated from the carry generation function G and the carry propagation function P. There is an advantage that the number of gates is smaller than that of generating the residue from B. In addition, in the conventional system, the recipe generation circuits 21 and 22 receive input from the Sam and Carry registers 6 and 7.
Since these are separate chips as an integrated circuit, it is necessary to provide a power gate at the output of registers 6 and 7, but if the input is taken from the G/P circuit, the driving ability of this circuit is large, so the power gate is It also has the advantage of not being necessary.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a CSA tree type multiplier to which the present invention is applied, Figs. 2 to 4 are explanatory diagrams showing an embodiment of the present invention, and Fig. 5 is an example of a conventional recipe generation circuit. FIG. In the figure, 8 is a carry propagation adder, 9 is a G/P unit, 17 is a resultant recipe generation circuit, GB ₀ ~
GB ₂ is a gate block.

Claims (1)

[Claims] 1. In a result generation circuit of an arithmetic unit using a carry propagation adder, the G/P of the adder
1. A residue generation circuit, characterized in that it generates a residue of the result from a carry generation function G and a carry propagation function P obtained by a unit.