JPH02184088A - ジョセフソン論理回路 - Google Patents
ジョセフソン論理回路Info
- Publication number
- JPH02184088A JPH02184088A JP892802A JP280289A JPH02184088A JP H02184088 A JPH02184088 A JP H02184088A JP 892802 A JP892802 A JP 892802A JP 280289 A JP280289 A JP 280289A JP H02184088 A JPH02184088 A JP H02184088A
- Authority
- JP
- Japan
- Prior art keywords
- circuit block
- circuit
- terminal
- wiring
- josephson
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005291 magnetic effect Effects 0.000 claims description 6
- 230000004907 flux Effects 0.000 claims description 5
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 7
- 230000001934 delay Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000005672 electromagnetic field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP892802A JPH02184088A (ja) | 1989-01-11 | 1989-01-11 | ジョセフソン論理回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP892802A JPH02184088A (ja) | 1989-01-11 | 1989-01-11 | ジョセフソン論理回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02184088A true JPH02184088A (ja) | 1990-07-18 |
| JPH0577348B2 JPH0577348B2 (enrdf_load_stackoverflow) | 1993-10-26 |
Family
ID=11539510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP892802A Granted JPH02184088A (ja) | 1989-01-11 | 1989-01-11 | ジョセフソン論理回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02184088A (enrdf_load_stackoverflow) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS558094A (en) * | 1978-06-30 | 1980-01-21 | Ibm | Josephson bond polarity inverting circuit |
-
1989
- 1989-01-11 JP JP892802A patent/JPH02184088A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS558094A (en) * | 1978-06-30 | 1980-01-21 | Ibm | Josephson bond polarity inverting circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0577348B2 (enrdf_load_stackoverflow) | 1993-10-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4210885A (en) | Thin film lossy line for preventing reflections in microcircuit chip package interconnections | |
| US5499445A (en) | Method of making a multi-layer to package | |
| US5309015A (en) | Clock wiring and semiconductor integrated circuit device having the same | |
| JP4572011B2 (ja) | 半導体デバイスアセンブリ | |
| US4831497A (en) | Reduction of cross talk in interconnecting conductors | |
| US4725878A (en) | Semiconductor device | |
| US4686492A (en) | Impedance match connection using multiple layers of bond wires | |
| JP4373531B2 (ja) | 差動平衡信号伝送基板 | |
| US6376904B1 (en) | Redistributed bond pads in stacked integrated circuit die package | |
| KR100227540B1 (ko) | 공면 전송선 장착 플립 칩 및 이를 이용한 무선 주파수 회로와 고주파 전력 증폭기 | |
| US7854368B2 (en) | Method and structure for controlled impedance wire bonds using co-dispensing of dielectric spacers | |
| CN109792840B (zh) | 用于减少量子信号串扰的多层印刷电路板 | |
| JPH01181540A (ja) | Ｔａｂパツケージ | |
| JPH02180056A (ja) | 多機能接地面 | |
| Senthinathan et al. | Reference plane parasitics modeling and their contribution to the power and ground path" effective" inductance as seen by the output drivers | |
| US20090091019A1 (en) | Memory Packages Having Stair Step Interconnection Layers | |
| JPH0462955A (ja) | 集積回路装置 | |
| KR20040085169A (ko) | 스플릿 게이트 파워 모듈과 그 모듈안의 진동을 억제하는방법 | |
| US5812384A (en) | Matrix filters for low-noise power distribution systems | |
| JPS5961192A (ja) | ３次元的実装構造体 | |
| JP2003134177A (ja) | デジタル信号伝送回路の設計方法 | |
| JPH02184088A (ja) | ジョセフソン論理回路 | |
| Eden | Capabilities of normal metal electrical interconnections for 3D MCM electronic packaging | |
| JPS595640A (ja) | 半導体装置 | |
| JPH0613421A (ja) | 集積回路装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |