JPH02184088A - Josephson logic circuit - Google Patents

Abstract

PURPOSE:To allow an external AC power source to produce a small output and to simultaneously reduce a crosstalk at a terminal connector between an LSI chip and a mounting board by dividing a circuit in the LSI chip into circuit groups which are electrically insulated from each other, connecting the circuit groups in series with respect to a power terminal, and applying an AC power source current input from an exterior once through respective circuit groups to a grounding point. CONSTITUTION:The first AC power terminal 111 of a first circuit group 102 is connected to the AC power input terminal 127 of an LSI chip 101, and an external AC power source 132 is connected to the same terminal 127. The second AC power input terminal 112 of the circuit group 102 is connected to the AC power input terminal 121 of a second circuit group 103 via wirings 107. Similarly, the first AC power input terminal 125 of a n-th circuit group 105 is connected to the second AC power input terminal of a (n-1)-th circuit group. The second AC power input terminal 126 of the n-th circuit group 105 is connected to the connection terminal 128 of a LSI chip 101.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the configuration of an AC voltage-driven Josephson logic circuit, and is particularly applicable to a Josephson LSI that operates with a high-speed clock and has a high degree of integration. The present invention relates to a power supply system suitable for a Josephson logic circuit.

[Prior Art] A Josephson element is a current-driven element, and requires an alternating current of approximately several hundred μA to drive one element. In order to suppress signal propagation delays between elements, a method is used in which the elements and circuits are formed on a superconducting ground plane, and the termination point of the signal wiring is connected to the ground plane via a matching resistor equal to the characteristic impedance of the wiring. This allows the return current of the output current to flow through the ground plane, making it possible to minimize wiring delays and reduce the area occupied by the wiring. In this case, it is necessary to supply alternating current in parallel to Josephson elements formed on the same ground plane. An example of such an alternating current supply method is provided by P.C. Arnett, D.J. Herrell; N.G. Volume 15, No. 1, January 1979, No. 554
Pages from page 557 CP, C.

Arnett and D, J-Herrel
``Regulated AC Power
r for Josephson Interf
Erometer LatchingLogic C
1rcuits,” IEEE Trans, on
Magnetics.

Vol, NAG-15, Nal, January
1979. pp. 554-557). In the same document, as shown in Figure 2, LSI
A transformer installed on a superconducting mounting board outside the chip increases the input current by 16 times, and a regulator with a Josephson junction with a large junction area connected in series is inserted between the power bus and ground plane on the chip. The technology uses the gap voltage of the Josephson junction to maintain the power supply bus voltage at a low, constant value.

In addition, in Fig. 2, 201 is a transformer, 202 is an LS
I-chip 203 indicates a card on which the LSI chip 202 is mounted. Further, 204 is a connection part between the LSI chip 202 and the card 203, 205 is a regulator on the LSI chip 202, 2o6 is an AC power supply terminal to the card 203, 207 is an AC power active Josephson logic circuit, 20
8 is an input/output signal terminal of the card 203.

[Problem to be Solved by the Invention] The AC power supply method using such a transformer has the great feature that the current that should be generated by the AC current source that supplies AC current from the outside can be reduced in a predetermined frequency band. . However, the following two problems remain. That is, (1) since the load of the transformer has a resistance component, there is a lower limit and an upper limit to the band in which current conversion is possible. (2)LS
In the input terminal section of the I chip, for example, 11 of the LSI chip
When the power reaches several gates, an alternating current reaching more than IA is flowing. The frequency of this alternating current is the high frequency of the clock, and the chip and the mounting board on which it is mounted (
If there is an inductance component in the connection between the product (package, card, board, etc.), a strong magnetic field will be generated there.
This causes crosstalk with other input/output terminal connections.

An object of the present invention is to provide a method for reducing the supply current of an alternating current source without band limitations, and also to provide a Josephson logic circuit configuration that reduces the amplitude of alternating current flowing through the connection terminal portion of an LSI chip.

[Means to solve the problem] In order to solve the above object, the present invention provides.

The circuits in an LSI chip are divided into circuit groups that are electrically connected to each other. Such division can be realized by using a flux-coupled Josephson element.

Each circuit group is connected in series when viewed from the power supply terminal, and the AC power terminal input from the outside passes through each circuit group once to reach the ground point.

[Operations] Since the AC power supply current is supplied in series to each circuit group, the amplitude of the AC power supply current input from the outside is reduced to 1/the number of circuit groups. Further, in this supply method, there is no element that imposes a lower limit in terms of frequency, and it can be used from the DC band.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to FIG. In the same figure, 101 is a Josephson LSI chip, 102 to 105
are circuits formed on different ground planes. 106 is a ground plane groove between each circuit group.In one circuit group 102, there are two AC power supply terminals 111 and 1.
There are 12.

A power bus 113 is connected to the AC power terminal 111, and a power bus 114 is connected to the AC power terminal 112. There is a power supply resistor 117 between the power bus and the ground plane.
A large number of branches each having a Josephson element 118 connected in series are provided in parallel.

A regulator 115 is connected between the power bus and the ground plane at a position closer to the AC power supply terminals 111 and 112 than where the branches on the power bus are connected. A dummy resistor 116 is connected between the power bus and the ground plane on the side closer to the AC power supply terminals 111 and 112 than where the regulator 115 is connected on the power bus.

The regulator 115 is formed by connecting an even number of Josephson junctions in series, the junction area of which is larger than the total area of the Josephson junctions included in the Josephson elements supplied with power from the power supply bus 113 or 114.

The other circuit groups 103 to 105 also have the same structure as the first circuit group 102. The first AC power supply terminal 111 of the first circuit group 102 is connected to the AC power input terminal 127 of the LSI chip 101, and the terminal 127 is connected to an external AC power supply terminal g1.
32 are connected. The second AC power input terminal 112 of the first circuit group 102 is connected to the first AC power input terminal 121 of the second circuit group 103 by a wiring 107. Second AC power input terminal 1 of second circuit group 103
22 is connected to the first AC power input terminal 123 of the third circuit group 104 through the fi 108. Similarly, the first AC power input terminal 125 of the n-th circuit group 105 is connected to the second AC power input terminal of the (n-1)th circuit group. A second AC power input terminal 126 of the n-th circuit group 105 is connected to a ground terminal 128 of the LSI chip 101.

Signal transmission between each circuit group is performed by routing signal wiring. From the first circuit group 102 to the second circuit group 10
A wiring 133 transmitting a signal to the second circuit group 10 originates from the Josephson junction 119 on the first circuit group 102 and connects to the second circuit group 10.
3, after transmitting the signal to the flux-coupled Josephson element 120 on the second circuit group 103 by magnetic flux coupling, it returns to the first circuit group 102 and passes through the terminating resistor 134 to the first circuit group 102. Connected to ground plane. Although signal transmission is performed between the first circuit group 102 and the second circuit group 103 in this way, there is no electrical contact at all except for the wiring 107.

That is, the first power input terminal 11 of the first circuit group 102
The AC power supply current input to the second power supply input terminal 112 appears almost unchanged at the second power supply input terminal 112, although there is a slight phase delay at high frequencies. This serves as a power input to the second circuit group 103.

It is desirable that the number of branches connected to each power supply bus, in which the feed resistor 117 and the Josephson element 118 are connected in series, is equal. The regulator 115 has a common shape and shape for each circuit group.
have characteristics. Then, the same value of power supply current is supplied to the Josephson elements 118 in any circuit group. However, it is extremely difficult to equalize the number of branches connected to each power supply bus if the structure is not regular, such as a gate array. Therefore, the load on the regulator is adjusted using the dummy resistor 116, so that the current supplied to each Josephson element 118 is finally made equal.

In FIG. 3, the signal wiring 133 is connected to the ground plane groove 106.
The structure of the part that crosses is shown. In the figure, 301 is the ground plane of the first circuit group 102, 302 is the ground plane 103 of the second circuit group, and the silicon substrate surface is exposed in the groove 106 between them. As shown in FIG. 1, the wiring between both ground planes includes a wiring 135 from the first circuit group 102 to the second circuit group 103, and a wiring 135 from the second circuit group 103 to the first circuit group 102. Wiring 136 towards
However, in the ground plane groove crossing portion, the latter is configured as a first wiring layer 304 and the former is configured as a second wiring layer 303. Both are stacked vertically in a direction perpendicular to the ground plane. In other words, the wiring layer 303 of the wiring 135 is superimposed on the wiring layer 304 of the wiring 136. The magnetic shielding effect of the ground plane is interrupted at the groove portion 106.

Therefore, if the wires 135 and 136 are not stacked, an external noise electromagnetic field may intersect with the loop formed by the wire 133, causing dielectric noise, and there is a possibility that an erroneous signal may be transmitted to the Josephson element 120. be.

Here, the wiring delay in the ground brain groove crossing portion will be explained with reference to FIG. 4. The signal wiring that originates from the Josephson element 119 in the first circuit group and reaches the Josephson element 120 in the second circuit group is connected to the partial ohm wire on the ground plane of the first circuit group and to the Josephson element 120 in the second circuit group. It can be considered separately into parts Q and 2 on the ground plane. Since the width of the ground plane groove portion 106 may be as small as several μm, there is no need to consider direct wiring delays in this portion. Furthermore, the portion of the wiring 136 that returns from the Josephson element 120 to the terminating resistor 134 provided on the first circuit group is designated as Q3.

The propagation delay from Josephson element 119 to 120 is not just a wiring delay of Q + Q2. That is, since the ground plane is interrupted at the 01 part and the Q2 part, the impedance is not continuous. For this reason, wiring 13
The signal that has arrived at the Josephson element 120 from the wiring 136 will not reach a steady value unless the reflected wave that has traveled back and forth through the wiring 136 returns. Therefore, Josephson elements 119 and 12
The wiring delay between 0 and 0 is Q + Q, +2 Q, therefore, it is important to shorten the distance Q as much as possible.

FIG. 5 shows how to use a buffer circuit to shorten the wiring delay. Output signal 5 from first circuit group 102
05 transmits a signal to the Josephson element 502 in the buffer circuit 501 provided on the second circuit group 103 by magnetic flux coupling, and then transmits the signal to the terminating resistor 506 of the first circuit group 102.
It is connected to the ground plane of the same circuit group via. In the figure, 504 is a power supply bus, and 503 is a power supply resistor that supplies power supply current to the Josephson element 502 from there. The buffer circuit 501 includes such a Josephson element 50.
2 are arranged in parallel for the required number of signals. This buffer circuit is provided in the immediate vicinity of the ground plane groove 106, and is Q2 in FIG. This is effective in shortening the wiring delay corresponding to Q.

[Effects of the Invention] According to the present invention, the value of the AC power supply current supplied from the external terminal is reduced to 1/the number of divided circuit groups.
The output of the external AC power supply is small, and at the same time, the output of the chip and mounting board (package) can be reduced.

This has the effect of reducing crosstalk at the terminal connection section between the terminal and the terminal (card, board, etc.).

[Brief Description of the Drawings] Fig. 1 shows the overall configuration of a Josephson logic circuit according to an embodiment of the present invention, and Fig. 2 shows a conventional example of a method for supplying AC power to a Josephson integrated circuit chip. Figure 3 is a diagram showing a signal wiring connection method between circuit groups according to an embodiment of the present invention, Figure 4 is a circuit diagram of signal wiring between circuit groups, and Figure 5 is used for signal wiring between circuit groups. 2 is a diagram showing the configuration of a buffer circuit for performing 101... LSI chip, 102-105... circuit group, 111.112, 121-126... AC power input terminal, 115... regulator, 116... dummy resistor, 127... LSI chip AC power input terminal,
128... LSI chip ground terminal, 132... External AC power supply.

Claims (1)

[Claims] 1. A Josephson logic circuit having a plurality of circuit blocks including Josephson elements, each of the circuit blocks being connected to first and second terminals and the first terminal. a power supply bus connected to the second terminal, a superconducting ground plane connected to the second terminal, and a plurality of series bodies of a power supply resistor and a Josephson element provided between the power supply bus and the superconducting ground plane, The plurality of circuit blocks are connected in series through the first and second terminals, and the AC power supply current supplied to the Josephson logic circuit passes through each of the circuit blocks once. Josephson logic circuit 2 characterized in that it reaches a ground point through
In claim 1, an alternating current source is connected to one of the first and second terminals of the first circuit block, and an alternating current source is connected to the other of the first and second terminals of the first circuit block. One of the first and second terminals of the second circuit block is connected to the other of the first and second terminals of the second circuit block, and the other of the first and second terminals of the second circuit block is connected to the first or second terminal of the third circuit block. terminal, and then similarly connect up to the nth circuit block, and connect the first or second terminal of the nth circuit block that is not connected to the (n-1)th circuit block. A Josephson logic circuit characterized by supplying alternating current power to n circuit blocks in series by grounding them. 3. In claim 1, from the i-th circuit block,
The j-th circuit block formed on the ground plane that is not directly connected to the ground plane of the i-th circuit block.
The signal wiring leading to the i-th (i≠j) circuit block is
After the signal is transmitted from the ith circuit block to the Josephson element in the jth circuit block by magnetic flux coupling, it returns to the ith circuit block and is connected to the ground plane via the terminating resistor. Features Josephson logic circuit. 4. In claim 3, the wiring between the ground plane of the i-th circuit block and the ground plane of the j-th circuit block is formed to cross a groove portion between the two ground planes, and comprises first and second superconducting signal wiring layers different from the ground planes, and the first and second superconducting signal wiring layers have wiring stacked vertically in a direction perpendicular to the ground planes. One of the lower first wiring layer and the upper second wiring layer is the wiring that originates from the i-th circuit block and goes to the j-th circuit block, and the other one is the wiring that originates from the i-th circuit block and goes to the j-th circuit block. A Josephson logic circuit characterized in that it is used as wiring from a j-th circuit block back to an i-th circuit block.