JPH02184068A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of crystal dislocation in element forming layers at the outside parts of a groove type isolating part due to heat applied in well running and to maintain the excellent characteristics of the elements which are formed in wells by forming the wells in the element forming layers of a semiconductor substrate formed by an SOI method, and providing the groove type isolating part which isolates the wells. CONSTITUTION:A plurality of wells 10 and 11 are formed at element forming layers 2 of a semiconductor substrate 1 having an SOI structure. Thereafter, a groove type isolating part 20 which isolates the wells 10 and 11 is formed. In this constitution, crystal dislocation does not occur in the element forming layers at the outside parts of the groove type isolating part 20 even if high temperature heat is applied at the time of well running. Therefore, the excellent characteristics can be maintained for the elements formed in the wells.

Description

[Detailed Description of the Invention] (Requires 4!t) Regarding a method for manufacturing a semiconductor device in which an element is formed on a semiconductor substrate having an SOI structure, the purpose is to suppress the occurrence of crystal dislocations in the element formation layer, and the SOI structure is The method includes a step of forming a plurality of wells in an element formation layer of a semiconductor substrate having a semiconductor substrate, and a step of forming a groove type isolation for separating the wells after forming the wells.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor, and more specifically, to a method for manufacturing a semiconductor.
The present invention relates to a method for manufacturing a semiconductor device in which elements are formed on a semiconductor substrate having an OI structure.

[Conventional technology]

In order to create a semiconductor device that prevents α-ray soft errors and CMOS latch amplifiers, a structure with an insulating layer between two single crystal semiconductor layers, that is, SOI (sHIcon-
An on-insulating 5 substrate structure has been proposed.

When forming a well in a semiconductor substrate having this SOi structure, a trench type isolation layer is provided in the element formation layer 51 of the semiconductor substrate 50 as shown in FIG. 2(a) to separate the well formation regions 52. The well 54 is formed to a depth that reaches the insulation WI 53 (FIG. 2(b)), and then the well is formed i.
P-type element or n-type element ions are implanted into region 52 (Figure (C)).Finally, well running is performed at a temperature of about 1200°C for about 3 hours to spread and activate the elements. , this is designated as well 55 (also l!I
(d)).

[Problem to be solved by the invention]

However, when the well 55 is formed by such a method, the bottom and sides of the element formation layer 51 in which the well is to be formed are covered with an insulating film, and furthermore, since the element formation layer 51 is extremely thin, , as shown by the arrow in FIG. 2(d), device formation J? from the groove type isolation 54 during well running. ! ! There is a problem that crystal dislocations are more likely to occur inside the well 51 and the characteristics of the element formed in the well 55 are deteriorated.

Of course, LOGO instead of groove type isolation
Although it is possible to prevent crystal dislocation by forming isolation according to 3, it is not suitable for device miniaturization because the area is larger than the groove type, and it is not possible to achieve a rough stub-free state. There is an inconvenience.

The present invention has been made in view of such problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can suppress the occurrence of crystal dislocations without hindering miniaturization.

[Means to solve the problem]

The above-mentioned problem is solved by a semiconductor device having a process of forming groove type isolation on a semiconductor substrate having an SOI structure! T! ! In the manufacturing method, a step of forming a plurality of wells 1O111 in the element formation layer 2 of the semiconductor substrate 1 having an SOI structure, and 2. After forming the wells 1O111, a trench type isolator is formed to separate the wells 10 and 11. Ration 2
1 of a semiconductor device characterized by comprising a step of forming 0! ! The problem can be solved by the method of delivery.

(Function) According to the present invention, after forming the plurality of wells 10.11 in the element formation layer 2 of the semiconductor substrate l having an SOI structure,
Well 10. ．． Since the groove type isolation 20 is formed to separate the groove type isolation 20, crystal dislocations do not occur in the element forming layer 2 around the groove type isolation 20 due to the high heat applied during well running.

Therefore, it is possible to maintain good characteristics of the elements formed in the wells 10 and 11, and it is also possible to miniaturize the semiconductor device.

〔Example〕

FIG. 1 is a cross-sectional view showing a process according to an embodiment of the present invention, in which reference numeral 1 indicates a semiconductor substrate having an SOI structure, an element formation layer 2 made of a semiconductor such as silicon, and a base layer. 3 and an insulating layer 4 formed between them.

When forming a well in this semiconductor substrate 1, as shown in FIG.
g) A film 5 is formed, and IW nitride (SisNa'R) 6 is laminated on the 5IO2 film 5 to a thickness of about 1000λ.

After the nitriding process, the nitrided 1! A window 7 is provided by etching the groove 6 by photolithography (FIG. 1(b)).

Next, a well is formed in the element formation M2 of the semiconductor substrate l. For example, when forming a P-well and an N-well on the same semiconductor substrate 1, first, as shown in FIG. After injecting into the element forming layer 2, the resist 8 is peeled off.

Next, as shown in the same figure (d), the part where the N well is not formed is covered with a resist 9, and m (P)
After the elements are implanted into the element forming layer 2, the resist 9 is removed. The element is 180KeV, l XIO"ca+-"
Inject under the following conditions.

After completing the ion implantation in this way, the semiconductor substrate 1 is placed in a heating furnace (not shown) for well running, and heated once at about 1.20θ°C for 3 hours in a nitrogen atmosphere, as shown in FIG. As shown in e), the implanted elements such as boron and phosphorus diffuse within the element forming layer 2 and become activated.

In this case, the region where boron is diffused becomes the P well 1O, and the region where phosphorus is diffused becomes the N well 11, thus completing the well forming process.

In this state, no crystal dislocation occurs in the element formation layer 2 because no groove type isolation is formed.

In this stage jj9, in order to separate the elements to be formed in the regions of the P well 11 and the N well 12, the surface of the element forming layer 2 is heated at 900°C in an oxygen atmosphere, resulting in the patterning described above. Since the nitride film 6 that has been subjected to the nitride film 6 acts as an oxidation prevention film, the element forming layer 2 exposed through the window 7 of the nitride film 6 is thermally oxidized, and then field oxidized by the LOCO3 method as shown in FIG. A film 12.13 will be formed.

Next, a PSG film 14 is formed on the nitride film 2 and the field oxide film 12, 13 to a thickness of about 4,000 by vapor phase growth, and after covering this PSC film 14 with a resist 15, the P-well The resist 15 located in the region separating the resist 10 and the N-well 11 is removed by exposure and development (FIG. 1(g)).

Then, using the patterned resist 15 as a mask, reactive ion etching (RI B) is performed using a fluorine-based gas, such as CF, plus CHF2, to remove the PSG film 14, nitride film 6, and oxide film 5. Patterning is performed to form groove forming windows 16 (FIG. 1(h)).

Next, after ashing the resist 15, PSGI'214
When the element formation layer 2 of the semiconductor substrate I is etched by the RIUF method using a chlorine-based gas such as chlorine or carbon tetrachloride, using as a mask, the selectivity of silicon to the PSG film 4 is high. As shown in Figure (i), only the element forming layer 2 made of silicon is etched to form a groove 17 for forming an isolation gin. This groove 17 has a depth that reaches the insulating layer 4 below the element forming layer 2.

After this, the PSG film 14 is removed using a hydrofluoric acid (IIF) solution. Hydrofluoric acid also has the function of cleaning the inside of the isolation forming groove 17.

Furthermore, after thermally oxidizing the inner wall of this trench 17 to form an oxide film 18 (FIG. 1(j)), polysilicon 19 is buried in the trench 17 to form a trench type isolation 20 (FIG. 1(j)). Figure 1 (k)).

Finally, groove type isolation 2 is formed by thermal oxidation.
After forming a cap layer 21 by oxidizing the surface portion of the polysilicon 19 within the cap layer 2, the nitride film 6 is removed using phosphoric acid (FIG. 1(1)).

In the embodiment described above, the groove isolation 20
Well 10.1 before creating! Therefore, by applying a temperature of 1200° C. during well running, it is possible to prevent crystal dislocations occurring at the interface between the two element forming layers.

CMO is applied to the P well 10 and N well 11 of the substrate 1 described above.
An example of a structure in which S transistors 30 and 40 are formed is shown in FIG. 1 (+1). In this case, well 1
Since no crystal dislocation occurs in O1ll, the characteristics of the transistors 30 and 40 are not deteriorated, and latch-up can be prevented.

In addition, the code 3 in the figure! Is it the gate of transistor 30? ]t
i, 32 indicates its source, 33 indicates its drain, 41 indicates the gate electrode of the transistor 40, 42 indicates its source, and 43 indicates its drain.

(Effects of the Invention) As described above, according to the present invention, after forming a well in the element formation layer of a semiconductor substrate formed by the SOI method,
Since groove-type isolation is provided to separate the wells, the heat applied during well running does not generate crystal dislocations in the element formation layer outside the groove-to-1 isolation, and they are formed inside the wells. Elements can be maintained with good characteristics, and semiconductor devices can be miniaturized.

[Brief explanation of the drawing]

FIGS. 1(a) to (m) are cross-sectional views showing the manufacturing process of an embodiment of the present invention, and FIGS. 2(a) to (d) are cross-sectional views showing the manufacturing process of a conventional method. (Explanation of symbols) 1... Semiconductor substrate, 2... Element formation layer, 3... Base layer, 4... Insulating layer, 5... 5iO1 film, 6... Nitride film, 8. 9... Resist, 10... P well, 11... N well, I4... PSG film, 15... Resist, 17... Window for isolation formation, 20... Groove type iso ration.

Claims (1)

[Claims] A method for manufacturing a semiconductor device comprising a step of forming groove-type isolation in a semiconductor substrate having an SOI structure, the step of forming a plurality of wells in an element formation layer of the semiconductor substrate having an SOI structure; A method for manufacturing a semiconductor device, comprising the step of forming a groove type isolation for separating the wells after forming the wells.