JPH02183625A - Transistor logic circuit - Google Patents

Abstract

PURPOSE:To decrease a difference between output delay times between input terminals without increasing much a layout area by varying an input switching level between the input terminals depending on specific constitution. CONSTITUTION:For example, the channel width of P-channel MOS TRs 1-3 is increased sequentially from the side of power supply and the channel width of N-channel MOS TRs 4-6 is decreased as the channel width of the P-channel MOS TR whose gate is connected in common is larger. Thus, the input switching level of input terminals 7, 9 is changed in such a manner. Then without much increase in the layout area, the difference between output delay times between the input terminals can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a transistor logic circuit composed of MOS transistors.

Conventional technology Figure 2 is a circuit diagram of a conventional transistor logic circuit.
11.12 is a P-channel MOS transistor, 13.1
4 is an N-channel MOS transistor, 15.16 is an input terminal, and 17 is an output terminal.
It constitutes an R circuit. Furthermore, the channel widths of P channel MOS transistors 11 and 12 are set equal, and the channel widths of N channel MOS transistors 13 and 14 are also set equal.

In the previous conventional circuit configuration, the input terminal 15.16 and the P channel MO8 transistor connected to this.
When viewed from the input terminal 15, the input terminal 15 is connected to the P-channel MOS transistor 11 on the power supply terminal side, and the input terminal 16 is connected to the P-channel MOS transistor 12 on the output terminal side. A resistor formed by the P channel MOS transistor 12 is connected between the P channel MOS transistor 11 and the output terminal, and when viewed from the input terminal 16, a resistance formed by the P channel MOS transistor 11 is connected between the P channel MOS transistor 12 and the power supply terminal. Input terminal 15.1
6 is not equivalent in terms of circuit. For this reason, there is a problem in that the input switching levels of each input terminal are different, and at the same time, the output delay time from each input terminal is also different. Generally, in a NOR circuit, the input switching level of each input terminal is smaller as the input terminal is connected to a P-channel MOS transistor closer to the power supply terminal, and experiments have shown that the difference in the manual switching level between these input terminals is approximately It becomes about 0.2 to 0.4 V, and the output delay time from each input terminal is larger as the input terminal is connected to the P-channel MOS transistor closer to the power supply terminal.
According to experiments, the difference in output delay time between these input terminals is approximately 10 to 10 times the average output delay time (average output delay time).
It will be about 40%. These points are not a problem in conventional transistor logic circuits that are not very fast, but
This becomes a problem in high-speed transistor logic circuits.

Figure 3 is a circuit diagram of a conventional transistor logic circuit that supports high speed. 18.19 and 20.21 are P-channel MO3 transistors, and 22.23 is an N-channel MOS.
Transistors, 24.25 are input terminals, 26 are output terminals, two-man powered CMO 8 type NO type OR
It's a circuit. In addition, P channel MOS transistor 1
The channel widths of 8,19°20.21 are set equal,
The channel widths of N-channel MOS transistors 22 and 23 are also set to be equal. In the circuit configuration shown in FIG. 3, two sets of P-channel MO8 transistors connected in series are connected in parallel, and the input terminal 24 is connected to the P-channel MOS transistor 18.21, and the input terminal 25 is connected to the P-channel MO3 transistor 19.20. By connecting input terminal 2
4.25 is completely equivalent in circuit terms, the input switching levels of each input terminal are equal, and there is no difference in output delay time between input terminals. However, this configuration has a problem in that the layout area increases because the number of MOS transistors increases. In the case of a two-person NOR circuit as shown in Figure 3, the increase in layout area is not so large (although it is not), the increase in layout area increases as the number of inputs increases, making it difficult to increase the layout area. It has been difficult to use it in memory devices and the like.

Problems to be Solved by the Invention It is an object of the present invention to realize a transistor logic circuit in which the difference in output delay time between input terminals is small without increasing the layout area too much.

Means for Solving the Problems In order to achieve this object, the transistor logic circuit of the present invention has a transistor logic circuit of the present invention that changes the channel width of a MOS transistor connected between a power supply terminal or a ground terminal and an output terminal from the power supply or ground terminal side. A group of MOS transistors whose drain and source terminals are connected in series, which have been increased in size, and a MOS transistor which is connected between a ground or power supply terminal and an output terminal, which operates complementary to the series-connected MOS transistor group. The larger the channel width of the series-connected MOS transistors whose gates are connected in common, the smaller the channel width of the transistors. .

According to this configuration, it is possible to change the input switching level between each input terminal without significantly increasing the layout area, and realize a transistor logic circuit with a small difference in output delay time between the input terminals.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit diagram of a transistor logic circuit in one embodiment of the present invention. 1.2 in Figure 1
．． 3 is P channel MO3 transistor, 4.5.6 is N
Channel MOS transistor? , 8.9 is the input terminal,
10 is the output terminal, which is a 3-person CMO 8 type NO type port O.
It has an R circuit. P-channel MOS transistors 1 and 2
．． The channel width W of No. 3 gradually increases from the power supply side, and is set to, for example, W=46.50.54 (μm). N-channel MOS transistor 4.5.
The channel width W of 6 is P where the gates are commonly connected.
The larger the channel width of the channel MOS transistor, the smaller it becomes, for example, W=11.10.
9 (μm). The input switching level of the CMO3 circuit is the P channel M connected to the input terminal.
It is determined by the ratio of the channel widths Wp and WN of the OS transistor and the N-channel MOS transistor, and the larger the size of WP/WN, the higher the input switching level. Therefore, with this configuration, compared to the conventional case where the channel widths of the transistors are equal, In comparison, the input switching level of input terminal 7 increases, and the input switching level of input terminal 9 decreases. In the present invention, by changing the input switching level as described above, the difference in the input switching level between each input terminal is reduced, but the input switching level of each input terminal is not equal. This is because the difference in output delay time between each input terminal is greatly affected by the input switching level, but since the impedance of the drain and source terminals of the MOS transistors connected in series differs depending on each input terminal, the input switching This is because it is possible to reduce the difference in output delay time by slightly shifting the levels rather than setting them all to the same level.In this example, by changing the switching level of each input terminal in this way, the input terminals 7, 9
The difference δT in output delay time between is 0.04 nsec,
This is approximately 27% of 0.15 nsec in the case of the conventional configuration, and can be reduced to a level that does not pose a problem. Since the average output delay time T from each input terminal of the circuit of this embodiment is 0.49 nsec, in the conventional configuration, the difference δT in output delay time is approximately 31 ns of the average output delay time T.
%, but in this example, it was possible to reduce it to about 8%.

Furthermore, the increase in layout area due to this embodiment is due to the increase in the layout area due to the MOS
Since it is only the increase in the channel width of the transistor, it is approximately 5
%, and can be used even in memory devices with a large layout area.

As described above, according to this embodiment, the channel widths of the P-channel MO8 transistors 1, 2.3 are sequentially increased from the power supply side, and the channel widths of the N-channel MOS transistors 4, 5, 6 are connected so that their gates are connected in common. P channel M
The larger the channel width of the OS transistor, the smaller the transistor logic circuit (by doing so, the input switching levels of input terminals 7 and 9 can be changed, and the difference in output delay time between each input terminal is small without a large increase in layout area. can be realized.

Note that this embodiment is a NOR circuit, but this is a NAND circuit.
In the case of a NAND circuit, the channel widths of the N-channel MOS transistors connected in series are gradually increased from the ground terminal side, and the gate width of the N-channel MOS transistors whose gates are connected in common is large. By reducing the channel width of the P-channel MOS transistors connected in parallel, it is possible to realize a transistor logic circuit with a small difference in output delay time between input terminals without increasing the layout area, similar to a NOR circuit.

Further, in this embodiment, the channel widths of all the transistor groups connected in parallel are changed, but the channel widths may be the same as in the conventional case.

Although the number of input signals is three in this embodiment, it is also possible to input more signals.

Effects of the Invention According to the present invention, there is provided a MOS transistor connected between a power supply terminal or a ground terminal and an output terminal, in which the channel width of the MOS transistor is sequentially increased from the power supply or ground terminal side, and the drain and source terminals are connected in series. The transistor group is connected between the ground or power supply terminal and the output terminal and operates complementary to the series-connected MOS transistor group, and the gates of the MOS transistors are connected in common. By configuring it with a group of MoS transistors whose drain and source terminals are connected in parallel, the channel width of the MOS transistor group connected to the MOS transistor group is made smaller as the channel width becomes larger, and the input switching level of each input terminal of the Lancistor logic circuit can be changed. Therefore, it is possible to realize an excellent transistor logic circuit with a small difference in output delay time between each input terminal without a large increase in layout area.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a transistor logic circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional transistor logic circuit, and FIG. 3 is a circuit diagram of a conventional improved transistor logic circuit. 1.2,3,11,12.18,19,20゜21,・
...P channel MOS transistor, 4°5.6
,13,14.22.23...N channel MO
3 transistors, 7, 8.9, 15, 16°24.25
...Input terminal 1.10, 17.26...
・Output terminal. Agent's name Patent attorney Shigetaka Awano Baka 16th 2 Figures 1 to 3-m-p=, > Le 5 Trashishizuta to-Dearinuma Figure 3 W+j=W group W+> W5 We Wn-%co

Claims (3)

[Claims] (1) A first group of MOS transistors connected between a power supply terminal or a ground terminal and an output terminal, in which the channel width of the MOS transistors is gradually increased from the power supply or ground terminal side, and the drain and source terminals are connected in series. and,
operating complementary to the first MOS transistor group;
connected between the ground or power terminal and the output terminal,
A transistor logic circuit comprising a second group of MOS transistors having drain and source terminals connected in parallel. (2) The larger the channel width of the first MOS transistor group, the smaller the channel width of the MOS transistors of the second MOS transistor group whose gates are commonly connected to the first MOS transistor group. The transistor logic circuit according to claim 1, characterized in that: (3) Claim (1) or (1) characterized in that the first MOS transistor group connected in series between the power supply terminal or the ground terminal and the output terminal is composed of three or more MOS transistors. 2) The transistor logic circuit described above.