JPH02183518A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH02183518A
JPH02183518A JP332089A JP332089A JPH02183518A JP H02183518 A JPH02183518 A JP H02183518A JP 332089 A JP332089 A JP 332089A JP 332089 A JP332089 A JP 332089A JP H02183518 A JPH02183518 A JP H02183518A
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JP
Japan
Prior art keywords
molecular
film
rays
temperature
gaas
Prior art date
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Granted
Application number
JP332089A
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Japanese (ja)
Other versions
JP2920923B2 (en
Inventor
Junji Saito
齋藤 淳二
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Fujitsu Ltd
Original Assignee
Fujitsu Ltd
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Abstract

PURPOSE:To improve semiconductor characteristics by making a carrier concentration profile to be sharp in the interface of a p-type GaAs film by setting the temperature of a substrate to a value which is lower than that where the carrier concentration of the GaAs film which grow by a molar beam of triethylgallium(TEG) and that of metal arsenic As4. CONSTITUTION:After setting the temperature of a substrate to 550 deg.C where the carrier concentration becomes the minimum, adding irradiation of TEL molecular rays and Si molar rays to that of As4 molecular rays, and then allowing an n<+>-GaAs collector contact layer 2 doped with Si, the strength of Si molecular rays is reduced to allow an n-GaAs collector layer 3 which is doped with Si to grow. Then, the temperature of the substrate is set to 430 deg.C while irradiating only As4 molar rays and irradiation of TEG molar rays is added to that of As4 molecular rays for allowing a p<+>-GaAs base layer 4 doped with C to grow, thus stopping irradiation of the TEG molar rays. Then, the temperature of the substrate is set to 550 deg.C while irradiating only the As4 molar rays and irradiation of the TEG molecular rays, Al molecular rays, and Si molecular rays is added to that of the As4 molecular rays, thus forming an emitter layer 5A.

Description

【発明の詳細な説明】 〔概 要〕 半導体装置の製造方法、特に、分子線エピタキシー装置
を用いて半導体基板上にp型GaAs膜或いは、p型G
aAs膜とn型または高純度GaAs膜とを有する多層
構成の半導体膜を成長する方法に関し、p型GaAs膜
の界面におけるキャリア濃度プロファイルを急峻にさせ
るために、GaAs膜のp型不純物をBeよりも熱拡散
係数が小さいCになし得て然も成長時の基板温度を低く
なし得るようにすることを目的とし、 トリエチルガリウムの分子線及び金属砒素の分子線によ
り成長するGaAs膜のキャリア濃度がほぼ最低となる
第1温度よりも低い第2温度に基板温度を設定し、上記
二つの分子線によりp型GaAs膜を成長するように構
成し、また、上記p型GaAs膜を成長する工程と、基
板温度を上記第1温度に設定し、上記二つの分子線によ
り高純度GaAs膜を成長するか、またはその際にn型
不純物の分子線を付加してn型GaAs膜を成長する工
程とを有するように構成し、また、上記高純度GaAs
膜またはn型GaAs膜の成長の際に、基板温度を上記
p型GaAs膜成長時の温度と共通にし、上記金属砒素
の分子線の代わりにクラッキングしたアルシンの分子線
を用いるように構成する。
[Detailed Description of the Invention] [Summary] A method for manufacturing a semiconductor device, in particular, a method for producing a p-type GaAs film or a p-type G film on a semiconductor substrate using a molecular beam epitaxy device.
Regarding the method of growing a multilayer semiconductor film having an aAs film and an n-type or high-purity GaAs film, in order to steepen the carrier concentration profile at the interface of the p-type GaAs film, the p-type impurity of the GaAs film is replaced with Be. The purpose of this study is to reduce the carrier concentration of the GaAs film grown by triethyl gallium molecular beams and metallic arsenic molecular beams. The substrate temperature is set to a second temperature lower than the first temperature which is approximately the lowest, and the p-type GaAs film is grown by the two molecular beams, and the step of growing the p-type GaAs film. , a step of setting the substrate temperature at the first temperature and growing a high-purity GaAs film using the two molecular beams, or adding a molecular beam of an n-type impurity at that time to grow an n-type GaAs film; The above-mentioned high-purity GaAs
When growing the film or the n-type GaAs film, the substrate temperature is made the same as the temperature during the growth of the p-type GaAs film, and cracked arsine molecular beams are used instead of the metallic arsenic molecular beams.

〔産業上の利用分野〕[Industrial application field]

本発明は、半導体装置の製造方法に係り、特に、分子線
エピタキシー装置を用いて半導体基板上にp型GaAs
膜或いは、P型GaAs膜とn型または高純度GaA3
膜とを有する多層構成の半導体膜を成長する方法に関す
る。
The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, in particular, p-type GaAs is grown on a semiconductor substrate using a molecular beam epitaxy device.
film or p-type GaAs film and n-type or high purity GaA3
The present invention relates to a method for growing a multilayer semiconductor film having a multilayer structure.

p型GaAs膜とn型または高純度GaAs膜とを有す
る多層構成の半導体膜を用いた半導体装置には、シリコ
ンを用いたものよりも特性の優れたヘテロバイポーラト
ランジスタ(HBT)やpinダイオードなどがある。
Semiconductor devices using a multilayer semiconductor film consisting of a p-type GaAs film and an n-type or high-purity GaAs film include hetero bipolar transistors (HBTs) and pin diodes, which have better characteristics than those using silicon. be.

これらの半導体装置では、上記半導体膜内の界面におけ
るキャリア濃度プロファイルの急峻性が重要である。そ
して、その象、酸性は、半導体膜の成長方法や、半導体
をP型やn型にする不純物の種類に依存している。
In these semiconductor devices, the steepness of the carrier concentration profile at the interface within the semiconductor film is important. The acidity depends on the growth method of the semiconductor film and the type of impurity that makes the semiconductor P-type or N-type.

〔従来の技術〕[Conventional technology]

第3図は、p型GaAs膜及びn型GaAs膜を有する
多層構成の半導体膜を用いた半導体装置の1例であるH
 B Tの概要を示す側断面図である。
FIG. 3 shows an example of a semiconductor device using a multilayer semiconductor film including a p-type GaAs film and an n-type GaAs film
FIG. 2 is a side sectional view showing an outline of BT.

同図において、1は半絶縁性GaAs基板、2はn’ 
 GaAsコレクタコンタクト層、3はn −GaAs
コレクタ層、4はp”−GaAsベース層、5はn−A
]GaAsエミ・ンタ層、6はn−GaAsエミッタコ
ンタクト層、7はコレクタ電極、8はベース電極、9は
エミッタ電極、である。エミツタ層5の構成は後述の実
施例のように若干異なる場合があるが、ここでは単純化
のため図示のようにしておく。
In the figure, 1 is a semi-insulating GaAs substrate, 2 is n'
GaAs collector contact layer, 3 is n-GaAs
Collector layer, 4 is p”-GaAs base layer, 5 is n-A
] GaAs emitter layer, 6 an n-GaAs emitter contact layer, 7 a collector electrode, 8 a base electrode, and 9 an emitter electrode. Although the structure of the emitter layer 5 may be slightly different as in the embodiments described later, it is shown here for the sake of simplicity.

このトランジスタは、基板1上にコレクタコンタクト層
2からエミッタコンタクト層6までを順次成長し、所要
のエツチングを施し、電極7〜9を形成して製造するが
、ベース層4のコレクタ層3及びエミツタ層5との界面
におけるキャリア濃度プロファイルの急峻性が必要であ
ることから、上記成長は膜厚及び界面の制御性に優れた
分子線エピタキシー(MBE)によって行うことが多い
This transistor is manufactured by sequentially growing a collector contact layer 2 to an emitter contact layer 6 on a substrate 1, performing necessary etching, and forming electrodes 7 to 9. Since a steep carrier concentration profile at the interface with layer 5 is required, the above growth is often performed by molecular beam epitaxy (MBE), which has excellent controllability of film thickness and interface.

そしてその成長における従来の方法は、Ga。And the traditional method in its growth is Ga.

As4 、AI% p型不純物となるBe、 n型不純
物となるStそれぞれの分子線を組合せ、基板温度を6
00〜700°Cにするのが一般的である。
As4, AI% The molecular beams of Be as a p-type impurity and St as an n-type impurity are combined, and the substrate temperature is set to 6
Generally, the temperature is 00 to 700°C.

〔発明が解決しようとする課題] しかしながら、p型不純物となるBeO熱拡散係数が大
きいこと、成長時における基板温度がかなり高いことの
ために、P”  GaAsベース層5の界面において所
望されるキャリア濃度プロファイルの急峻性が充分に満
たされないようになり、トランジスタの特性が低下する
問題がある。
[Problems to be Solved by the Invention] However, due to the large thermal diffusion coefficient of BeO, which serves as a p-type impurity, and the considerably high substrate temperature during growth, the desired carrier concentration at the interface of the P'' GaAs base layer 5 is There is a problem that the steepness of the concentration profile is not sufficiently satisfied, and the characteristics of the transistor are deteriorated.

このことは、P型GaAs膜とn型または高純度GaA
s膜とを有する多層構成の半導体膜を用いた半導体装置
において多くの場合共通している。
This means that P-type GaAs film and n-type or high-purity GaAs film
This is common in many semiconductor devices using a multilayered semiconductor film having an S film.

一方、GaAsに対するp型不純物としてBeよりも熱
拡散係数が小さいものにCがある。
On the other hand, as a p-type impurity for GaAs, carbon has a smaller thermal diffusion coefficient than Be.

そこで本発明は、半導体装置の製造方法、特に、分子線
エピタキシー装置を用いて半導体基板上にp型GaAs
膜或いは、P型GaAs膜とn型または高純度GaAs
膜とを有する多層構成の半導体膜を成長する方法におい
て、p型GaAs膜の界面におけるキャリア濃度プロフ
ァイルを急峻にさせるために、GaAs膜のp型不純物
をBeよりも熱拡散係数が小さいCになし得て然も成長
時の基板温度を低くなし得るようにすることを目的とす
る。
Therefore, the present invention provides a method for manufacturing a semiconductor device, in particular, a method for manufacturing a semiconductor device using a molecular beam epitaxy apparatus to form p-type GaAs on a semiconductor substrate.
film or p-type GaAs film and n-type or high purity GaAs
In a method for growing a multilayer semiconductor film having a multilayer structure, the p-type impurity of the GaAs film is changed to C, which has a smaller thermal diffusion coefficient than Be, in order to steepen the carrier concentration profile at the interface of the p-type GaAs film. The object of the present invention is to make it possible to lower the substrate temperature during growth.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的は、トリエチルガリウムGa(Cz Hs)s
(TEG> の分子線及び金属砒素As4の分子線によ
り成長するGaAs膜のキャリア濃度がほぼ最低となる
第1温度よりも低い第2温度に基板温度を設定し、上記
二つの分子線によりp型GaAs膜を成長するようにし
た本発明の成長方法によって解決され、 また、上記P型GaAs膜を成長する工程と、基板温度
を上記第1/IA度に設定し、上記二つの分子線により
高純度GaAs膜を成長するか、またはその際にn型不
純物の分子線を付加してn型GaAs膜を成長する工程
とを有するようにした本発明の成長方法によって解決さ
れ、 また、上記高純度GaAs膜またはn型GaAs膜の成
長の際に、基板温度を上記p型GaAs膜成長時の温度
と共通にし、上記As、の分子線の代わりにクラッキン
グ(熱分解)したアルシンAsH3の分子線を用いるよ
うにした本発明の成長方法によって解決される。
For the above purpose, triethyl gallium Ga(Cz Hs)s
The substrate temperature is set to a second temperature lower than the first temperature at which the carrier concentration of the GaAs film grown by the molecular beam of TEG> and the molecular beam of metallic arsenic As4 is almost the lowest, and the two molecular beams The problem is solved by the growth method of the present invention, which grows a GaAs film, and also includes the step of growing the P-type GaAs film, setting the substrate temperature to the 1/IA degree, and using the two molecular beams to increase the temperature. The problem is solved by the growth method of the present invention, which comprises a step of growing a high-purity GaAs film or adding a molecular beam of n-type impurity at that time to grow an n-type GaAs film. When growing a GaAs film or an n-type GaAs film, the substrate temperature is made the same as the temperature during the growth of the p-type GaAs film, and a molecular beam of cracked (pyrolyzed) arsine AsH3 is used instead of the molecular beam of As. This problem is solved by the growth method of the present invention.

〔作 用] 第1図は本発明を説明するキャリア濃度特性図で、縦軸
はP型キャリア濃度、横軸は成長時の基板温度、である
。そして、・を結ぶ実線■はTEGの分子線とAs、の
分子線によりGaAs膜を成長した場合、○を結ぶ破線
■はTEGの分子線と920°Cでクラッキングしたア
ルシンの分子線によりGaAs膜を成長した場合、Δを
結ぶ破線■はそのクラッキング温度を850°Cにした
場合、を示す。これらの成長では、P型不純物の分子線
を付加していないが、TEG中の炭素(C)が導入され
てGaAs膜のキャリアがP型となっている。即ち、こ
こで導入されたCは、従来方法のBeよりも熱拡散係数
が小さいp型不純物となっている。
[Function] FIG. 1 is a carrier concentration characteristic diagram illustrating the present invention, in which the vertical axis represents the P-type carrier concentration and the horizontal axis represents the substrate temperature during growth. The solid line ■ connecting . is a GaAs film grown using a TEG molecular beam and an As molecular beam, and the broken line ■ connecting ○ is a GaAs film grown using a TEG molecular beam and an arsine molecular beam cracked at 920°C. The broken line (■) connecting Δ indicates the case where the cracking temperature is set to 850°C. In these growths, no molecular beam of P-type impurity is added, but carbon (C) in TEG is introduced and the carriers in the GaAs film become P-type. That is, the C introduced here is a p-type impurity having a smaller thermal diffusion coefficient than Be used in the conventional method.

破線■及び■の特性は、文献App1. Phys。The characteristics of the broken lines ■ and ■ are shown in the document App1. Phys.

Lett、 51.1987 p、1109に示された
ものであり、基板温度を低くするに従いp型キャリア濃
度が低下して、500〜600°C程度以下の基板温度
でGaAs膜が実質的に不純物を含有しない高純度とな
る。
Lett, 51.1987 p., 1109, the p-type carrier concentration decreases as the substrate temperature is lowered, and the GaAs film is substantially free of impurities at substrate temperatures below about 500 to 600°C. It has high purity and does not contain.

これに対して実線■の特性は、本発明者が見出したもの
である。その特性は、550’C近傍の基板温度でキャ
リア濃度が最低になり、その前後の温度ではキャリア濃
度が次第に増大している。即ち、破線■や■の特性と比
較すると基板温度の高い側で同様であるも基板温度の低
い側ではその顛きが逆になっている。そして基板温度を
550°Cと400°Cの間の適宜な温度にすることに
より、キャリア濃度を2X1016/c++tにした高
純度GaAs膜とキャリア濃度を3X10”/cイにし
た高ドープp型 GaAs膜の間の任意のP型キャリア
濃度のGaAs膜を成長することができることを示して
いる。
On the other hand, the characteristics indicated by the solid line (■) were discovered by the present inventor. The characteristic is that the carrier concentration is the lowest at a substrate temperature of around 550'C, and the carrier concentration gradually increases at temperatures around that temperature. That is, when compared with the characteristics indicated by the broken lines (■) and (2), the characteristics are similar on the high substrate temperature side, but the trends are reversed on the low substrate temperature side. By adjusting the substrate temperature to an appropriate temperature between 550°C and 400°C, we created a high-purity GaAs film with a carrier concentration of 2X1016/c++t and a highly doped p-type GaAs film with a carrier concentration of 3X10''/c. This shows that it is possible to grow a GaAs film with any P-type carrier concentration between the films.

また、実線■の特性は、As、分子線の圧力を2XIO
−’Paにした場合であるが、この圧力を高くすること
により最低のキャリア濃度を更に低下させることができ
、例えばその圧力を2 Xl0−2Paにすればキャリ
ア濃度が1.5X10”/c+flとなることが判って
いる。
In addition, the property of the solid line ■ is As, the pressure of the molecular beam is 2XIO
-'Pa, but by increasing this pressure, the lowest carrier concentration can be further lowered. For example, if the pressure is set to 2Xl0-2Pa, the carrier concentration becomes 1.5X10''/c+fl. I know it will happen.

一方、高純度GaAs膜にn型不純物をドーピングすれ
ば、高純度GaAs膜に含まれている不純物がp型であ
っても形成されるGaAs膜をn型になし得ることは周
知である。
On the other hand, it is well known that by doping a high-purity GaAs film with n-type impurities, the formed GaAs film can be made n-type even if the impurities contained in the high-purity GaAs film are p-type.

本発明は、上述のことを利用したものである。The present invention takes advantage of the above.

従ってこの説明により、本発明の成長方法では、GaA
s膜のp型不純物がBeよりも熱拡散係数の小さいCと
なり、然も成長時の基板温度が従来方法の600〜70
0’Cよりも低くなることが容易に理解されよう。そし
てそのことは、P型GaAs膜の界面におけるキャリア
濃度プロファイルを従来方法の場合よりも急峻にさせる
Therefore, according to this explanation, in the growth method of the present invention, GaA
The p-type impurity of the S film is C, which has a smaller thermal diffusion coefficient than Be, and the substrate temperature during growth is 600-700℃ compared to the conventional method.
It will be easily understood that the temperature will be lower than 0'C. This makes the carrier concentration profile at the interface of the P-type GaAs film steeper than in the conventional method.

なお、本発明の成長方法において、高純度GaAs膜ま
たはn型GaAs膜の成長にTEGの分子線とAs、の
分子線を用いる場合は、p型GaAs膜の成長時と基板
温度を切り換えるのみで分子線を共通にしていることが
、また、高純度GaAs膜またはn型GaAs膜の成長
にTEGの分子線とアルシンの分子線を用いる場合は、
p型GaAs膜の成長時と分子線を切り換えるのみで基
板温度を共通にしていることが特徴となっている。
In addition, in the growth method of the present invention, when using TEG molecular beams and As molecular beams to grow a high-purity GaAs film or an n-type GaAs film, it is only necessary to change the substrate temperature when growing a p-type GaAs film. In addition, when using a common molecular beam, and when using a TEG molecular beam and an arsine molecular beam to grow a high-purity GaAs film or an n-type GaAs film,
A feature of this method is that the substrate temperature is kept the same during the growth of a p-type GaAs film by simply switching the molecular beam.

そして、後者の場合に基板温度の切り換えを行っても良
いことはいうまでもない。
It goes without saying that in the latter case, the substrate temperature may be switched.

〔実施例] 以下本発明による成長方法を用いた半導体装置製造の実
施例について、HBTを例にとった第2図の側断面図を
用いて説明する。
[Example] Hereinafter, an example of manufacturing a semiconductor device using the growth method according to the present invention will be described using the side cross-sectional view of FIG. 2, taking an HBT as an example.

第2図に示すHBTは、第3図のHBTにおけるエミツ
タ層5を、グレーデッドn −AlGaAs層5c。
In the HBT shown in FIG. 2, the emitter layer 5 in the HBT shown in FIG. 3 is replaced with a graded n-AlGaAs layer 5c.

n−AlGaAs層5b及びグレーデッドn −AlG
aAs層5cからなる3層構成のエミツタ層5Aにした
ものである。
n-AlGaAs layer 5b and graded n-AlG
The emitter layer 5A has a three-layer structure consisting of an aAs layer 5c.

このトランジスタの製造手順は第3図のHBTに準する
が、基板1上にコレクタコンタクト層2からエミッタコ
ンタクト層6までを成長する際に本発明の成長方法を適
用している。
The manufacturing procedure of this transistor is similar to that of the HBT shown in FIG. 3, but the growth method of the present invention is applied when growing from the collector contact layer 2 to the emitter contact layer 6 on the substrate 1.

この成長の実施例は次のようである。これは、高純度G
aAs膜またはn型GaAs膜の成長にTEGの分子線
とAs、の分子線を用いる場合に該当する。
An example of this growth is as follows. This is high purity G
This applies when using TEG molecular beams and As molecular beams to grow an aAs film or an n-type GaAs film.

即ち、基板1をMBE装置内に配置し、先ず、As、分
子線の照射下で基板1を600°C以上に加熱して基板
1表面の自然酸化膜を除去する。
That is, the substrate 1 is placed in an MBE apparatus, and first, the natural oxide film on the surface of the substrate 1 is removed by heating the substrate 1 to 600° C. or higher under irradiation with As and molecular beams.

次いで、基板温度を550°Cに設定し、A54分子線
の照射に780分子線及びSi分子線の照射を加えて、
Siを3X1018/cnlにドープしたn” −Ga
AsコレクタコンタクトN2を厚さ550nmに成長し
た後、Si分子線の強度を下げてSiを3X1016/
cn!にドープしたn−GaAsコレクタ層3を厚さ5
50nmに成長する。成長の停止は、780分子線およ
びSi分子線の照射を止めることによって行う。
Next, the substrate temperature was set at 550°C, and 780 molecular beam and Si molecular beam irradiation were added to the A54 molecular beam irradiation.
n”-Ga doped with Si to 3X1018/cnl
After growing the As collector contact N2 to a thickness of 550 nm, the intensity of the Si molecular beam was lowered and the Si was grown to 3X1016/
cn! The n-GaAs collector layer 3 doped with
Grows to 50 nm. Growth is stopped by stopping irradiation with the 780 molecular beam and the Si molecular beam.

次いで、As、分子線のみを照射したまま基板温度を4
30°Cに設定し、As、分子線の照射に780分子線
の照射を加えて、Cが1.5 X 10” / cnl
にドープされたp” −GaAsベース層4を厚さ 1
100nに成長し、780分子線の照射を止める。
Next, while irradiating only As and molecular beams, the substrate temperature was increased to 4.
Set at 30°C, add 780 molecular beam irradiation to As and molecular beam irradiation, and C is 1.5 x 10”/cnl.
A p”-GaAs base layer 4 doped with a thickness of 1
After growing to 100n, irradiation with the 780 molecular beam is stopped.

次いで、As、分子線のみを照射したまま基板温度を5
50°Cに設定し、As、分子線の照射に780分子線
、A1分子線及びSi分子線の照射を加えて、Siを5
X1017/cイにドープしたグレーデッドnAlGa
As層5a (厚さ50nm)  、n −AIGaA
s層sb (厚さ150nm)及びグレーデッドn −
AlGaAs層5c (厚さ30r++n)を順次成長
してエミツタ層5Aを形成する。
Next, while irradiating only As and molecular beams, the substrate temperature was increased to 5.
Set the temperature to 50°C, add 780 molecular beam, A1 molecular beam, and Si molecular beam irradiation to As and molecular beam irradiation to
Graded nAlGa doped with X1017/c
As layer 5a (thickness 50 nm), n-AIGaA
s layer sb (thickness 150 nm) and graded n −
An emitter layer 5A is formed by sequentially growing an AlGaAs layer 5c (thickness 30r++n).

次いで、グレーデッドn −AlGaAs層5cの厚さ
が30nmになったところで、A1分子線の照射を止め
ると共にSi分子線の強度を上げて、Siを5X  1
0”/Caにドープしたn−GaAsエミッタコンタク
ト層6を厚さ1100nに成長して、一連の成長を完了
する。
Next, when the thickness of the graded n-AlGaAs layer 5c reached 30 nm, the irradiation of the A1 molecular beam was stopped and the intensity of the Si molecular beam was increased to form a 5×1 layer of Si.
An n-GaAs emitter contact layer 6 doped with 0''/Ca is grown to a thickness of 1100 nm to complete the growth series.

このように成長して製造されたトランジスタは、先に述
べた従来の成長方法により製造された同一構成のトラン
ジスタと比べて、最大電流利得が30から40へと向上
していることが確認された。
It was confirmed that the maximum current gain of the transistor grown and manufactured in this way was improved from 30 to 40 compared to the transistor of the same configuration manufactured using the conventional growth method described above. .

次に、上記成長の他の実施例について説明する。Next, another example of the above growth will be described.

これは、高純度GaAs膜またはn型GaAs膜の成長
にTEGの分子線とアルシンの分子線を用いる場合に3
亥当する。
When using TEG molecular beams and arsine molecular beams to grow high-purity GaAs films or n-type GaAs films, 3
Inferred.

即ち、基板1をMBE装置内に配置し、先ず、920°
Cでクラッキングしたアルシン分子線の照射下で基板l
を600°C以上に加熱して基板1表面の自然酸化膜を
除去する。
That is, the substrate 1 is placed in an MBE apparatus, and first, the substrate 1 is rotated at 920°.
Substrate l under irradiation of arsine molecular beam cracked with C
The natural oxide film on the surface of the substrate 1 is removed by heating to 600° C. or higher.

次いで、基板温度を430°Cに設定し、上記アルシン
分子線の照射に780分子線及びSi分子線の照射を加
えて、Siを3X10”/CT11にドープしたn ”
−GaAsコレクタコンタクト層2を厚さ550nmに
成長した後、Si分、子線の強度を下げてSiを3×1
0”/cn!にドープしたn−GaAsコレクタ層3を
厚さ550nmに成長する。
Next, the substrate temperature was set at 430°C, and 780 molecular beam and Si molecular beam irradiation were added to the arsine molecular beam irradiation described above to form a 3×10”/CT11 Si-doped n”
- After growing the GaAs collector contact layer 2 to a thickness of 550 nm, the intensity of the consonant beam is lowered by the amount of Si, and the Si layer is grown to a thickness of 3×1.
An n-GaAs collector layer 3 doped to 0''/cn! is grown to a thickness of 550 nm.

次いで、コレクタ層3の厚さが550nmになったとこ
ろで、Si分子線の照射を止めると共に上記アルシン分
子線の照射をAs、分子線の照射に切り換えて、As4
分子線及び780分子線の照射にし、基板温度を430
°Cのままに維持して、Cが1.5×10”/c+fl
にドープされたp” −GaAsベース層4を厚さ11
00nに成長する。
Next, when the thickness of the collector layer 3 reached 550 nm, the irradiation with the Si molecular beam was stopped, and the irradiation with the arsine molecular beam was switched to the irradiation with the As4 molecular beam.
Molecular beam and 780 molecular beam irradiation, substrate temperature 430
Keep it at °C until C is 1.5×10”/c+fl
A p”-GaAs base layer 4 doped with a thickness of 11
Grows to 00n.

次いで、ベース層4の厚さが1100nになったところ
で、As、分子線の照射を上記アルシン分子線の照射に
切り換えると共に、アルシン分子線及び780分子線の
照射にA1分子線及びSi分子線の照射を加え、基板温
度を430″Cのままに維持して、Siを5×10′7
/c1i1にドープしたグレーデッドnAlGaAs層
5a (厚さ50nm) 、n −AlGaAs層5b
 (厚さ150nm)及びグレーデッドn  AlGa
As層5c (Jtさ30nm)を順次成長してエミツ
タ層5Aを形成する。
Next, when the thickness of the base layer 4 reached 1100 nm, the irradiation with As and molecular beams was switched to the irradiation with arsine molecular beams, and the irradiation with A1 molecular beams and Si molecular beams was replaced with the irradiation with arsine molecular beams and 780 molecular beams. Apply irradiation and maintain the substrate temperature at 430″C to reduce the Si to 5×10′7
/c1i1 doped graded nAlGaAs layer 5a (thickness 50 nm), n-AlGaAs layer 5b
(thickness 150nm) and graded n AlGa
An emitter layer 5A is formed by sequentially growing As layers 5c (Jt: 30 nm).

次いで、グレーデッドn−AlGaAs層5cの厚さが
30nmになったところで、At分子線の照射を止める
と共にSi分子線の強度を上げて、Stを5X  10
”/cTAにドープしたn−GaAsエミッタコンタク
ト層6を厚さloonmに成長して、一連の成長を完了
する。
Next, when the thickness of the graded n-AlGaAs layer 5c reached 30 nm, the irradiation of the At molecular beam was stopped, and the intensity of the Si molecular beam was increased to increase the St.
An n-GaAs emitter contact layer 6 doped with ``/cTA'' is grown to a thickness of 10m to complete the growth series.

なお、これらの成長におけるアルシンのクラッキング温
度は920°Cに限定されるものではない。
Note that the cracking temperature of arsine in these growths is not limited to 920°C.

このように成長して製造されたトランジスタの特性は、
先の実施例によるトランジスタとほぼ同じになることが
6′し召されて、従来の成長方法により製造された同一
構成のトランジスタよりも格段に向上している。
The characteristics of transistors grown and manufactured in this way are:
It is desired that the transistor be substantially the same as the transistor according to the previous embodiment, and is a significant improvement over a transistor of the same configuration manufactured by conventional growth methods.

以上に説明した実施例は、P型GaAs膜にn型GaA
s膜を組み合わせた場合であるが、n型GaAs膜の代
わりに高純度GaAs膜を組み合わせて例えばpinダ
イオードなどを製造する場合にも、P型GaAs膜の界
面におけるキャリア濃度プロファイルを急峻にさせるこ
とに対して本発明が極めて有効であることは、先の第1
図を用いた説明からして容易に理解されよう。
In the embodiment described above, an n-type GaAs film is added to a P-type GaAs film.
This is the case when combining an S film, but also when manufacturing a pin diode by combining a high purity GaAs film instead of an n-type GaAs film, the carrier concentration profile at the interface of the p-type GaAs film should be made steep. The fact that the present invention is extremely effective against
It will be easily understood from the explanation using the figures.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明の構成によれば、半導体装置
の製造方法、特に、分子線エピタキシー装置を用いて半
導体基板上にp型GaAs膜或いは、p型GaAs膜と
n型または高純度GaAs膜とを有する多層構成の半導
体膜を成長する方法において、GaAs膜のP型不純物
をBeよりも熱拡散係数が小さいCになし得て然も成長
時の基板温度を低くなし得るようになり、それによりp
型GaAs膜の界面におけるキャリア濃度プロファイル
を急峻にさせて当該半導体装置の特性改善を可能にさせ
る効果がある。
As explained above, according to the structure of the present invention, there is provided a method for manufacturing a semiconductor device, in particular, a p-type GaAs film, or a p-type GaAs film and an n-type or high-purity GaAs film on a semiconductor substrate using a molecular beam epitaxy apparatus. In a method for growing a semiconductor film with a multilayer structure having By p
This has the effect of making the carrier concentration profile at the interface of the GaAs film steeper, thereby making it possible to improve the characteristics of the semiconductor device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明を説明するキャリア濃度特性図、第2図
は実施例を説明するためのHBTO側断面図、 第3図はHBTの概要を示す側断面図、である。 図において、 lは半絶縁性GaAs基板、 2はn’−GaAsコレクタコンタクト層、3はn−G
aAs]レクタ層、 4はp’ −GaAsベース層、 5はn−AlGaAsエミック層、 5八はエミ・ンタ層、 5aはグレーデッドn −AIGaAs層、5bはn 
−AIGaAs層、 5cはグレーデッドn −AIGaAs層5c。 6はn  GaAsエミッタコンタクト層、である。 1000/75 (K−つ 苓拒逼度Ts   C’C) 、fee月゛ε、言兇e月マろシヘイ11ア濃虐牛杵々
任、瓜]第  l  2
FIG. 1 is a carrier concentration characteristic diagram for explaining the present invention, FIG. 2 is a side sectional view of an HBTO for explaining an embodiment, and FIG. 3 is a side sectional view showing an outline of the HBT. In the figure, l is a semi-insulating GaAs substrate, 2 is an n'-GaAs collector contact layer, and 3 is an n-G
4 is a p'-GaAs base layer, 5 is an n-AlGaAs emic layer, 58 is an emitter layer, 5a is a graded n-AIGaAs layer, 5b is an n-AlGaAs layer,
-AIGaAs layer, 5c is graded n-AIGaAs layer 5c. 6 is an n GaAs emitter contact layer. 1000/75 (K-Tsusei refusal Ts C'C), fee month ゛ε, saying 兇e月MARoshihei 11 A brutal cow persecution, melon] No. 1 2

Claims (3)

【特許請求の範囲】[Claims] (1)分子線エピタキシー装置を用いて、 トリエチルガリウムの分子線及び金属砒素の分子線によ
り成長するGaAs膜のキャリア濃度がほぼ最低となる
第1温度よりも低い第2温度に基板温度を設定し、上記
二つの分子線によりp型GaAs膜を成長することを特
徴とする半導体装置の製造方法。
(1) Using a molecular beam epitaxy device, the substrate temperature is set to a second temperature lower than the first temperature at which the carrier concentration of the GaAs film grown by triethyl gallium molecular beams and metallic arsenic molecular beams is approximately the lowest. . A method for manufacturing a semiconductor device, characterized in that a p-type GaAs film is grown using the above two molecular beams.
(2)分子線エピタキシー装置を用いて、 トリエチルガリウムの分子線及び金属砒素の分子線によ
り成長するGaAs膜のキャリア濃度がほぼ最低となる
第1温度よりも低い第2温度に基板温度を設定し、上記
二つの分子線によりp型GaAs膜を成長する工程と、 基板温度を上記第1温度に設定し、上記二つの分子線に
より高純度GaAs膜を成長するか、またはその際にn
型不純物の分子線を付加してn型GaAs膜を成長する
工程とを有することを特徴とする半導体装置の製造方法
(2) Using a molecular beam epitaxy device, set the substrate temperature at a second temperature lower than the first temperature at which the carrier concentration of the GaAs film grown by triethyl gallium molecular beams and metallic arsenic molecular beams is approximately the lowest. , a step of growing a p-type GaAs film using the two molecular beams, and setting the substrate temperature to the first temperature and growing a high-purity GaAs film using the two molecular beams, or
A method for manufacturing a semiconductor device, comprising the step of growing an n-type GaAs film by adding a molecular beam of a type impurity.
(3)上記請求項2記載の製造方法において、上記高純
度GaAs膜またはn型GaAs膜の成長の際に、基板
温度を上記p型GaAs膜成長時の温度と共通にし、上
記金属砒素の分子線の代わりにクラッキングしたアルシ
ンの分子線を用いることを特徴とする半導体装置の製造
方法。
(3) In the manufacturing method according to claim 2, when growing the high-purity GaAs film or the n-type GaAs film, the substrate temperature is made the same as the temperature during the growth of the p-type GaAs film, and the molecules of the metal arsenic are A method for manufacturing a semiconductor device, characterized in that a molecular beam of cracked arsine is used instead of a wire.
JP332089A 1989-01-10 1989-01-10 Method for manufacturing semiconductor device Expired - Lifetime JP2920923B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP332089A JP2920923B2 (en) 1989-01-10 1989-01-10 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP332089A JP2920923B2 (en) 1989-01-10 1989-01-10 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH02183518A true JPH02183518A (en) 1990-07-18
JP2920923B2 JP2920923B2 (en) 1999-07-19

Family

ID=11554061

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
JP (1) JP2920923B2 (en)

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