JP2004296636A - Nitride iii-v compound semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a nitride III-V compound semiconductor device having small transfer density of the nitride III-V compound semiconductor on a buffer layer and excellent electrical characteristics, and to provide the nitride III-V compound semiconductor device. <P>SOLUTION: A buffer layer 42 made of an AlN is formed on an SiC substrate 41, and further a Ga layer 43 is deposited on the buffer layer 42 made of the AlN. Thereafter, the surface of the Ga layer 43 is irradiated with a nitrogen source to rebuild this Ga layer 43 on the lower layer 44 of the GaN layer having a little number of transfers and the upper layer 45 of the GaN layer having further less number of transfers than the lower layer 44. Finally, a GaN layer 46 is formed on the upper layer 45 of the GaN layer having small number of the transfers and excellent crystallinity. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【００９９】
表１に示すように、１×１０^１９ｃｍ^−３の高キャリア濃度の場合、どの方法で窒化物系ＩＩＩ−Ｖ族化合物半導体装置を形成しても、ＧａＮ層の移動度は、略１００ｃｍ^２／Ｖｓ前後の値になり、４つの方法でＧａＮ層の電気的特性に違いが見られない。一方、１×１０^１６ｃｍ^−３の低キャリア濃度の場合、通常の方法で製作されたＧａＮ層の移動度と、他の３つの方法（すなわち、本発明の第１、第２および第３実施形態の方法）で製作されたＧａＮ層の移動度との間に、顕著な違いが見られる。
【０１００】
図９に、通常の窒化物系ＩＩＩ−Ｖ族化合物半導体装置の製造方法と、第１、第２および第３実施形態の窒化物系ＩＩＩ−Ｖ族化合物半導体装置の製造方法で作製された４通りの窒化物系ＩＩＩ−Ｖ族化合物半導体装置のＧａＮ層のキャリア濃度と移動度との関係を示す。
【０１０１】
図９に示す丸印は、通常の窒化物系ＩＩＩ−Ｖ族化合物半導体装置の製造方法を用いた場合の計測点であり、表１の結果をプロットしたものである。一方、図９に示す四角印は、第１、第２および第３実施形態の窒化物系ＩＩＩ−Ｖ族化合物半導体装置の製造方法を用いた場合の計測点であり、表１の結果をプロットしたものである（図９の縮尺の尺度では、第１、第２および第３実施形態の違いを示せず、３つの実施形態は図上で同じ点をさす）。
【０１０２】
図９に示すように、キャリア濃度が１×１０^１７．３ｃｍ^−３以上の領域においては、同じキャリア濃度に対する移動度が、４つの方法で同等になっており、キャリア濃度が下がるにつれて、移動度が増加していることがわかる。
【０１０３】
一方、キャリア濃度が下がって１×１０^１７．３ｃｍ^−３に達すると、図９に示すように、通常の方法の移動度と、本発明の３つの実施形態の方法の移動度とが分岐することがわかる。詳細には、キャリア濃度が１×１０^１５ｃｍ^−３以上で１×１０^１７．３ｃｍ^−３未満の領域においては、通常の方法では、キャリア濃度が下がるにつれて、移動度も減少するのに対し、本発明の３つの方法では、キャリア濃度が下がるにつれて、移動度が増加していることがわかる。つまり、通常の方法と本発明の３つの方法で、移動度の振る舞いに大きな違いが生じていることがわかる。
【０１０４】
これは、ＧａＮ層の移動度μが、以下の式（１）に示すように、キャリア濃度ｎの１．５乗と転位密度Ｎ_{ｄｉｓｌ．}により決定されるからである。
【０１０５】
【数１】

【０１０６】
詳細には、キャリア濃度が大きい場合には、キャリア濃度ｎの１．５乗の値が大きくなるので、ＧａＮの移動度μは、上記式（１）により、主にキャリア濃度ｎの１．５乗の因子によって決定される。これは、キャリア濃度が大きくなるとキャリア同士の衝突が頻繁に起こって、キャリア‐キャリア散乱で移動度μが決定されることを意味している。つまり、キャリア濃度が１×１０^１９ｃｍ^−３等の大きな領域では、移動度μは、ｎの１．５乗の値だけで略決定され、転位密度Ｎ_ｄｉｓｌの影響を受けにくくなる。これが、キャリア濃度が１×１０^１９ｃｍ^−３で、移動度μが、いずれの方法でも１００ｃｍ^２／Ｖｓ前後の値になることの理由である。
【０１０７】
一方、キャリア濃度が１×１０^１６ｃｍ^−３等の小さい領域では、式（１）の分子の値が小さくなり、移動度μは転位密度Ｎ_ｄｉｓｌの影響を大きく受けることになる。これが、キャリア濃度が１×１０^１６ｃｍ^−３では、転位が多い通常の成長法では移動度が３０ｃｍ^２／Ｖｓ程度にしかならない一方、転位が少ない本発明の方法では移動度が１５００ｃｍ^２／Ｖｓ程度の大きな値になることの理由である。つまり、本発明の方法で作成したＧａＮ層では、通常の成長法とは異なり、キャリア濃度が１０^１２ｃｍ^−３程度以下にならないと転位が支配的な領域には入らないのである。すなわち、本発明の方法を用いれば、転位が少ないＧａＮ層を形成できるので、キャリア濃度が小さい領域においても、大きな移動度μを得ることができるのである。
【０１０８】
図１０に、窒化物系ＩＩＩ−Ｖ族化合物半導体装置の一例としてのＨＥＭＴ（高電子移動度トランジスタ）の構造を示す。
【０１０９】
図１０において、１０１はサファイア基板の（０００１）面、１０２は低温成長させた膜厚２０ｎｍのＧａＮバッファ層、１０３はＧａＮ層（バックグラウンドキャリア濃度１０^１６ｃｍ^−３以下、膜厚３μｍ）、１０４はＡｌ_０．２５Ｇａ_０．７５Ｎ層（膜厚３０ｎｍ）、１０５はＨｆ（ハフニウム）ソース／ドレイン電極、１０６はＰｄ（パラジウム）ゲート電極である。
【０１１０】
次に、図１０に示す層構造を有するＨＥＭＴ（高電子移動度トランジスタ）を、ＭＯＣＶＤ法を用いた通常の方法およびＭＯＣＶＤ法を用いた第１、第２および第３実施形態の方法で作成し、４つのＨＥＭＴのヘテロ構造特性およびＨＥＭＴ特性を比較した。
【０１１１】
以下に、４つのＨＥＭＴの作製法について要点のみ簡単に述べる。
【０１１２】
初めに、通常の場合には、先ず、水素雰囲気中でサファイア基板の基板温度を１１００℃にして、サファイア基板の酸化膜を除去するクリーニングを１０分間行った後、サファイア基板の基板温度を５００℃、Ｇａ原料流量（トリメチルガリウムＴＭＧ）の流量を１０ｓｃｃｍ、ＨＮ_３の流量を５ｓｌｍに夫々設定してＧａＮバッファ層を成長させる。
【０１１３】
次に、基板温度を１０００℃、Ｇａ原料（トリメチルガリウムＴＭＧ）の流量を４０ｓｃｃｍに設定して、ＧａＮ層を成長させた後、基板温度を１０００℃、トリメチルアルミニウム（ＴＭＡ）流量を５ｓｃｃｍ、ＴＭＧの流量を２５ｓｃｃｍ、ＮＨ_３の流量を６ｓｌｍに夫々設定してＡｌ_０．２５Ｇａ_０．７５Ｎ層を成長させる。
【０１１４】
最後に、Ａｌ_０．２５Ｇａ_０．７５Ｎ層にＨｆ（ハフニウム）ソース／ドレイン電極、Ｐｄ（パラジウム）ゲート電極を形成してＨＥＭＴが作製される。
【０１１５】
次に、本発明の第１実施形態の方法では、ＧａＮバッファ層成長後にＴＭＧのみを流してＧａを堆積して温度を上げながら窒素源としてのＮＨ_３を流してＧａを結晶化する。
【０１１６】
また、本発明の第２実施形態の方法では、バッファ層成長後にＴＥＧのみを流してＧａを堆積した後、引き続いて成長温度を５００℃にして２０ｎｍ程度のＧａＮ層を形成する。その後、基板温度を上げてＧａＮを成長させて、成長中断後に基板温度を１０５０℃に上げて１分間熱処理し、引き続いて１０００℃でへテロ構造を成長させる。
【０１１７】
最後に、本発明の第３実施形態の方法では、低温バッファ層成長後にＧａＮ層を成長させた後、イオン注入を行う。その後、１０５０℃で１分間の熱処理を行い、この熱処理に引き続いて１０００℃でヘテロ構造を形成する。
【０１１８】
尚、上記４つの方法では、ゲート長Ｌｇが０．１μｍ、ゲート幅Ｗｇが２００μｍのＨＥＭＴを製造した。
【０１１９】
表２に、従来の方法と、第１、第２および第３実施形態の方法で製造した４つのＨＥＭＴの特性比較結果を示す。
【０１２０】
【表２】

【０１２１】
尚、表２において、ＤＣ／ＲＦ分散率は、直流印加時の特性と高周波印加時の特性の変化率であり、この値が小さいと、ＨＥＭＴ特性は、高周波応用に優れたものになる。
【０１２２】
表２に示すように、通常の方法と本発明の方法（第１，第２および第３実施形態の方法）では、転位密度が２桁程度異なっているが、ヘテロ構造の電気的特性を示す移動度、ＨＥＭＴ特性である相互コンダクタンスｇ_ｍおよび最大発信周波数ｆ_ｍａｘに大きな違いは見られない。しかしながら、トラップとして働いていた転位密度が小さくなるため、本発明の方法（第１，第２および第３実施形態の方法）では、通常の方法と比較して、ＤＣ／ＲＦ分散率が３０％から１０％以下に大きく減少し、ＨＥＭＴ特性が大きく改善されている。
【０１２３】
尚、上記ＨＥＭＴを形成するにあたって、各層をＭＯＣＶＤ法を用いて成長させたが、ＲＦ−ＭＢＥ法以外の分子線エキタピシー装置を用いた結晶成長法でもＭＯＣＶＤ法と同様の改善が見られることが確認されている（ＲＦ−ＭＢＥ法を用いた成長方法では、転位が多いために移動度が極端に小さくて、十分なＨＥＭＴ特性が出ないことが確認されている）。
【０１２４】
【発明の効果】
以上より明らかなように、第１、第２および第３の発明の窒化物系ＩＩＩ−Ｖ族化合物半導体装置の製造方法によれば、窒化物系ＩＩＩ−Ｖ族化合物半導体からなるバッファ層の上方の窒化物系ＩＩＩ−Ｖ族化合物半導体層の転位を小さくできて、このバッファ層の上方の窒化物系ＩＩＩ−Ｖ族化合物半導体層の移動度等の電気的特性を優れたものにすることができる。したがって、この転位が小さくて電気的特性に優れた窒化物系ＩＩＩ−Ｖ族化合物半導体層を有するＨＦＥＴ等の窒化物系ＩＩＩ−Ｖ族化合物半導体装置の移動度や高周波特性等の電気的特性を優れたものにすることができる。
【０１２５】
また、第４の発明の窒化物系ＩＩＩ−Ｖ族化合物半導体装置は、Ｇａを堆積する工程で堆積されたＧａ層を用いてＧａの拡散を行い、このＧａ層よりも上方に形成された窒化物系ＩＩＩ−Ｖ族化合物半導体層の転位を低減した窒化物系ＩＩＩ−Ｖ族化合物半導体装置であるので、結晶性および電気的特性が優れたものになる。
【０１２６】
また、第５の発明の窒化物系ＩＩＩ−Ｖ族化合物半導体装置は、例えば、イオン打ち込み工程等のアモルファス化を行う工程の後、例えば、熱処理工程等で、アモルファスの層の上方の層が再結晶化された装置であるので、第５の発明の窒化物系ＩＩＩ−Ｖ族化合物半導体装置の再結晶化された層の転位密度が小さくなり、電気的特性が優れたものになる。
【図面の簡単な説明】
【図１】第１の発明の窒化物系ＩＩＩ−Ｖ族化合物半導体装置の製造方法の製造工程の原理を説明する模式図である。
【図２】第２の発明の窒化物系ＩＩＩ−Ｖ族化合物半導体装置の製造方法の製造工程の原理を説明する模式図である。
【図３】第３の発明の窒化物系ＩＩＩ−Ｖ族化合物半導体装置の製造方法の製造工程の原理を説明する模式図である。
【図４】本発明の第１実施形態の窒化物系ＩＩＩ−Ｖ族化合物半導体装置の製造方法の製造工程を示す図である。
【図５】本発明の第２実施形態の窒化物系ＩＩＩ−Ｖ族化合物半導体装置の製造方法の製造工程の一部を示す図である。
【図６】図５に続く窒化物系ＩＩＩ−Ｖ族化合物半導体装置の製造方法の製造工程の一部を示す図である。
【図７】本発明の第３実施形態の窒化物系ＩＩＩ−Ｖ族化合物半導体装置の製造方法の製造工程の一部を示す図である。
【図８】図７に続く窒化物系ＩＩＩ−Ｖ族化合物半導体装置の製造方法の製造工程の一部を示す図である。
【図９】窒化物系ＩＩＩ−Ｖ族化合物半導体装置のキャリア濃度と移動度との関係を示す図である。
【図１０】窒化物系ＩＩＩ−Ｖ族化合物半導体装置の一例としてのＨＥＭＴ（高電子移動度トランジスタ）の構造を示す図である。
【符号の説明】
１，２１，３１ バッファ層
２，２２，４３，５３ Ｇａ層
３，４６，５４，５５，５６，７３，７５，７６，１０３ ＧａＮ層
４，４４ ＧａＮ層の下層部
５，５５ ＧａＮ層の上層部
２３，２５，３２ 窒化物系ＩＩＩ−Ｖ族化合物半導体層
３５，７４ アモルファスの層
４１，５１，７１ ＳｉＣ基板
４２，５２，７２ ＡｌＮのバッファ層
１０１ サファイア基板
１０２ ＧａＮバッファ層
１０４ ＡｌＧａＮ層
１０５ ソース／ドレイン電極
１０６ ゲート電極[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a nitride-based III-V compound semiconductor device and a nitride-based III-V compound semiconductor device, and more particularly to a semiconductor laser and a light-emitting diode having a nitride-based III-V compound semiconductor layer. Also, the present invention relates to a method for manufacturing a nitride III-V compound semiconductor device such as a HEMT (High Electron Mobility Transistor) and a nitride III-V compound semiconductor device.
[0002]
[Prior art]
Conventionally, as a nitride III-V compound semiconductor device, a device using sapphire as a substrate material (for example, see Patent Document 1) and a device using SiC as a substrate material (for example, see Patent Document 2) is there. These nitride III-V compound semiconductor devices have a heterostructure having a nitride III-V compound semiconductor above each substrate. When a nitride-based III-V compound semiconductor is grown on a sapphire substrate, a C-plane is usually used. However, even when an A-plane, an R-plane, or an M-plane is used, the nitride-based III-V It has been clarified that a -V group compound semiconductor grows on the C-plane. This is because the nitride III-V compound semiconductor has a hexagonal crystal structure (wurtzite structure), so that the nitride III-V compound semiconductor has an energetically stable C-axis orientation (C-plane). Growth).
[0003]
As another nitride-based III-V compound semiconductor device, there is a device using Si as a substrate material. In particular, a device that inserts SiC between a Si substrate and a nitride-based III-V compound semiconductor is used. (For example, see Patent Document 3). As another apparatus using Si as a substrate material, there is an apparatus for inserting polycrystalline Si between a Si substrate and a nitride III-V compound semiconductor (for example, see Patent Document 4).
[0004]
The nitride-based III-V compound semiconductor device is not limited to the device using the sapphire substrate, the SiC substrate, or the Si substrate, but may be any device using any substrate. In order to alleviate the difference in lattice constant, the difference in thermal expansion coefficient or the difference in crystal structure between GaN and AlN (a high temperature in the case of AlN, (A growth is also possible).
[0005]
Further, as a further nitride-based III-V compound semiconductor device, after growing a nitride-based III-V compound semiconductor on a substrate, the substrate is removed to remove the nitride-based III-V compound semiconductor. There is an apparatus using a new substrate material (for example, see Patent Document 5).
[0006]
[Patent Document 1]
U.S. Pat. No. 5,296,395
[Patent Document 2]
JP 2001-177189 A
[Patent Document 3]
JP 2001-17190 A
[Patent Document 4]
JP 2001-7396 A
[Patent Document 5]
JP-A-10-70079
[0007]
[Problems to be solved by the invention]
However, in the nitride-based III-V compound semiconductor devices disclosed in Patent Documents 1 to 4, generally, a large number of dislocations are present in the buffer layer made of GaN or AlN. The crystal structure of the nitride III-V compound semiconductor on the buffer layer is affected, the crystal structure of the nitride III-V compound semiconductor is deteriorated, and the movement of the nitride III-V compound semiconductor device is caused. There is a problem that electrical characteristics such as the degree are deteriorated.
[0008]
For example, when a nitride-based III-V compound semiconductor is grown at a high temperature on a buffer layer using MOCVD (metal organic chemical vapor deposition) or GSMBE (gas source molecular beam epitaxy), the nitride The growth mode of the group III-V compound semiconductor becomes the grain growth mode, and the influence of many dislocations in the buffer layer is likely to affect the nitride group III-V compound semiconductor on the buffer layer. However, there is a problem that this occurs in the nitride III-V compound semiconductor. Then, as the large number of grains grow in the lateral direction, the fusion plane of the different grains shifts, and a large number of dislocations occur in the nitride III-V compound semiconductor on the buffer layer, and the nitride III-V There is a problem that electrical characteristics such as mobility of the group III compound semiconductor device are further deteriorated. More specifically, when a nitride III-V compound semiconductor is grown using MOCVD, the dislocation density of the nitride III-V compound semiconductor becomes 10%. ⁸ cm ^-2 From 10 ⁹ cm ^-2 It has been found that the value of the nitride III-V is high using RF-MBE (molecular beam epitaxy using high frequency) or ECR-MBE (molecular beam epitaxy using electron cyclotron resonance). When a group III compound semiconductor is grown, the dislocation density of the nitride III-V compound semiconductor becomes 10%. ⁹ cm ^-2 From 10 ¹⁰ cm ^-2 It has been found that the value is much larger.
[0009]
On the other hand, even in the case of the device disclosed in Patent Document 5, since the dislocation density of the nitride-based III-V compound semiconductor layer is determined by the properties of the substrate before being removed and the growth method of each layer, The dislocation density of the nitride III-V compound semiconductor on the buffer layer is 10 ⁸ cm ^-2 From 10 ⁹ cm ^-2 As in the case of using a sapphire substrate, a SiC substrate, or a Si substrate, there is a problem that electrical characteristics such as mobility of the nitride-based III-V compound semiconductor device deteriorate.
[0010]
Therefore, an object of the present invention is to provide a method of manufacturing a nitride-based III-V compound semiconductor device having a small dislocation density of a nitride-based III-V compound semiconductor on a buffer layer and having excellent electrical characteristics, and a nitride. It is an object of the present invention to provide a system III-V compound semiconductor device.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, a method for manufacturing a nitride III-V compound semiconductor device according to a first aspect of the present invention provides a buffer layer forming step of forming a buffer layer made of a nitride III-V compound semiconductor on a substrate. A Ga deposition step of depositing a Ga layer on the buffer layer; a crystallization step of irradiating a surface of the Ga layer deposited in the Ga deposition step with a nitrogen source to crystallize as a GaN layer; And a compound semiconductor growing step of growing a nitride-based III-V compound semiconductor layer on the GaN layer.
[0012]
According to the first aspect, Ga is deposited in the Ga deposition step on the buffer layer having dislocations formed on the substrate in the buffer layer formation step, and N is further deposited on the surface of Ga in the crystallization step. Since the source is irradiated and crystallized as a GaN layer, the number of dislocations (ie, dangling bonds (line defects)) in the lower layer of the GaN layer crystallized by the irradiation of the N source is determined by the dislocation information from the buffer layer. The number of dislocations in the Ga layer before the crystallization is greatly affected by the influence of the above, and the crystal structure of the lower layer of the GaN layer becomes a high-quality crystal structure with few dislocations. Therefore, the crystal structure of the lower layer of the GaN layer has a high quality with dangling bonds eliminated, and the crystal structure of the upper layer of the crystallized GaN layer has the same structure as that of the dangling bond of the underlying buffer layer. It is possible to prevent dislocation information from reaching the information and to transmit only information other than dislocation information in the crystal structure of the underlying buffer layer to the upper layer of the GaN layer. From this, the crystal structure of the upper layer of the GaN becomes substantially the same as the crystal structure of the buffer layer having no dislocation, and in the next compound semiconductor growth step, the upper layer of the high-quality GaN layer having few dislocations is formed. The dislocation density of the nitride III-V compound semiconductor layer formed thereon can be reduced. Therefore, a nitride III-V compound semiconductor device having excellent electrical characteristics such as mobility can be provided.
[0013]
Incidentally, the dislocation density of the nitride III-V compound semiconductor layer formed in the compound semiconductor growth step of the method of the first invention is about 10%, which is almost the same as that of the GaAs semiconductor. ⁵ cm ^-2 The following small dislocation density was obtained.
[0014]
Further, according to a second aspect of the present invention, there is provided a method of manufacturing a nitride-based III-V compound semiconductor device, comprising the steps of: forming a buffer layer made of a nitride-based III-V compound semiconductor on a substrate; After a Ga deposition step of depositing a Ga layer thereon, a first compound semiconductor growth step of growing a first nitride III-V compound semiconductor layer on the Ga layer, and after the first compound semiconductor growth step A heat treatment step of performing a heat treatment, and a second compound semiconductor growth step of growing a second nitride III-V compound semiconductor layer after the heat treatment step.
[0015]
In the second invention, Ga is deposited in a Ga deposition step on the buffer layer having dislocations formed on the substrate in the buffer layer formation step, and subsequently, Ga is deposited on the Ga layer in a first compound semiconductor growth step. A first nitride III-V compound semiconductor layer such as GaN is grown. Further, in the heat treatment step, Ga deposited in the Ga deposition step is evaporated from the surface through the dislocation of the nitride-based III-V compound semiconductor layer such as GaN, and thereafter, in the second compound semiconductor growth step, the second A nitride III-V compound semiconductor layer is grown.
[0016]
According to the second aspect, since the heat treatment is performed in the heat treatment step, the Ga in the Ga layer is removed from the first nitride III- until the excess Ga in the Ga layer evaporates from the surface through the dislocation portion. The Ga can be moved toward the group V compound semiconductor layer, and the remaining Ga in the Ga layer can be moved to and stay near the dislocation of the first nitride III-V compound semiconductor layer on the Ga layer. . Therefore, the dislocations in the first nitride III-V compound semiconductor layer can be eliminated by the retained Ga, and the crystallinity of the first nitride III-V compound semiconductor layer is reduced. It can be of good quality. From this, in the second compound semiconductor growth step, the second nitride III-V compound semiconductor layer formed on the high quality first nitride III-V compound semiconductor layer with less dislocations is formed. The number of dislocations is even smaller than the number of dislocations in the first nitride III-V compound semiconductor layer, and the second nitride formed on the first nitride III-V compound semiconductor layer The crystallinity of the system III-V compound semiconductor layer becomes higher than that of the first nitride III-V compound semiconductor layer. Therefore, the electrical characteristics such as the mobility of the nitride III-V compound semiconductor device are improved.
[0017]
In one embodiment, the method for manufacturing a nitride III-V compound semiconductor device is characterized in that, in the Ga deposition step, a Ga layer having a thickness of 0.1 nm or more and 10 nm or less is deposited.
[0018]
According to the above embodiment, Ga having a thickness of 0.1 nm or more and 10 nm or less is deposited in the Ga deposition step, so that dislocations of the nitride III-V compound semiconductor on the Ga layer are sufficiently eliminated. As a result, the crystallinity of the nitride III-V compound semiconductor on the Ga layer can be improved.
[0019]
The present inventors changed the thickness of the Ga layer, grew a nitride III-V compound semiconductor thereon, and measured the crystallinity and dislocation density of the nitride III-V compound semiconductor with a transmission electron microscope ( (TEM).
[0020]
At this time, if the thickness of the Ga layer deposited in the Ga deposition step is smaller than 0.1 nm, dislocations of the nitride III-V compound semiconductor on the Ga deposited layer cannot be sufficiently eliminated, Also, when the thickness of Ga deposited in the Ga deposition step is greater than 10 nm, the crystallinity of the nitride III-V compound semiconductor on the Ga layer deteriorated. On the other hand, when the thickness of Ga deposited in the Ga deposition step is 0.1 nm or more and 10 nm or less, dislocation of the nitride III-V compound semiconductor on the Ga layer can be sufficiently eliminated. In addition, the crystallinity of the nitride III-V compound semiconductor on the Ga layer was improved.
[0021]
In a third aspect of the invention, there is provided a method of manufacturing a nitride III-V compound semiconductor device, comprising the steps of: forming a buffer layer made of a nitride III-V compound semiconductor on a substrate; A compound semiconductor growing step of growing a nitride-based III-V compound semiconductor layer thereon; and implanting ions near the interface between the buffer layer and the nitride-based III-V compound semiconductor layer so that the vicinity of the interface is amorphous. And a heat treatment step of performing a heat treatment after the ion implantation step.
[0022]
According to the third aspect, the buffer layer is formed on the substrate in the buffer layer forming step, and the buffer layer is formed of the nitride III-V compound semiconductor layer, and is grown on the buffer layer in the compound semiconductor growing step. Since ions are implanted in the vicinity of the interface with the nitride-based III-V compound semiconductor layer in the ion implantation step, the vicinity of the interface between the buffer layer and the nitride-based III-V compound semiconductor layer is made amorphous by the ion implantation. Thus, the buffer layer and the nitride III-V compound semiconductor layer can be separated by the amorphous layer existing near the interface. In a heat treatment step to be performed next, heat treatment is performed, so that the nitride III-V compound semiconductor on the amorphous layer formed near the interface between the buffer layer and the nitride III-V compound semiconductor layer is formed. The layer can be recrystallized, and the dislocation density of the recrystallized nitride III-V compound semiconductor layer can be reduced. Therefore, the dislocations of the nitride-based III-V compound semiconductor layer on the buffer layer, which contain many dislocations less than the buffer layer, can be effectively eliminated, and the nitride-based III-V The electrical characteristics of the group III compound semiconductor device can be improved.
[0023]
In one embodiment, the method for manufacturing a nitride-based III-V compound semiconductor device is characterized in that the implanted ions are at least one of C, N, Mg, Al, Zn, Ga and In. Features.
[0024]
According to the above embodiment, the ions to be implanted are p-type with respect to Al, Ga, In, N and the nitride III-V compound semiconductor layers, which are the elements forming the nitride III-V compound semiconductor layer. Since it is limited to at least one of C, Mg, and Zn which are elements serving as impurities, for example, when Si ions serving as n-type impurities are implanted into a nitride-based III-V compound semiconductor layer. In addition, a high-concentration n-type layer is not formed at the interface. For this reason, for example, if a field-effect transistor is manufactured using the method for manufacturing a nitride III-V compound semiconductor device of the above-described embodiment, the interface between the buffer layer and the nitride III-V compound semiconductor layer can be improved. Since a high-concentration n-type layer cannot be formed, parallel conduction does not occur between the n-type layer and a channel layer, which is a path through which current flows. From this, it is possible to realize a large current of the nitride III-V compound semiconductor device. The parallel conduction is a phenomenon in which a current flows through two paths of a high-concentration n-type layer existing at an interface between a channel layer and a buffer layer and a nitride III-V compound semiconductor layer due to a two-dimensional electron gas. It is. When this parallel conduction occurs, there arises a problem that the pinch-off of the transistor does not occur sufficiently.
[0025]
In one embodiment, in the method for manufacturing a nitride-based III-V compound semiconductor device, the temperature of the heat treatment step is set to a growth temperature of a nitride-based III-V compound semiconductor layer formed before the heat treatment step. And a temperature lower than a temperature obtained by adding 200 ° C. to the growth temperature.
[0026]
According to the above embodiment, in the heat treatment step, the growth temperature of the nitride-based III-V compound semiconductor layer formed before the heat treatment step is higher than that of the nitride-based III-V compound semiconductor layer before the heat treatment step. Since the heat treatment is performed at a temperature lower than the temperature obtained by adding 200 ° C. to the growth temperature of the −V group compound semiconductor layer, dislocations in the nitride III-V compound semiconductor layer can be reduced and the dislocation density can be reduced.
[0027]
The inventor performed the heat treatment at the same growth temperature as the growth temperature of ± 100 ° C., ± 200 ° C., and + 250 ° C., and evaluated by TEM how the dislocation density and crystallinity changed. . The surface state after the heat treatment was evaluated by a scanning electron microscope (SEM).
[0028]
At this time, when the heat treatment temperature of the heat treatment step is lower than the growth temperature of the nitride III-V compound semiconductor layer formed before the heat treatment step, the deposition of the Ga layer and the heat treatment step In the case where a nitride-based III-V compound semiconductor layer is grown, in this heat treatment step, Ga of the stacked Ga layer is sufficiently diffused into the nitride-based III-V compound semiconductor layer to form a nitride. In the case where dislocations in the system III-V compound semiconductor layer cannot be eliminated and an ion implantation step is performed before the heat treatment step, the nitride-based nitride layer on the generated amorphous layer is formed by implanting ions. The recrystallization of the III-V compound semiconductor layer could not be sufficiently performed, and the dislocations in the nitride III-V compound semiconductor layer could not be sufficiently reduced. On the other hand, when the heat treatment temperature in the heat treatment step becomes higher than the temperature obtained by adding 200 ° C. to the growth temperature of the nitride III-V compound semiconductor layer formed before the heat treatment step, the nitride III-V Evaporation of the group V compound semiconductor layer occurred.
[0029]
A fourth aspect of the present invention is a nitride-based III-V compound semiconductor device in which a nitride-based III-V compound semiconductor layer is formed above a substrate. A part of the nitride-based III-V compound semiconductor layer is characterized in that a stoichiometric ratio of a group III element and a nitrogen element (group III element / nitrogen) is 1 or more and 1.5 or less. .
[0030]
Note that the stoichiometric ratio is a value indicating a quantitative relationship between elements constituting the compound.
[0031]
The present inventor conducted an experiment using Auger electron spectroscopy (AES) to examine how the stoichiometric ratio changes while etching a nitride-based III-V compound semiconductor layer with Ar ions. . Further, the relationship between the stoichiometric ratio and the crystallinity was also evaluated by TEM.
[0032]
As a result, the nitride-based III-V compound semiconductor device manufactured by using the step of depositing Ga and the step of diffusing Ga such as the heat treatment step includes the steps of depositing Ga and performing the heat treatment step. Unlike the nitride-based III-V compound semiconductor device manufactured without using the step of diffusing, a region having a large number of Ga atoms is present, and in the region having a large number of Ga atoms, the number of Ga elements is reduced by a nitrogen element. It was confirmed that the stoichiometric ratio of the group III element to the nitrogen element (group III / nitrogen) became a large value of 1 or more and 1.5 or less.
[0033]
According to the fourth aspect, in a part of the nitride-based III-V compound semiconductor layer on the substrate, the stoichiometric ratio of the group III element to the nitrogen element (group III / nitrogen) is 1 or more and 1. The nitride-based III-V compound semiconductor device having the number of 5 or less is manufactured by using a step of depositing Ga and a step of diffusing Ga such as a heat treatment step. Therefore, the nitride III-V compound semiconductor device according to the fourth aspect of the present invention uses the Ga layer deposited in the step of depositing Ga to form a nitride III-V compound above the Ga layer. Since it is a nitride III-V compound semiconductor device in which Ga is diffused to reduce dislocations in the semiconductor layer, the crystallinity and electrical characteristics of the nitride III-V compound semiconductor device of the fourth invention But it will be excellent.
[0034]
Further, according to a fifth aspect of the present invention, there is provided a nitride-based III-V compound semiconductor device having a nitride-based III-V compound semiconductor layer formed above a substrate. A part of the nitride III-V compound semiconductor device is amorphous.
[0035]
In a nitride-based III-V compound semiconductor device in which dislocation density is reduced by using a process of making a part of a grown layer amorphous, such as an ion implantation process, a nitride-based III-V compound semiconductor device that does not become amorphous Unlike this, an amorphous portion remains in a part of the nitride III-V compound semiconductor device. In the nitride-based III-V compound semiconductor device according to the fifth aspect of the present invention, since a part of the nitride-based III-V compound semiconductor layer on the substrate is amorphous, a growth layer such as an ion implantation step is formed. It is manufactured using a process of partially amorphizing. Therefore, in the fifth nitride III-V compound semiconductor device, for example, after a step of performing amorphization such as an ion implantation step, a layer above the amorphous layer is recrystallized by a heat treatment step or the like. The recrystallized layer has a low dislocation density. From this, the crystallinity and electrical characteristics of the nitride III-V compound semiconductor device of the fifth invention are improved.
[0036]
In one embodiment, at least one of C, Mg, and Zn exists in the amorphous portion, or a stoichiometric ratio of a group III element to nitrogen. (Group III element / nitrogen) has a portion of 1 or more and 1.5 or less in the amorphous portion, or the stoichiometric ratio of nitrogen to the group III element (nitrogen / Group III element) is 1 It is characterized in that a portion not less than 1.5 and not more than 1.5 exists in the amorphous portion.
[0037]
The group III element required for calculating the stoichiometric ratio is assumed to be, for example, Al, Ga, or In.
[0038]
The present inventor conducted an experiment using Auger electron spectroscopy (AES) to examine how the stoichiometric ratio changes while etching a nitride-based III-V compound semiconductor layer with Ar ions. . Further, the relationship between the stoichiometric ratio and the crystallinity was also evaluated by TEM.
[0039]
As a result, when at least one of C, Mg, and Zn is implanted to partially amorphize the growth layer, at least one of C, Mg, and Zn exists in that portion, and nitrogen is implanted. When a part of the growth layer is made amorphous by the above, the stoichiometric ratio of the group III element and nitrogen is biased toward the one having more nitrogen, and the stoichiometric ratio of nitrogen and the group III element (nitrogen / group III) is increased. One or more and 1.5 or less parts were present. When at least one of Al, Ga and In is implanted to partially amorphize the growth layer, the stoichiometric ratio between at least one of Al, Ga and In and nitrogen is changed to Al. , Ga, and In are biased toward the larger one, and a stoichiometric ratio of group III element to nitrogen (group III / nitrogen) is 1 or more and 1.5 or less.
[0040]
According to the above embodiment, at least one of C 2, Mg and Zn is present in the amorphous portion, or the stoichiometric ratio of group III element to nitrogen (group III / nitrogen) is 1 or more and 1. A portion of 5 or less is present in the amorphous portion, or a portion having a stoichiometric ratio of nitrogen to a group III element (nitrogen / group III) of 1 or more and 1.5 or less is present in the amorphous portion. . Therefore, the nitride-based III-V compound semiconductor device according to the above-described embodiment includes at least one of the elements Al, Ga, In, and N forming the nitride-based III-V compound semiconductor layer, or the nitride. It is manufactured using a process of implanting at least one of C, Mg, and Zn ions serving as p-type impurities into the system III-V compound semiconductor layer to make a part of the growth layer amorphous. . For this reason, the nitride III-V compound semiconductor device of this embodiment has a high concentration of n at the interface like a nitride III-V compound semiconductor device into which Si ions serving as n-type impurities are implanted. Since no mold layer is formed and parallel conduction does not occur, a large current can flow through the nitride III-V compound semiconductor device.
[0041]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
[0042]
First, the principle of a method for manufacturing a three-way nitride III-V compound semiconductor device of the present invention will be briefly described with reference to FIGS.
[0043]
FIG. 1 is a diagram for explaining the principle of a method for manufacturing a nitride III-V compound semiconductor device according to the first invention, and FIG. 2 is a diagram illustrating a nitride III-V compound semiconductor according to the second invention. FIG. 3 is a diagram for explaining the principle of the method for manufacturing the device, and FIG. 3 is a diagram for explaining the principle of the method for manufacturing the nitride-based III-V compound semiconductor device of the third invention. 1 to 3, dislocations are schematically represented by vertical lines. 1 to 3, illustration of layers below the buffer layer is omitted. FIGS. 1 to 3 and FIGS. 4 to 8 and 10 shown below are schematic views. The film thickness of each layer shown in FIGS. 1 to 8 and 10 is the film thickness of each layer in an actual device. Different from thickness.
[0044]
As shown in FIG. 1A, a method for manufacturing a nitride-based III-V compound semiconductor device according to a first aspect of the present invention provides a method in which Ga is formed on a buffer layer 1 having dislocations formed above a substrate (not shown). After the layer 2 is deposited, a nitrogen source (hereinafter, referred to as an N source) is irradiated from above the Ga layer 2. At this time, the Ga layer 2 is reconstructed by the irradiation of the N source, and recrystallized as the GaN layer 3 shown in FIG. At this time, the GaN layer 3 does not crystallize randomly but recrystallizes in the same structure as the underlayer under the influence of the underlying buffer layer 1, but in the lower layer portion 4 of the GaN layer, Ga atoms undergo dislocation. Since the process ends, the dislocation information of the buffer layer 1 is not transmitted to the upper layer portion 5 of the GaN layer. Accordingly, the dislocation density of the nitride III-V compound semiconductor layer grown on the upper layer 5 of the GaN layer can be reduced, and the crystal structure of the nitride III-V compound semiconductor layer can be reduced. Is excellent in electrical characteristics such as mobility.
[0045]
As shown in FIG. 2A, the method for manufacturing a nitride-based III-V compound semiconductor device according to the second aspect of the present invention includes a method of manufacturing a semiconductor device on a buffer layer 21 having dislocations formed above a substrate (not shown). Then, a nitride-based III-V compound semiconductor layer 23 such as GaN is grown on the Ga layer 22. Next, heat treatment is performed to move Ga in the Ga layer 22 toward the nitride III-V compound semiconductor layer 23 above until excess Ga in the Ga layer 22 evaporates from the surface through the dislocations. As a result, Ga that has not evaporated in the Ga layer 22 remains near dislocations in the nitride III-V compound semiconductor layer 23. Then, dislocations in the nitride III-V compound semiconductor layer 23 such as GaN are annihilated by Ga remaining near dislocations in the nitride III-V compound semiconductor layer 23, as shown in FIG. As described above, the Ga layer 22 and the nitride III-V compound semiconductor layer 23 are made into a high-quality nitride III-V compound semiconductor layer 25 having few dislocations and excellent electric characteristics.
[0046]
As shown in FIG. 3A, the method for manufacturing a nitride III-V compound semiconductor device according to the third aspect of the present invention includes the step of forming a buffer layer 31 having dislocations formed above a substrate (not shown). Then, a nitride-based III-V compound semiconductor layer 32 such as GaN containing a smaller number of dislocations than the buffer layer 31 is formed, and then the buffer layer 31 and the nitride-based III-V compound are formed. Ions are implanted near the interface with the semiconductor layer 32 to form an amorphous layer 35 near the interface, as shown in FIG. Next, heat treatment is performed to recrystallize a part of the amorphous layer 35 and the nitride III-V compound semiconductor layer 32 on the amorphous layer 35, and as shown in FIG. The dislocation of the recrystallized layer 37 on the amorphous layer 35 remaining after that is reduced, and the crystallinity of the recrystallized layer 37 is made excellent in electrical characteristics and good.
[0047]
Hereinafter, the first invention will be described in detail in a first embodiment, the second invention will be described in a second embodiment, and the third invention will be described in a third embodiment.
[0048]
(1st Embodiment)
FIG. 4 shows a method for manufacturing a nitride III-V compound semiconductor device according to the first embodiment of the present invention. In FIG. 4 as well, as in FIGS. 1 to 3, dislocations are schematically shown by vertical lines.
[0049]
First, in the substrate oxide film removing step, the substrate temperature of the SiC substrate 41 is raised to about 1000 ° C. to remove the surface oxide film of the SiC substrate 41, and then a buffer layer forming step is performed. In this buffer layer forming step, the growth temperature was 800 ° C., and the Al beam intensity was 2.0 × 10 ^-7 As shown in FIG. 4A, a 20 nm-thick AlN film was formed on the SiC substrate 41 from which the surface oxide film had been removed by setting the Torr and the RF input power to 200 W and the nitrogen flow rate to 1.4 sccm, respectively. Is formed.
[0050]
Next, a Ga deposition step is performed. In this Ga deposition step, the intensity of the Ga beam was set to 6.0 × 10 ^-7 By setting the pressure to Torr and irradiating the AlN buffer layer 42 with a Ga beam for 10 seconds, a Ga layer 43 having a thickness of 1 nm is formed on the AlN buffer layer 42 as shown in FIG. 4B. . In FIG. 4, vertical lines drawn in the buffer layer 42, the Ga layer 43, and the like schematically represent dislocations (dangling bonds (line defects)) existing in the buffer layer 42, the Ga layer 43, and the like. It is. In FIG. 4B, the number of vertical lines drawn on the Ga layer 43 is smaller than the number of vertical lines drawn on the buffer layer 42, and the number of vertical lines drawn on the Ga layer 43 is smaller. , A vertical line drawn on the buffer layer 42. This schematically shows that the dislocation generated in the Ga layer 43 is smaller than the dislocation generated in the buffer layer 42 and is generated by being dragged by the dislocation of the buffer layer 42.
[0051]
Subsequently, the crystallization step is performed by setting the RF input power to 300 W, the nitrogen flow rate to 2.0 sccm, and the substrate temperature to about 750 ° C., respectively. In this crystallization step, the Ga layer 43 is crystallized by irradiating the Ga layer 43 with nitrogen from above the Ga layer 43 shown in FIG.
[0052]
As a result, before the crystallization step, the Ga layer indicated by reference numeral 43 in FIG. 4B is replaced with the lower layer portion 44 of the GaN layer after the crystallization step, as shown in FIG. , The upper layer 45 of the GaN layer. Since the crystallization was performed by irradiating the N source in the crystallization step, the number of dislocations in the lower portion 44 of the GaN layer was reduced (four in the Ga layer 43 in FIG. 4B). The number of dislocations is reduced to two in the lower layer portion 44 of the GaN layer shown in FIG. 4C, which is schematically illustrated). The crystal structure having a smaller number of dislocations than the number of dislocations in the portion 44 becomes an excellent layer (dislocations are set to 0 in the upper layer portion 45 of the GaN layer shown in FIG. 4C, which is schematically shown). After the crystallization step, the stoichiometric ratio of Ga element and nitrogen element (Ga element / nitrogen element) in the lower layer portion 44 of the GaN layer and the upper layer portion 45 of the GaN layer is set to a value of 1 or more and 1.5 or less. Has become.
[0053]
Finally, a compound semiconductor growth step is performed. In this compound semiconductor growth step, the substrate temperature was 750 ° C., and the Ga beam intensity was 6.0 × 10 ^-7 Torr, the RF input power was set to 450 W, the nitrogen flow rate was set to 2.2 sccm, and the upper layer portion 45 of the GaN layer was irradiated with a Ga beam and nitrogen, as shown in FIG. The GaN layer 46 having a thickness of 2 μm is formed on the upper layer part 45, and the manufacture of the main part of the nitride III-V compound semiconductor device of the first embodiment of the present invention is completed.
[0054]
A nitride-based III-V compound semiconductor device having a GaN layer is manufactured using the method for manufacturing a nitride-based III-V compound semiconductor device of the first embodiment. Using the molecular beam epitaxy method (RF-MBE method), a nitride-based III-V compound semiconductor device in which a GaN layer was directly grown on a buffer layer was prepared. An experiment was conducted to compare the electrical characteristics and dislocation density of the GaN layer of the -V compound semiconductor device.
[0055]
As a result of the experiment, when GaN was grown by a normal method, the dislocation density of GaN was 2 × 10 ¹⁰ cm ^-2 Value before and after and the carrier concentration is 1 × 10 ¹⁹ cm ^-3 The mobility is 98cm ² / Vs. Further, the carrier concentration is 1 × 10 ¹⁶ cm ^-3 The mobility is 30cm ² / Vs.
[0056]
On the other hand, when the GaN layer is grown by the method of the first embodiment, the dislocation density of the GaN layer is 3 × 10 ⁴ cm ^-2 The value is about 2 × 10 when GaN is grown by the usual method. ¹⁰ cm ^-2 The value was significantly smaller than the values before and after, and the crystal structure of the GaN layer was excellent in crystallinity. When a GaN layer is grown by the method of the first embodiment, the carrier concentration is 1 × 10 ¹⁹ cm ^-3 The mobility of the GaN layer is 100 cm ² / Vs, the GaN layer shows electrical characteristics equivalent to those of the GaN layer formed by the usual method, while the carrier concentration is 1 × 10 ¹⁶ cm ^-3 In the case of, the mobility is 1500 cm ² / Vs, which is a very large value, and the electrical characteristics of the GaN layer formed by the method of the first embodiment are far superior to those of the GaN layer formed by the normal method.
[0057]
According to the method for manufacturing a nitride III-V compound semiconductor device of the first embodiment, the AlN buffer layer 42 having dislocations formed on the SiC substrate 41 in the buffer layer forming step has a Ga After the layer 43 is deposited and the surface of the Ga layer 43 is irradiated with an N source in the crystallization step to crystallize the Ga layer 43, the buffer layer 42 is irradiated after the crystallization step of irradiating the N source. The crystal structure of the lower layer portion 44 of the GaN layer formed thereon has a high-quality crystal structure in which dislocations (dangling bonds (line defects)) have disappeared. Therefore, since the GaN crystal structure of the lower layer portion 44 of the GaN layer has a high quality with dangling bonds eliminated, the information of the dangling bonds of the buffer layer 42 reaches the upper layer portion 45 of the GaN layer. Thus, it is possible to prevent the dislocation information from reaching, and to transmit only information other than the dislocation information of the underlying buffer layer 42 to the upper layer portion 45 of the GaN layer. That is, the crystal structure of the upper layer portion 45 of the GaN layer can be made substantially the same as the crystal structure of the buffer layer 42 having no dislocation. Therefore, in the compound semiconductor growing step, the GaN layer 46 having a low dislocation density can be formed on the upper layer portion 45 of the high-quality GaN layer having a small number of dislocations. The electrical characteristics such as mobility of the nitride-based III-V compound semiconductor device formed by using the method for manufacturing a group V compound semiconductor device can be improved.
[0058]
Further, according to the method for manufacturing a nitride III-V compound semiconductor device of the first embodiment, the thickness of the Ga layer 43 deposited in the Ga deposition step is set to 1 nm. Dislocations in the GaN layer 46 can be sufficiently eliminated, and the crystallinity of the GaN layer 46 on the Ga layer 43 can be improved.
[0059]
In the first embodiment, the SiC substrate 41 is used, but a substrate other than the SiC substrate such as a sapphire substrate or a Si substrate may be used instead of the SiC substrate.
[0060]
In the first embodiment, the AlN buffer layer 42 is grown on the SiC substrate 41. However, the present invention is not limited to the AlN buffer layer. A buffer layer of a group V compound semiconductor may be grown.
[0061]
In the first embodiment, the GaN layer 46 is grown on the upper portion 45 of the crystallized GaN layer in the compound semiconductor growth step. However, in the compound semiconductor growth step, the GaN layer is not limited to the GaN layer. A nitride III-V compound semiconductor layer such as an AlN layer or an InN layer may be grown on the upper layer of the GaN layer.
[0062]
In the first embodiment, the Ga layer 43 having a thickness of 1 nm is formed on the AlN buffer layer 42 in the Ga deposition step. However, in the Ga deposition step, a buffer of a nitride III-V compound semiconductor is formed. A Ga layer having a thickness of 0.1 nm or more and 10 nm or less may be formed over the layer. Note that even when a Ga layer having a thickness of 0.1 nm or more and 10 nm or less is formed on a buffer layer of a nitride III-V compound semiconductor, the Ga layer 43 having a thickness of 1 nm is formed. As in the case of the formation, the dislocation of the nitride III-V compound semiconductor on the Ga layer can be sufficiently eliminated, and the crystallinity of the nitride III-V compound semiconductor on the Ga layer can be improved. It can be something.
[0063]
(2nd Embodiment)
FIGS. 5 and 6 show a method of manufacturing a nitride III-V compound semiconductor device according to a second embodiment of the present invention. In FIGS. 5 and 6, similarly to FIG. 4, dislocations are schematically shown by vertical lines.
[0064]
First, in the substrate oxide film removing step, the substrate temperature of the SiC substrate 51 is raised to 1000 ° C. to remove the surface oxide film of the SiC substrate 51, and then a buffer layer forming step is performed. In this buffer layer forming step, the growth temperature was 800 ° C., and the Al beam intensity was 2.0 × 10 ^-7 As shown in FIG. 5A, a 20 nm thick AlN film was formed on the SiC substrate 51 from which the surface oxide film had been removed, by setting the Torr and the RF input power to 200 W and the nitrogen flow rate to 1.4 sccm, respectively. Of the buffer layer 52 is formed.
[0065]
Next, a Ga deposition step is performed. In this Ga deposition step, the intensity of the Ga beam was set to 6.0 × 10 ^-7 By setting the pressure to Torr and irradiating the AlN buffer layer 52 with this Ga beam for 10 seconds, a Ga layer 53 having a thickness of 1 nm is formed on the AlN buffer layer 52 as shown in FIG. I do.
[0066]
Subsequently, a first compound semiconductor growth step is performed. In the first compound semiconductor growth step, the substrate temperature was set to 750 ° C., and the Ga beam intensity was set to 6.0 × 10 ^-7 By setting the Torr and the RF input power to 450 W and the nitrogen flow rate to 2.2 sccm, a GaN layer 54 having a thickness of 20 nm is formed on the Ga layer 53 as shown in FIG.
[0067]
Next, a heat treatment step is performed by raising the substrate temperature to 800 ° C. In this heat treatment step, the Ga deposited in the Ga deposition step is moved to the dislocation portion of the GaN layer 54 via the dislocation of the GaN layer 54 shown in FIG. Evaporate from the surface of 54. At this time, of the Ga deposited in the Ga deposition step, Ga not evaporated from the surface remains near the dislocation portion of the GaN layer 54 shown in FIG. The Ga remaining near the dislocation portion of the GaN layer 54 shown in FIG. 5C eliminates the dislocation of the GaN layer 54 shown in FIG. 5C, and the GaN layer 54 shown in FIG. , A high quality GaN layer 55 having few dislocations as shown in FIG. In the above-described heat treatment step, Ga deposited in the Ga deposition step is moved to the GaN layer 54, so that the Ga layer 53 disappears after the heat treatment step. After the heat treatment step, the stoichiometric ratio (Ga element / nitrogen element) of the Ga element and the nitrogen element of the high-quality GaN layer 55 having a small number of dislocations is 1 or more and 1.5 or less.
[0068]
Finally, a second compound semiconductor growth step is performed. In the second compound semiconductor growth step, the substrate temperature was set to 750 ° C., and the Ga beam intensity was set to 6.0 × 10 6 ^-7 As shown in FIG. 6B, the GaN layer 56 having a thickness of 2 μm was formed on the high-quality GaN layer 55 having a small number of dislocations by setting the Torr and the RF input power to 450 W and the nitrogen flow rate to 2.2 sccm. After the growth, the manufacture of the main part of the nitride III-V compound semiconductor device of the second embodiment is completed.
[0069]
Electrical characteristics and dislocation density of the GaN layer 56 of the main part of the nitride III-V compound semiconductor device manufactured by using the method of manufacturing the nitride III-V compound semiconductor device of the second embodiment; An experiment was performed to compare the electrical characteristics and dislocation density of a GaN layer directly grown on a buffer layer using a molecular beam epitaxy method (RF-MBE method) using ordinary plasma-excited nitrogen.
[0070]
As a result of the experiment, when the GaN layer 56 was grown by the method of the second embodiment, the dislocation density of the GaN 56 was 2 × 10 ⁴ cm ^-2 2 × 10, which is the value of the dislocation density when GaN is grown by a normal method. ¹⁰ cm ^-2 Significantly smaller than before and after.
[0071]
When the GaN layer 56 is grown by the method of the second embodiment, the carrier concentration of the GaN layer 56 is 1 × 10 ¹⁹ cm ^-3 The mobility of the GaN layer 56 is 95 cm ² / Vs, the electrical characteristics of the GaN layer 56 are substantially the same as the electrical characteristics of the GaN layer formed by the usual method, while the carrier concentration of the GaN layer 56 is 1 × 10 ¹⁶ cm ^-3 The mobility of the GaN layer 56 is 1450 cm ² / Vs, which is a very large value, and the electrical characteristics of the GaN layer 56 are far superior to those of the GaN layer formed by the usual method.
[0072]
According to the second embodiment, since the heat treatment is performed in the heat treatment step, a part of Ga of the Ga deposition layer can be evaporated from the surface through the dislocation part of the GaN layer 54 shown in FIG. 5C. At the same time, the remaining Ga in the Ga layer is moved to the vicinity of the dislocation of the GaN layer 54 shown in FIG. 5C, so that the dislocation of the GaN layer 54 shown in FIG. 5C can be eliminated. In other words, the GaN layer 54 having many dislocations shown in FIG. 5C can be reconstructed into the high-quality GaN layer 55 having few dislocations shown in FIG. 6A. The crystallinity of the GaN layer 56 formed on the high-quality GaN layer 55 can be made high-quality with few dislocations. Therefore, the electrical characteristics such as the mobility of the nitride III-V compound semiconductor device can be improved.
[0073]
Further, according to the second embodiment, the thickness of the Ga layer 53 deposited in the Ga deposition step is set to 1 nm, so that the dislocation of the GaN layer 56 above the Ga layer 53 can be sufficiently eliminated. In addition, the crystal quality of the GaN layer 56 above the Ga layer 53 can be improved.
[0074]
According to the second embodiment, in the heat treatment step, the temperature is higher than 750 ° C., which is the substrate temperature in the first compound semiconductor growth step, and 200 ° C., which is 750 ° C., which is the substrate temperature in the first compound semiconductor growth step. Since the heat treatment is performed at 800 ° C., which is lower than 950 ° C., which is the temperature at which the GaN layer 54 is added, Ga can be sufficiently diffused without evaporating the GaN layer 54, and the GaN layer 54 can be Can do enough. Therefore, dislocations in the GaN layer 54 that have undergone the heat treatment can be sufficiently reduced, and the dislocation density in the GaN layer 54 can be significantly reduced.
[0075]
Although the SiC substrate 51 is used in the second embodiment, a substrate other than the SiC substrate such as a sapphire substrate or a Si substrate may be used instead of the SiC substrate 51.
[0076]
In the second embodiment, the AlN buffer layer 52 is grown on the SiC substrate 51. However, the present invention is not limited to the AlN buffer layer, and a nitride-based buffer layer such as a GaN buffer layer or an InN buffer layer may be formed on the substrate. A buffer layer of a III-V compound semiconductor may be grown.
[0077]
In the above-described second embodiment, the GaN layer 56 is grown after the heat treatment step. However, the present invention is not limited to the GaN layer. Layers may be grown.
[0078]
In the second embodiment, the Ga layer 53 having a thickness of 1 nm is formed on the AlN buffer layer 52 in the Ga deposition step. However, in the Ga deposition step, a buffer of a nitride III-V compound semiconductor is formed. A Ga layer having a thickness of 0.1 nm or more and 10 nm or less may be formed over the layer. Then, even when a Ga layer having a thickness of 0.1 nm or more and 10 nm or less is formed on the buffer layer of a nitride III-V compound semiconductor, the Ga layer 53 having a thickness of 1 nm is formed. As in the case of the formation, the dislocation of the nitride III-V compound semiconductor on the Ga layer can be sufficiently eliminated, and the crystallinity of the nitride III-V compound semiconductor on the Ga layer can be improved. It can be something.
[0079]
In the second embodiment, the heat treatment process is performed by increasing the substrate temperature to 800 ° C., but is higher than 750 ° C., which is the substrate temperature in the first compound semiconductor growth process, and the first compound semiconductor growth process is performed. Even if the heat treatment process is performed by setting the substrate temperature to a temperature smaller than 950 ° C. obtained by adding 200 ° C. to 750 ° C. which is the same as the case where the heat treatment process is performed by increasing the substrate temperature to 800 ° C. It has been confirmed that it has an effect. If the heat treatment step is performed with the substrate temperature set to 950 ° C. or higher, the GaN layer 54 evaporates, and the quality of the nitride III-V compound semiconductor device deteriorates. If the heat treatment step is performed while setting the substrate temperature to the following temperature, Ga cannot be sufficiently diffused.
[0080]
(Third embodiment)
7 and 8 show a method for manufacturing a nitride III-V compound semiconductor device according to a third embodiment of the present invention. In FIGS. 7 and 8, dislocations are schematically shown by vertical lines as in FIGS. 4, 5 and 6. FIG.
[0081]
First, in the substrate oxide film removing step, the substrate temperature of the SiC substrate 71 is raised to 1000 ° C. to remove the surface oxide film of the SiC substrate 71, and then a buffer layer forming step is performed. In this buffer layer forming step, the growth temperature was 800 ° C., and the Al beam intensity was 2.0 × 10 ^-7 With the Torr and RF input power set to 200 W and the nitrogen flow rate set to 1.4 sccm, respectively, an AlN buffer layer 72 having a thickness of 20 nm is formed on the SiC substrate 71 as shown in FIG.
[0082]
Next, a compound semiconductor growth step is performed. In this compound semiconductor growth step, the substrate temperature was 750 ° C., and the Ga beam intensity was 6.0 × 10 ^-7 By setting the Torr and the RF input power to 450 W and the nitrogen flow rate to 2.2 sccm, a GaN layer 73 having a thickness of 20 nm is grown on the AlN buffer layer 72 as shown in FIG. 7B.
[0083]
Subsequently, an ion implantation step is performed. In this ion implantation step, Ga is used as ion implantation atoms, the acceleration voltage of the Ga ions is 20 keV, and the implantation amount of the Ga ions is 1 × 10 ¹⁸ cm ^-3 In the vicinity of the interface between the AlN buffer layer 72 and the GaN layer 73, Ga ions are implanted near the interface between the AlN buffer layer 72 and the GaN layer 73, as shown in FIG. The layer 74 is formed, and the AlN buffer layer 72 and the GaN layer 73 are separated by the amorphous layer 74.
[0084]
Next, a heat treatment step is performed. In this heat treatment step, the GaN layer 73 on the amorphous layer 74 shown in FIG. 7 (C) is recrystallized by raising the substrate temperature to 800 ° C. and performing heat treatment as shown in FIG. 8 (A). Next, a GaN layer 75 having few dislocations is formed. After performing this heat treatment step, the thickness of the amorphous layer 74 formed by implanting Ga ions becomes small as shown in FIG. In the remaining amorphous layer 74 shown in FIG. 8A, the stoichiometric ratio of Ga element and nitrogen (Ga element / nitrogen) is 1 or more and 1.5 or less.
[0085]
Finally, a second compound growth step is performed. In this second compound growth step, the substrate temperature was set to 750 ° C., and the Ga beam intensity was set to 6.0 × 10 ^-7 By setting the Torr and the RF input power to 450 W and the nitrogen flow rate to 2.2 sccm, a GaN layer 76 having a thickness of 2 μm is grown on the GaN layer 75 having few dislocations as shown in FIG. 8B. . Thus, the manufacture of the main part of the nitride III-V compound semiconductor device of the third embodiment is completed.
[0086]
Electrical characteristics and dislocation density of the GaN layer 76 of the main part of the nitride III-V compound semiconductor device manufactured by using the method of manufacturing the nitride III-V compound semiconductor device of the third embodiment; An experiment was performed to compare the electrical characteristics and dislocation density of a GaN layer directly grown on a buffer layer using a molecular beam epitaxy method (RF-MBE method) using ordinary plasma-excited nitrogen.
[0087]
As a result of the above experiment, when GaN was grown by the method for manufacturing a nitride III-V compound semiconductor device of the third embodiment, the dislocation density of GaN was 4 × 10 ⁴ cm ^-2 The value is about 2 × 10 when GaN is grown by the usual method. ¹⁰ cm ^-2 Significantly smaller than before and after.
[0088]
When the GaN layer 76 is grown by the method of the third embodiment, the carrier concentration of the GaN layer 76 is 1 × 10 ¹⁹ cm ^-3 The mobility of the GaN layer 76 is 10 ³ cm ² / Vs, the electrical characteristics of the GaN layer 76 show almost the same electrical characteristics as those of the GaN layer formed by the usual method, while the carrier concentration of the GaN layer 76 is 1 × 10 ¹⁶ cm ^-3 The mobility of the GaN layer 76 is 1480 cm ² / Vs, which is a very large value, and the electrical characteristics of the GaN layer 76 are far superior to those of the GaN layer formed by the usual method.
[0089]
According to the third embodiment, the buffer layer 72 made of AlN formed on the SiC substrate 71 in the buffer layer forming step and the GaN layer 73 grown on the AlN buffer layer 72 in the compound semiconductor growing step In the ion implantation step, Ga ions are implanted in the vicinity of the interface between the AlN buffer layer 72 and the GaN layer 73, so that an amorphous layer 74 can be formed near the interface between the AlN buffer layer 72 and the GaN layer 73. By separating, the dislocation information of the AlN buffer layer 72 can be prevented from being transmitted to the GaN layer 73. In a heat treatment performed next, the GaN layer 73 on the amorphous layer 74 is recrystallized by performing heat treatment, and the GaN layer 73 having a large number of dislocations shown in FIG. The GaN layer 75 having few dislocations shown in FIG. Therefore, the GaN layer 76 having good crystallinity can be formed on the GaN layer 75 having a small number of dislocations, and the nitride-based GaN layer 76 formed using the main part of the nitride-based III-V compound semiconductor device of the third embodiment can be formed. The electrical characteristics of the group III-V compound semiconductor device can be improved.
[0090]
According to the third embodiment, Ga ions are implanted near the interface between the AlN buffer layer 72 and the GaN layer 73 in the ion implantation step, so that the Ga ion is implanted near the interface between the AlN buffer layer and the GaN layer. As in the case where Si ions are implanted, a high-concentration n-type layer is not formed near the interface. Therefore, for example, even when a field-effect transistor is manufactured using the method for manufacturing a nitride III-V compound semiconductor device of the third embodiment, a high-density impurity exists at the interface between the AlN buffer layer 72 and the GaN layer 73. No n-type layer is formed, and the n-type layer does not cause parallel conduction with the channel layer, which is a path through which current flows. From this, it is possible to realize a large current of the nitride III-V compound semiconductor device manufactured by using the method of manufacturing the nitride III-V compound semiconductor device of the third embodiment.
[0091]
According to the third embodiment, in the heat treatment step, 200 ° C. is set to be higher than 750 ° C., which is the substrate temperature in the first compound semiconductor growth step, and to 750 ° C., which is the substrate temperature in the first compound semiconductor growth step. Since the heat treatment is performed at 800 ° C. lower than the added 950 ° C., the GaN layer 73 on the amorphous layer 74 can be sufficiently recrystallized without re-evaporation of the GaN layer 73, and The dislocation density of the GaN layer 75 formed by crystallization can be reduced. Therefore, the crystallinity of the GaN layer 76 formed on the GaN layer 75 can be further improved.
[0092]
Although the SiC substrate 71 is used in the third embodiment, a substrate other than the SiC substrate such as a sapphire substrate or a Si substrate may be used instead of the SiC substrate 71.
[0093]
In the third embodiment, the AlN buffer layer 72 is grown on the SiC substrate 71. However, the present invention is not limited to the AlN buffer layer, and a nitride-based buffer layer such as a GaN buffer layer or an InN buffer layer may be formed on the substrate. A buffer layer of a III-V compound semiconductor may be grown.
[0094]
Further, in the third embodiment, the GaN layer 73 is grown on the AlN buffer layer 72 in the compound semiconductor growth step. However, the present invention is not limited to the GaN layer. A nitride III-V compound semiconductor layer such as an AlN layer or an InN layer may be grown on the buffer layer of the -V compound semiconductor.
[0095]
In the third embodiment, in the ion implantation step, Ga ions are implanted near the interface between the AlN buffer layer 72 and the GaN layer 73 to form the amorphous layer 74, but instead of Ga ions, Even if one of C ions, N ions, Mg ions, Al ions, Zn ions, and In ions is implanted, the same effect as when Ga ions are implanted can be obtained. In addition, even if any two or more of C ions, N ions, Mg ions, Al ions, Zn ions, Ga ions, and In ions are implanted, the same effect as when Ga ions are implanted can be obtained.
[0096]
Further, in the third embodiment, the heat treatment step is performed by raising the substrate temperature to 800 ° C., but the substrate temperature used in the heat treatment step is not limited to 800 ° C. The substrate temperature is higher than 750 ° C., which is the growth temperature of AlN, and lower than 950 ° C., which is the temperature obtained by adding 200 ° C. to 750 ° C., which is the growth temperature of AlN. It may be. It has been confirmed that when the heat treatment step is performed at a substrate temperature in this range, the same operation and effect as when the heat treatment step is performed with the substrate temperature raised to 800 ° C. are exhibited. If the heat treatment step is performed with the substrate temperature set to 950 ° C. or higher, the GaN layer 73 evaporates, and the quality of the nitride-based III-V compound semiconductor device deteriorates. If the heat treatment step is performed with the substrate temperature set to the following temperature, the GaN layer 73 cannot be sufficiently recrystallized.
[0097]
Table 1 shows a method for manufacturing a normal nitride-based III-V compound semiconductor device and a method for manufacturing a nitride-based III-V compound semiconductor device according to the first, second, and third embodiments. The dislocation density of the uppermost GaN layer and the carrier concentration of 1 × 10 3 in the main part of the three nitride-based III-V compound semiconductor devices ¹⁹ cm ^-3 And the carrier concentration of the GaN layer is 1 × 10 ¹⁶ cm ^-3 5 shows the mobility of the GaN layer at the time.
[0098]
[Table 1]

[0099]
As shown in Table 1, 1 × 10 ¹⁹ cm ^-3 High carrier concentration, the mobility of the GaN layer is approximately 100 cm regardless of the method of forming the nitride-based III-V compound semiconductor device. ² / Vs, and there is no difference in the electrical characteristics of the GaN layer between the four methods. On the other hand, 1 × 10 ¹⁶ cm ^-3 In the case of the low carrier concentration, the mobility of the GaN layer manufactured by the usual method and the GaN layer manufactured by the other three methods (that is, the methods of the first, second, and third embodiments of the present invention). There is a significant difference between the mobility of the layers.
[0100]
FIG. 9 shows a method of manufacturing a normal nitride-based III-V compound semiconductor device and a method of manufacturing a nitride-based III-V compound semiconductor device according to the first, second, and third embodiments. The relationship between the carrier concentration and the mobility of the GaN layer of the nitride-based III-V compound semiconductor device is shown.
[0101]
The circles shown in FIG. 9 are measurement points when a normal method of manufacturing a nitride-based III-V compound semiconductor device is used, and the results in Table 1 are plotted. On the other hand, square marks shown in FIG. 9 are measurement points when the method of manufacturing the nitride-based III-V compound semiconductor device of the first, second, and third embodiments is used, and the results in Table 1 are plotted. (The scale of FIG. 9 does not show the difference between the first, second, and third embodiments, and the three embodiments point to the same points on the drawing).
[0102]
As shown in FIG. 9, the carrier concentration is 1 × 10 ^17.3 cm ^-3 In the above regions, the mobility for the same carrier concentration is equal in the four methods, and it can be seen that the mobility increases as the carrier concentration decreases.
[0103]
On the other hand, the carrier concentration decreased to 1 × 10 ^17.3 cm ^-3 , It can be seen that the mobility of the normal method and the mobility of the methods of the three embodiments of the present invention diverge, as shown in FIG. Specifically, the carrier concentration is 1 × 10 ^Fifteen cm ^-3 1 x 10 ^17.3 cm ^-3 In the region below, the mobility decreases as the carrier concentration decreases in the usual method, whereas the mobility increases in the three methods of the present invention as the carrier concentration decreases. . That is, it can be seen that there is a great difference in the behavior of the mobility between the normal method and the three methods of the present invention.
[0104]
This is because, as shown in the following equation (1), the mobility μ of the GaN layer becomes 1.5 times the carrier concentration n and the dislocation density N. _disl. Is determined by
[0105]
(Equation 1)

[0106]
Specifically, when the carrier concentration is high, the value of the carrier concentration n to the 1.5th power is large. Therefore, the mobility μ of GaN is mainly 1.5% of the carrier concentration n according to the above equation (1). It is determined by a factor of the power. This means that if the carrier concentration increases, collisions between carriers frequently occur, and the mobility μ is determined by carrier-carrier scattering. That is, the carrier concentration is 1 × 10 ¹⁹ cm ^-3 , The mobility μ is substantially determined only by the value of n to the 1.5th power, and the dislocation density N _disl Less susceptible to This is because the carrier concentration is 1 × 10 ¹⁹ cm ^-3 And the mobility μ is 100 cm in any method. ² / Vs.
[0107]
On the other hand, when the carrier concentration is 1 × 10 ¹⁶ cm ^-3 , The value of the numerator in equation (1) becomes small, and the mobility μ becomes smaller than the dislocation density N. _disl Will be greatly affected. This is because the carrier concentration is 1 × 10 ¹⁶ cm ^-3 In the normal growth method with many dislocations, the mobility is 30 cm. ² / Vs while the method of the present invention having few dislocations has a mobility of 1500 cm. ² The reason is that the value becomes as large as about / Vs. In other words, unlike the normal growth method, the GaN layer formed by the method of the present invention has a carrier concentration of 10%. ¹² cm ^-3 The dislocations do not enter the region where the dislocations are dominant until they are below the level. That is, by using the method of the present invention, a GaN layer having few dislocations can be formed, and thus a large mobility μ can be obtained even in a region where the carrier concentration is low.
[0108]
FIG. 10 shows a structure of a HEMT (high electron mobility transistor) as an example of a nitride III-V compound semiconductor device.
[0109]
In FIG. 10, 101 is the (0001) plane of the sapphire substrate, 102 is a 20-nm-thick GaN buffer layer grown at a low temperature, and 103 is a GaN layer (background carrier concentration of 10 nm). ¹⁶ cm ^-3 Hereinafter, the film thickness is 3 μm), 104 is Al _0.25 Ga _0.75 An N layer (thickness: 30 nm), 105 is a Hf (hafnium) source / drain electrode, and 106 is a Pd (palladium) gate electrode.
[0110]
Next, a HEMT (High Electron Mobility Transistor) having the layer structure shown in FIG. 10 is formed by the usual method using the MOCVD method and the first, second and third embodiments using the MOCVD method. Heterostructure characteristics and HEMT characteristics of the four HEMTs were compared.
[0111]
Hereinafter, only the main points of the four HEMT manufacturing methods will be briefly described.
[0112]
First, in a normal case, first, the substrate temperature of the sapphire substrate is set to 1100 ° C. in a hydrogen atmosphere, and cleaning for removing an oxide film of the sapphire substrate is performed for 10 minutes. , Ga raw material flow rate (trimethylgallium TMG) flow rate is 10 sccm, HN ₃ Is set to 5 slm, and the GaN buffer layer is grown.
[0113]
Next, the GaN layer was grown by setting the substrate temperature to 1000 ° C. and the flow rate of the Ga raw material (trimethylgallium TMG) to 40 sccm, and then setting the substrate temperature to 1000 ° C., the trimethylaluminum (TMA) flow rate to 5 sccm, and Flow rate 25 sccm, NH ₃ The flow rate of each of them to 6 slm _0.25 Ga _0.75 Grow the N layer.
[0114]
Finally, Al _0.25 Ga _0.75 A HEMT is manufactured by forming an Hf (hafnium) source / drain electrode and a Pd (palladium) gate electrode on the N layer.
[0115]
Next, in the method of the first embodiment of the present invention, after growing the GaN buffer layer, only TMG is allowed to flow to deposit Ga, and NH is used as a nitrogen source while increasing the temperature. ₃ To crystallize Ga.
[0116]
In the method according to the second embodiment of the present invention, after depositing Ga by flowing only TEG after the growth of the buffer layer, the growth temperature is subsequently set to 500 ° C. to form a GaN layer of about 20 nm. Thereafter, the substrate temperature is increased to grow GaN, and after the growth is interrupted, the substrate temperature is increased to 1050 ° C. and heat treatment is performed for 1 minute, and subsequently, a hetero structure is grown at 1000 ° C.
[0117]
Finally, in the method according to the third embodiment of the present invention, after growing the GaN layer after growing the low-temperature buffer layer, ion implantation is performed. Thereafter, a heat treatment is performed at 1050 ° C. for 1 minute, and a heterostructure is formed at 1000 ° C. following the heat treatment.
[0118]
In the above four methods, a HEMT having a gate length Lg of 0.1 μm and a gate width Wg of 200 μm was manufactured.
[0119]
Table 2 shows the characteristic comparison results of the conventional method and the four HEMTs manufactured by the methods of the first, second and third embodiments.
[0120]
[Table 2]

[0121]
In Table 2, the DC / RF dispersion ratio is the rate of change between the characteristics when a direct current is applied and the characteristics when a high frequency is applied. If this value is small, the HEMT characteristics will be excellent for high frequency applications.
[0122]
As shown in Table 2, although the dislocation density differs between the ordinary method and the method of the present invention (methods of the first, second and third embodiments) by about two orders of magnitude, it shows the electrical characteristics of the heterostructure. Mobility, HEMT characteristics, transconductance g _m And the maximum transmission frequency f _max No big difference is seen. However, since the dislocation density acting as a trap becomes small, the DC / RF dispersion rate of the method of the present invention (the method of the first, second and third embodiments) is 30% lower than that of the ordinary method. From 10% to 10% or less, and the HEMT characteristics are greatly improved.
[0123]
In forming the above HEMT, each layer was grown by MOCVD. However, it was confirmed that the same improvement as in MOCVD was also observed in a crystal growth method using a molecular beam ectopic device other than the RF-MBE method. (In the growth method using the RF-MBE method, it has been confirmed that the mobility is extremely small due to the large number of dislocations and sufficient HEMT characteristics cannot be obtained.)
[0124]
【The invention's effect】
As is clear from the above, according to the method for manufacturing a nitride-based III-V compound semiconductor device of the first, second, and third inventions, the upper part of the buffer layer made of the nitride-based III-V compound semiconductor is formed. Can reduce dislocations in the nitride-based III-V compound semiconductor layer and improve the electrical characteristics such as mobility of the nitride-based III-V compound semiconductor layer above the buffer layer. it can. Therefore, the electrical characteristics such as mobility and high frequency characteristics of a nitride III-V compound semiconductor device such as an HFET having a nitride III-V compound semiconductor layer having a small dislocation and excellent electrical characteristics are improved. It can be excellent.
[0125]
Further, in the nitride-based III-V compound semiconductor device of the fourth invention, Ga is diffused using the Ga layer deposited in the step of depositing Ga, and the nitride layer formed above the Ga layer is diffused. Since the nitride-based III-V compound semiconductor device has reduced dislocations in the compound-based III-V compound semiconductor layer, the crystallinity and electrical characteristics are excellent.
[0126]
In the nitride-based III-V compound semiconductor device according to the fifth aspect of the present invention, for example, after a step of performing amorphization such as an ion implantation step, a layer above the amorphous layer is regenerated by a heat treatment step or the like. Since the device is a crystallized device, the dislocation density of the recrystallized layer of the nitride-based III-V compound semiconductor device of the fifth invention is small, and the electrical characteristics are excellent.
[Brief description of the drawings]
FIG. 1 is a schematic diagram for explaining the principle of the manufacturing process of the method for manufacturing a nitride III-V compound semiconductor device according to the first invention.
FIG. 2 is a schematic diagram illustrating the principle of the manufacturing process of the method for manufacturing a nitride-based III-V compound semiconductor device according to the second invention.
FIG. 3 is a schematic diagram illustrating the principle of the manufacturing process of the method for manufacturing a nitride III-V compound semiconductor device according to the third invention.
FIG. 4 is a view showing a manufacturing process of a method for manufacturing a nitride-based III-V compound semiconductor device according to the first embodiment of the present invention.
FIG. 5 is a view illustrating a part of a manufacturing process of a method for manufacturing a nitride-based III-V compound semiconductor device according to a second embodiment of the present invention.
FIG. 6 is a view illustrating a part of the manufacturing process of the method for manufacturing the nitride-based III-V compound semiconductor device continued from FIG. 5;
FIG. 7 is a view showing a part of a manufacturing process of a method for manufacturing a nitride III-V compound semiconductor device according to a third embodiment of the present invention.
8 is a view showing a part of the manufacturing process of the method for manufacturing a nitride-based III-V compound semiconductor device following FIG. 7;
FIG. 9 is a diagram showing a relationship between carrier concentration and mobility of a nitride III-V compound semiconductor device.
FIG. 10 is a diagram illustrating a structure of a HEMT (high electron mobility transistor) as an example of a nitride III-V compound semiconductor device.
[Explanation of symbols]
1,21,31 Buffer layer
2,22,43,53 Ga layer
3,46,54,55,56,73,75,76,103 GaN layer
Lower layer of 4,44 GaN layer
Upper layer of 5,55 GaN layer
23,25,32 Nitride III-V compound semiconductor layers
35,74 Amorphous layer
41, 51, 71 SiC substrate
42, 52, 72 AlN buffer layer
101 Sapphire substrate
102 GaN buffer layer
104 AlGaN layer
105 source / drain electrodes
106 Gate electrode

Claims (9)

A buffer layer forming step of forming a buffer layer made of a nitride III-V compound semiconductor on a substrate;
A Ga deposition step of depositing a Ga layer on the buffer layer;
A crystallization step of irradiating the surface of the Ga layer deposited in the Ga deposition step with a nitrogen source to crystallize it as a GaN layer;
A method for growing a nitride-based III-V compound semiconductor layer on the crystallized GaN layer. A method for manufacturing a nitride-based III-V compound semiconductor device, comprising: A buffer layer forming step of forming a buffer layer made of a nitride III-V compound semiconductor on a substrate;
A Ga deposition step of depositing a Ga layer on the buffer layer;
A first compound semiconductor growing step of growing a first nitride III-V compound semiconductor layer on the Ga layer;
A heat treatment step of performing a heat treatment after the first compound semiconductor growth step;
A second compound semiconductor growing step of growing a second nitride III-V compound semiconductor layer after the heat treatment step. A method for manufacturing a nitride III-V compound semiconductor device, comprising: The method for manufacturing a nitride-based III-V compound semiconductor device according to claim 1 or 2,
The method for manufacturing a nitride-based III-V compound semiconductor device, wherein a Ga layer having a thickness of 0.1 nm or more and 10 nm or less is deposited in the Ga deposition step. A buffer layer forming step of forming a buffer layer made of a nitride III-V compound semiconductor on a substrate;
A compound semiconductor growing step of growing a nitride III-V compound semiconductor layer on the buffer layer;
Ion implantation step of implanting ions near the interface between the buffer layer and the nitride-based compound semiconductor layer to make the vicinity of the interface amorphous;
And a heat treatment step of performing a heat treatment after the ion implantation step. A method of manufacturing a nitride-based III-V compound semiconductor device, comprising: The method for manufacturing a nitride-based III-V compound semiconductor device according to claim 4,
A method for manufacturing a nitride-based III-V compound semiconductor device, wherein ions implanted in the ion implantation step are at least one of C, N, Mg, Al, Zn, Ga, and In. The method for manufacturing a nitride III-V compound semiconductor device according to claim 2 or 4,
The temperature of the heat treatment step is higher than the growth temperature of the nitride-based III-V compound semiconductor layer formed before the heat treatment step, and lower than the temperature obtained by adding 200 ° C. to the growth temperature. A method for manufacturing a nitride-based III-V compound semiconductor device. A nitride-based III-V compound semiconductor device in which a nitride-based III-V compound semiconductor layer is formed above a substrate,
A part of the nitride-based III-V compound semiconductor layer has a stoichiometric ratio of a group III element to nitrogen (group III element / nitrogen) of 1 or more and 1.5 or less. Group III-V compound semiconductor device. A nitride-based III-V compound semiconductor device in which a nitride-based III-V compound semiconductor layer is formed above a substrate,
A nitride-based III-V compound semiconductor device, wherein a part of the nitride-based III-V compound semiconductor layer is amorphous. 9. The nitride-based III-V compound semiconductor device according to claim 8, wherein at least one of C, Mg, and Zn exists in the amorphous portion, or a stoichiometric ratio of a group III element to nitrogen. A portion having (Group III element / nitrogen) of 1 or more and 1.5 or less is present in the amorphous portion, or a stoichiometric ratio of nitrogen to Group III element (Nitrogen / Group III element) is 1 or more and A nitride III-V compound semiconductor device, wherein 1.5 or less portions exist in the amorphous portion.

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