JPH02183348A - Function instruction debug processor - Google Patents

Abstract

PURPOSE:To easily confirm whether continuity to one function instruction is obtained or not in mutually different arithmetic processing by repeatedly executing the function instruction until the address of a microinstruction, which is desired to be checked, is coincident with an execution micro-address. CONSTITUTION:Data are set from an input control part 1 to an arithmetic data part 2 and the address of the microinstruction, which is desired to be checked, is set to a check address register part 7. The address of the microinstruction executed by an arithmetic processing part 4 is successively set to a register part 6 and it is checked whether the register part 6 is coincident with the register part 7 or not by a checking circuit 8. Then, a returning address register part 5 is referred until the register parts 6 and 7 are coincident. Then, the instruction is repeated. Thus, the input data can be easily discovered to confirm whether the two types of the arithmetic processing obtains the continuity or not to one function instruction by reading the input data when the instruction is finished in an output control part 10.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to detecting input data for a process that is particularly desired to be executed by a function instruction in an information processing device incorporating a plurality of function instructions. Regarding.

[Prior art] When the result of a certain function instruction becomes sufficiently small or, conversely, becomes sufficiently large, a function command is executed according to the result of the intermediate operation, rather than performing normal arithmetic processing. Performing separate arithmetic processing often results in fewer errors and faster calculation speed.

In this way, when creating another arithmetic process, it is necessary to check whether the final arithmetic results of the normal arithmetic process and the special arithmetic process are continuous.

In the conventional technology, this confirmation involves a verifier inputting a plurality of appropriate consecutive input data, checking whether those input data have undergone different arithmetic processing, and if only one arithmetic processing has been performed. In that case, it was necessary to input several consecutive pieces of manual data and check again.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, the checker considers a plurality of consecutive input data each time and checks whether or not different arithmetic processing has been performed on them. Therefore, it is time consuming and has the disadvantage that the checker has to rely on a certain level of intuition when considering the input data.

SUMMARY OF THE INVENTION In view of the above drawbacks, the technical problem of the present invention is to provide a function instruction debug processing device that can easily check whether or not mutually different arithmetic operations have continuity with respect to one function instruction. That's true.

[Means for Solving the Problems] According to the present invention, in an information processing device incorporating a plurality of function instructions, addresses of microinstructions to be checked among certain function instructions are stored as a first table. a check circuit for determining whether or not the execution microaddress matches the contents of the table 1, and a second means for providing a flag that is set when the check circuit detects a match; The function instruction ends,
A third means for incrementing or decrementing the operation data of the function instruction when the flag set by the second means is not set, and a third means for incrementing or decrementing the operation data of the function instruction when the flag provided by the second means is not set, and a third means for incrementing or decrementing the operation data of the function instruction, and a third means for incrementing or decrementing the operation data of the function instruction when the flag is not set. and a fourth means for storing return address information as a second table, inputting initial data with a certain function instruction,
If the data does not set the flag provided by the second means, increment or decrement the manual data and refer to the address information in the second table until it matches the first table information. As a result, a function instruction debug processing device is obtained, which is characterized in that the function instruction is repeatedly executed.

Embodiment C] Next, an embodiment of the present invention will be described with reference to the drawings.

First, assume that a certain function instruction has the flow shown in FIG. In the figure, X is a certain constant, and path S is a path where the calculation result of calculation process A is greater than or equal to X, and the instruction is completed by performing calculation process B based on the calculation result. T indicates a path where the calculation result of the calculation process A is less than X, and the instruction is completed by performing the calculation process C based on the calculation result.

FIG. 1 shows an embodiment of the invention.

Human control unit 1. The data is set in the arithmetic data section 2, the address of the microinstruction to be checked is set in the check address register section 7, and the return address of the microinstruction to be branched is set in the return address register section 5, respectively. In addition, for the initial human power data, prepare data such that the route S is taken, and then consider whether the human power data needs to be increased or decreased in order to take the route T. I'll keep it.

When it is necessary to increase the value, the input control section 1 sets the increment/decrement control section 3 to increment it, and in the opposite case, it sets it to decrement it.

The function instruction is activated, the arithmetic processing section 4 executes the arithmetic operation, and the address of the executed microinstruction is sequentially set in the micro-instruction address register section 6, and a check circuit 8 checks whether or not it matches the check address register section 7. If they match, flag 9 is set.

The instruction is repeated with reference to the return address register section 5 until flag 9 is set, and when flag 9 is set, the instruction ends.

Here, whether or not the path S and the path T maintain continuity is determined by the output control unit 10, which reads the input data at the time the instruction is completed, and calculates the instruction result when the vicinity of the input data is set as the input data. You can easily confirm this by comparing.

[Effects of the Invention] As explained above, the present invention provides a system in which when a certain function instruction has a flow in which there is a special arithmetic process in addition to the normal arithmetic process, the two processes are considered as one function instruction. Sometimes, it has the effect of making it easy to find input data to check whether continuity is satisfied.

5... Return address register part, 6... Micro instruction address register part, 7... Check address register part, 8... Check circuit, 9... Flag,
]n...Output control section.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a flowchart of function instructions used in the embodiment of the present invention. 1... Input control section, 2... Calculation data section, 3...
Increment/decrement control unit, 4...Arithmetic processing Figure 1

Claims (1)

[Claims] 1. A first information processing device used in an information processing device incorporating a plurality of function instructions, which stores addresses of microinstructions to be checked among the function instructions as a first table. means; a check circuit for determining whether or not the execution microaddress matches the contents of the first table; a second means for providing a flag that is set when the check circuit detects a match; and the function. a third means for incrementing or decrementing the operation data of the function instruction when the flag set by the second means is not set after the instruction is completed; When the return address information of a branching microinstruction is input as initial data using a second certain function instruction, if the flag set by the second means is not set, the input data is incremented or decremented. The function instruction debug processing device is characterized in that the function instruction is repeatedly executed by referring to the address information in the second table until the address information matches the first table information.