JPH02181550A - Communication control equipment and atm exchange provided with the same - Google Patents

Abstract

PURPOSE:To efficiently utilize a memory and to rapidly execute information processing by storing a header formed by the 1st processing means and an information field protocol-processed by the 2nd processing means in a common storage means. CONSTITUTION:When frame information is transferred from a transfer control processing part 10 to a transmission frame memory 23 in an inter-processor common memory 20, a microprocessor(muP) 13 writes the leading address of the information and the number of bytes in a PR2 interruption control part 24. The control part 24 executes the interruption processing of the muP 31 in a protocol processing part 30. The muP 31 inputs the contents of the information field of the frame information in a memory part 33 and executes the protocol processing of the contents of the information field. After ending the protocol processing of the muP 31, a memory access control part 32 writes the contents of the information field in a transmission frame memory 22 and writes the leading address of the written contents and the number of transfer bytes in a register of a PR1 interruption control part 21.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is applicable to communication control devices (for example, ATMs).
The present invention relates to a communication control device that is advantageously applied to a (chronous transfer mode) exchange, etc., and performs protocol processing thereon.

(Prior Art) A communication control device receives a cell including a header such as an address/control field and an information field from a switch section of an ATM switch, assembles it into frame information,
For example, after performing layer 2 or layer 3 protocol processing, the processed frame information is decomposed into cells and transmitted to the switch unit. This communication control device has a transfer control processing unit that analyzes addresses and control fields, and a protocol control processing unit that performs protocol processing of information fields. In the communication control device in the prior art, these two processing units perform protocol processing on the received information by directly transmitting data to each other.

When the transfer control processing section receives a frame in which cells are assembled, it makes a bus request to the protocol processing section and makes it wait. Thereafter, the transfer control processing section transfers the contents of the information field to the protocol processing section and activates it. After the protocol processing unit is activated, the transfer control processing unit analyzes the address field and the control field, and the protocol processing unit performs protocol processing on the contents of the information field. After the protocol processing is completed, the protocol processing unit performs transfer. A bus request is made to the control processing unit and it is placed on standby. Then, the protocol processing section transfers the contents of the information field subjected to the protocol processing to the transfer control section and activates it. The transfer control processing section adds the contents of the address/control field to the received information field to form return frame information. This return frame is divided into cells and then sent to the switch section.

(Problems to be Solved by the Invention) However, in such a conventional communication control device, data is exchanged directly between the transfer control processing section and the protocol processing section. For this reason, during data transmission, the processor of the processing unit on the side to which the data is transferred must be temporarily stopped, causing a problem in that processing time is delayed. Also.

Since the transfer control processing section transfers information fields to the protocol processing section, a storage section is required to store information fields that are not processed by the transfer control processing section, in addition to the address and control fields. Furthermore, since the contents of the information field are read and written in the storage section of the transfer control processing section, there is a problem in that it takes extra time and causes a processing delay.

SUMMARY OF THE INVENTION It is an object of the present invention to overcome the drawbacks of the prior art and to provide a communication control device and an ATM switch equipped with the communication control device that can efficiently utilize memory and process information at high speed.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention receives cells,
After assembling this cell into frame information including an information field and header information and performing protocol processing on the information field, a communication control device that disassembles the protocol-processed information field into cells and transmits them analyzes the header information, a first processing means that performs frame information transfer control processing by forming a transmission header after analysis; a second processing means that performs protocol processing of the information field;
and common storage means that can be accessed by the first processing means and the second processing means.

Further, according to the present invention, an AT &
The I exchange includes a first processing means that performs frame information transfer control processing by analyzing header information and forming a transmission header after analysis; a second processing means that performs protocol processing of information fields; and a common storage means accessible by the second processing means.

(Function) According to the present invention, when a cell is received, the cell is assembled into frame information and stored in the common storage means. The first processing means reads a header portion of the frame information stored in the common storage means, analyzes it, and then forms a transmission header of the frame information to be transmitted. Further, the second processing means reads out the information field of the frame information stored in the common storage means and performs protocol processing on the information field.

The header formed by the first processing means and the information field protocol processed by the second processing means are:
Transmission frame information is formed by being recorded in the common storage means. The transmitted frame information stored here is decomposed into cells and output.

(Example) Next, an example of a communication control device according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, a functional diagram of an embodiment of a communication control device according to the present invention is shown.

The communication control device l in this embodiment is incorporated in an ATM switch, and the switch section (not shown) of this switch
When a cell is received, the control device assembles the frame information into frame information including an information field and header information, performs protocol processing such as layer 2 or 3, and then transmits it to the switch unit.

Communication control device l has switch section interface +5 IU
) 60. Cell receiving unit (BPAD140, cell transmitting unit (
FPAD) 50, transfer control processing unit fPR1) to, protocol processing unit (PH 1030, and inter-processor common memory (PCMI 20).
This is an interface section that is connected to, for example, a switch section of an M exchange and matches the interface with the outside. The interface section 60 sends cells received from the switch section to the cell reception section 40 via the output 122, and also sends cells received from the cell transmission section 50 via the human power 124 to the switch section via the output 120.

The cell receiving unit 40 is a frame assembly unit that assembles received cells into a frame. After performing an FCS check on the assembled frame, the receiving section 40 outputs it to the bus 200 as frame information.

The cell transmitter 50 is a cell disassembler that adds Fe2 to the frame information sent via the bus 200 and then disassembles this information into cells. The cell transmitter 50 sends this cell to the switch interface 60 via the output 124.

The transfer control processing unit 1O is connected to the cell receiving unit 4 via the bus 200.
0, cell transmitter 50 and inter-processor common memory 20
It is connected to the. The transfer control processing unit IO includes a memory unit (
MM)11. Direct memory access control unit (DMA)
I 1213 and a microprocessor (μp) 13. The transfer control processing unit IO is a processor that performs transfer control processing of frame information. That is, the transfer control processing unit 10 analyzes header contents such as the address and control field of the frame information, and forms a transmission header of the frame information to be transmitted based on the analysis result.

The inter-processor common memory 20 is connected to the transfer control processing section 10 and also to the protocol processing section 30 via a bus 210. The inter-processor common memory 20 is a data intermediary section provided so that the transfer control processing section 10 and the protocol processing section 30 can perform their own information processing without directly exchanging data. The common memory 20 includes a bus contention unit (BA) 2
5. PR1 interrupt control unit (INTI) 21. Transmission frame memory fsFMl 22, reception frame memory (RF
Ml 23 and PR2 interrupt controller [INT2) 24
has.

The protocol processing unit 30 includes an inter-processor common memo 1J2.
0 to receive the contents of the information field of the frame information,
This is an information processing unit that performs protocol processing of this information field. The protocol processing unit 30 includes a microprocessor (μp) 31. Direct memory access control unit (D
MA) 32 and a memory section (MM) 33.

The memory unit 11 of the transfer control processing unit 1O is a storage unit that is connected to the bus 200 and stores the address of the frame information received from the bus 200, the contents of the control field, and the like.

The direct memory access control unit 12 is connected to the bus 200 and transfers the frame information assembled by the cell reception unit 40 to the reception frame memory 2 of the inter-processor common memory 20.
This is a control unit that transfers the data to 2.

The microprocessor 13 is a processor that performs frame information transfer and control processing, and is connected to the bus 200 and also connects to the signal line! It is connected to the PRI interrupt control unit 21 via 00. When the processor 13 stores the frame information in the reception frame memory 23, the processor 13 writes its start address and the number of bytes to the PR1 interrupt control unit 24. The processor 13 also writes the address and control field of the frame information stored in the memory unit ll. Performs analysis processing and forms a header associated with transfer control. The processor 13 further completes the frame information to be transmitted by writing the contents of the formed header address and control field into the transmission frame memory 22 in which the protocol-processed information field is stored.

The bus contention section 25 of the inter-processor common memory 20 is connected to the transfer control processing section 10 via the bus 200 and to the protocol processing section 30 via the bus 210, respectively. The bus contention unit 25 also includes a PR1 interrupt control unit 21, a transmission frame memory 22, a reception frame memory 23, and a PR2
This is a connection section that is connected to the interrupt control section 24 and connects these to the bus 200 or 21G.

The PR1 interrupt control unit 21 is a control unit that interrupts the microprocessor 13 of the transfer control unit IO at a predetermined timing. The PR1 interrupt control unit 21 also has a register in which the start address of the information field stored in the transmission frame memory 22 and the number of transferred bytes are stored.

The transmission frame memory 22 is a storage unit that stores information fields subjected to protocol processing, address fields subjected to analysis processing, and control fields. Note that in this embodiment, the transmission frame memory 22 is managed by the protocol processing section 30.

The reception frame memory 23 is a storage unit that stores frame information assembled by the cell reception unit.

Note that in this embodiment, the reception frame memory 23 is managed by the transfer control processing unit IO.

The PR2 interrupt controller 24 is connected via an output 110 to the microprocessor 31 of the protocol processor.

The 0 interrupt control unit 24, which is a control unit that performs interrupt processing on the processor 31 at a predetermined timing, also has a register in which the start address and number of bytes of the information field stored in the reception frame memory 23 are stored.

The microprocessor 31 of the protocol processing unit 30 is a processing unit that performs protocol processing of the contents of the information field, for example, information processing regarding layer 2 or 3. The direct memory access control unit 32 is a transfer control unit that transfers the protocol-processed information field to the transmission frame memory 22. The memory unit 33 is a storage unit that stores the contents of information fields to be subjected to protocol processing. These microprocessors 31. Direct memory access control section 32 and memory section 33 are each connected to bus 210.

When the switch section interface section 60 receives a cell from the switch section of the ATM exchange, the interface section 60 sends this cell via the output 122 to the cell receiving section 4°. When the cell reception section 40 receives a cell, it assembles it as frame information and then performs an FCS check. When the frame information is FCS checked, the direct memory access control section 12 transfers this frame information to the bus 20.
0 and the bus contention unit 25, the receive frame memory 2
Transfer to 3.

When the frame information is transferred to the reception frame memory 23, the microprocessor 13 of the transfer control processing unit 10 transfers the frame information to the reception frame memory 23 that stores the transferred frame information.
The start address and number of bytes are written to the PR2 interrupt control unit 24. When these pieces of information are stored, the interrupt control unit 24 performs interrupt processing on the microprocessor 31 of the protocol processing unit 30.

When the microprocessor 31 receives an interrupt process, the microprocessor 31 outputs P
The frame information storage area is known from the register of the R2 interrupt control unit 24, and the contents of the information field of the frame information are read into the memory unit 33. And the processor 31 is
Performs protocol processing on the contents of the information field. On the other hand, the microprocessor 13 of the transfer control processing unit IO is
During this time, the content of the address/control field of the frame information is analyzed, and after this analysis processing, other processing related to frame information transfer control is performed.

When the microprocessor 31 completes the protocol processing, the memory access control unit 32 writes the contents of the information field of the frame information into the transmission frame memory 22. The processor 31 also writes the start address of the transmission frame memory 22 that stores the contents of this information field and the number of transferred bytes into the register of the PR1 interrupt control unit 21. , performs interrupt processing on the microprocessor 13.

When the microprocessor 13 receives an interrupt process from the control unit 21, the microprocessor 13 inputs the contents of the address field and control field of the frame information to be sent back to the switch unit of the exchange.
When frame information is formed by writing into a transmission frame memory in which information fields already subjected to protocol processing are stored, processor 13 sends this frame information to cell transmitter 50 . When the cell transmitter 50 receives the frame information, it adds Fe2 to it, decomposes it into cells, and sends it to the switch interface 60 via the output 124. Interface 60 sends the received cells via output 120 to the switch section of the ATM switch.

FIG. 2 shows a functional block diagram of a communication control device in the prior art. In the conventional communication control device 2, since the inter-processor common memory 20 is not provided as in the present embodiment, the transfer control processing section 10A and the protocol processing section 30A directly transmit data via the bus confounding section 90. must be carried out. That is, for example, when exchanging the contents of an information field, the microprocessor of the processing unit on the receiving side must be temporarily stopped, resulting in a delay in processing time. Furthermore, the transfer control processing section 10A needs to temporarily store the contents of the information field of the frame information assembled by the cell receiving section 40 in its memory IIA, and thus requires an extra memory area. Furthermore, in the communication control device 2, extra time is required to read and write information fields in the memory 11A.

In contrast, in this embodiment, the inter-processor common memory 2
0 is provided and information is transmitted via this, it is possible to execute information processing without stopping the microprocessor. Also.

Since the reception frame memory 23 and the transmission frame memory 22 are arranged in the common memory 22, there is no need for a memory to store the contents of the information field in the memory unit U of the transfer control processing unit IO, and the contents of the information field can be read and written at high speed. can.

It should be noted that although the communication control device l in this embodiment is assumed to be incorporated into an ATM switch to which this embodiment is advantageously applied,
Of course, the communication control device l in the present invention is not limited in this way, and although the communication control device l in this embodiment is intended to perform layer 2 or layer 3 protocol processing, it is of course possible to perform layer 2 or layer 3 protocol processing. The level is not limited to this.

(Effects of the Invention) As described above, according to the present invention, by providing the common storage means, the first processing means and the second processing means can exchange data via this storage means. Therefore, the first processing means and the second processing means can perform parallel processing without stopping during data transmission, and it is possible to improve processing performance. Furthermore, since the transmission and reception of frame information is stored in the common storage means, there is no need for the first processing means and the second processing means to directly transfer this information to each other. Therefore, the time required for this transfer can be reduced and the processing speed of one communication control device can be improved. Furthermore, since the frame information is stored in the common storage means, the first processing means does not need a memory for storing the information field of the received cell, and the memory can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing an embodiment of a communication control device according to the present invention, and FIG. 2 is a functional block diagram showing an example of a conventional communication control device. 13.31 20. 21.24 22. 23. 25. 40. 50. 60.

Claims (1)

[Claims] 1. Receive a cell, assemble the cell into frame information including an information field and header information, perform protocol processing on the information field, and then decompose the protocol-processed information field into cells. a communication control device that transmits the frame information, the control device comprising: a first processing unit that performs transfer control processing of the frame information by analyzing the header information and forming a transmission header after the analysis; A communication control device comprising: second processing means for performing protocol processing; and common storage means that can be accessed by the first processing means and the second processing means. 2. The communication control device according to claim 1, wherein the common storage means includes a first storage section that stores frame information for performing the protocol processing, and a header formed by the first processing means and a second storage section. and a second storage section that stores the information field subjected to the protocol processing by the processing means as frame information, the first processing means manages the first storage section, and the second processing means manages the second storage section. A communication control device characterized by managing a storage section. 3. An ATM switch receives cells, assembles the cells into frame information including an information field and header information, performs protocol processing on the information fields, and then disassembles the protocol-processed information fields into cells. The exchange includes: a first processing unit that performs transfer control processing of the frame information by analyzing the header information and forming a transmission header after the analysis; and a second processing unit that performs protocol processing of the information field. An ATM switch comprising: a communication control device having a common storage means accessible by the first processing means and the second processing means.