JPH02180053A - Lead substrate for semiconductor package - Google Patents
Lead substrate for semiconductor packageInfo
- Publication number
- JPH02180053A JPH02180053A JP33500288A JP33500288A JPH02180053A JP H02180053 A JPH02180053 A JP H02180053A JP 33500288 A JP33500288 A JP 33500288A JP 33500288 A JP33500288 A JP 33500288A JP H02180053 A JPH02180053 A JP H02180053A
- Authority
- JP
- Japan
- Prior art keywords
- lid substrate
- sealing
- substrate
- lid
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000007789 sealing Methods 0.000 claims abstract description 28
- 239000000919 ceramic Substances 0.000 claims description 12
- 230000005499 meniscus Effects 0.000 abstract description 7
- 230000002950 deficient Effects 0.000 abstract description 2
- 238000007689 inspection Methods 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 description 11
- 238000007639 printing Methods 0.000 description 9
- 238000001465 metallisation Methods 0.000 description 7
- 230000007547 defect Effects 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 239000006071 cream Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 238000005219 brazing Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010344 co-firing Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
イ９発明の目的
本発明は、半導体パッケージの構造に係り、詳しくは、
コファイアドセラミックリッド（蓋）や厚膜印刷するセ
ラミックリッド基板の形状およびそのメタライズに関す
る。DETAILED DESCRIPTION OF THE INVENTION A9.Object of the Invention The present invention relates to the structure of a semiconductor package, and in detail,
This article relates to the shape and metallization of cofired ceramic lids and ceramic lid substrates for thick film printing.
従来の技術
ＩＣ，ＬＳＩ等の半導体用パッケージの形態の一つとし
て、第６図に示すセラミックパッケージが用いられてい
る。このセラミックパッケージは、半導体チップ６を搭
載するため中央に凹部を有するセラミックベース基板５
（以下ベース基板という）と、このベース基板５の蓋と
なるセラミックリッド（蓋）基板１（以下リッド基板と
いう）から構成され、両基板の接合面は、コファイア（
同時焼成）されたメタライズが施されており、両メタラ
イズ間をリッド基板に形成されたソルダー材でロー付け
して接着封止するようになっている。2. Description of the Related Art A ceramic package shown in FIG. 6 is used as one type of package for semiconductors such as ICs and LSIs. This ceramic package includes a ceramic base substrate 5 having a recessed portion in the center for mounting a semiconductor chip 6.
(hereinafter referred to as a base substrate) and a ceramic lid substrate 1 (hereinafter referred to as a lid substrate) that serves as a lid for this base substrate 5. The bonding surface of both substrates is a cofired
A solder material formed on the lid substrate is solder-bonded between the two metallizations to bond and seal them.
第７図は、方形のリッド基板の平面図であり、封着面を
斜線で示した。FIG. 7 is a plan view of a rectangular lid substrate, and the sealing surface is shown with diagonal lines.
リッド基板１の封着面の構造の例を第７図のＡＡの断面
図として第８図て示ず。グリーンテープにＷメタライズ
を印刷し、同時焼成した後、メタライズ層を酸化防止の
ため覆うＮｉメツキ等でＮｉ層を形成して１００９℃で
焼結する。さらにソルダー（半田〉４として、例えばＰ
ｂ−８ｕ、Ｐｂ／Ｉｎ／Ａｇ、またはＰｂ／Ｉｎ／Ａｇ
等を印刷し、リフロー（ＲＥＦＩ、０１１１）してリッ
ド基板にツルターを一体化させる。さらにフラ′・クス
等や・有機物の除去のため十面を洗浄して・ベース基板
らとの封止の準備を整える。An example of the structure of the sealing surface of the lid substrate 1 is shown in FIG. 8 as a cross-sectional view taken along line AA in FIG. 7. After printing W metallization on the green tape and co-firing, a Ni layer is formed by Ni plating or the like to cover the metallization layer to prevent oxidation, and sintering is performed at 1009°C. Furthermore, as a solder (solder) 4, for example, P
b-8u, Pb/In/Ag, or Pb/In/Ag
etc., and perform reflow (REFI, 0111) to integrate the turret with the lid board. Furthermore, ten surfaces are cleaned to remove flux, wax, etc. and organic matter, and preparations are made for sealing with the base substrate.
一方、リッド基板の封止部の相手側のベース基板５の被
封止部を第６図Ｂ部の断面図の第８図で説明する。ベー
ス基板５の上面にＷメタライズ印刷し同時焼成した後、
その上にＮｉメツキを施し、その上にハンダ濡れ性を改
善するために必要に応じて金メツキ（図示せず）されて
いる。On the other hand, the sealed portion of the base substrate 5 on the other side of the sealed portion of the lid substrate will be explained with reference to FIG. 8, which is a cross-sectional view of part B in FIG. 6. After printing W metallization on the top surface of the base substrate 5 and simultaneously firing,
Ni plating is applied thereon, and gold plating (not shown) is applied thereon as necessary to improve solder wettability.
リッド基板１の封着面にパターン形成のさい、・ル・ド
基板下面の端の外□側対着面′ア詩近は完全に印刷で覆
うことは、印刷タレ防止や印刷ズレのため困難であり、
若干外側の封着面を残すように控えて印刷して形成する
ことになる。即ち、ベース基板５とリッド基板１を封着
するさい、セラミックベースとの封止面のズレやソルダ
ー量の少ない場答、封止性能にバラツキが生じ、第１０
図（ａ）のよう、にメニスカス８の不良、ロー材中のボ
イドの発生、リッド基板５とベース基板１のスレ等によ
り、封止不良が発生し気密性を害し、信頼性に乏しい欠
点があった。一方、ツルター量が多過きる場合、第１０
図の（ｂ）に示すようにメニスカスの外側に余剰のツル
ターが凸状に堆積し、メニスカスの外観検蕎を困難にし
、才なメタライズとソルダー間に同図のＯのようにボイ
ドが発生し、気密性の信頼性を欠くことになる恐れがあ
った。When forming a pattern on the sealing surface of the lid substrate 1, it is difficult to completely cover the area near the outer □ side of the lower edge of the lid substrate with printing to prevent printing from sagging and to prevent printing from shifting. and
It will be formed by printing so as to leave a little outer sealing surface. That is, when sealing the base substrate 5 and the lid substrate 1, misalignment of the sealing surface with the ceramic base, a small amount of solder, and variations in sealing performance occur.
As shown in Figure (a), a defect in the meniscus 8, the occurrence of voids in the brazing material, scratches between the lid substrate 5 and the base substrate 1, etc., may cause sealing failures, impairing airtightness, and resulting in poor reliability. there were. On the other hand, if the amount of sulter is too large, the 10th
As shown in (b) of the figure, excess sinter is deposited in a convex shape on the outside of the meniscus, making it difficult to inspect the appearance of the meniscus, and voids are generated between the thin metallization and the solder, as shown in O in the figure. , there was a risk that the reliability of airtightness would be lost.
が 決しようとする課
本発明は、以上のベース基板とリッド基板の封゛着部の
メニスカスの不良、封着部不良を防ぎ、気密性がありか
つその外観検査を確実にできる高信頼性の半導体セラミ
ック基板用リッド基板を提供することを目的としている
。The present invention aims to prevent meniscus defects and sealing defects in the sealed portion between the base substrate and the lid substrate, and to provide a highly reliable semiconductor that is airtight and can be reliably inspected for appearance. The purpose is to provide a lid substrate for a ceramic substrate.
ロ６発明の構成
課題を解決するための手段
本第１発明は、ベース基板の上面に封着するりラド基板
下面のメタライズ封着面において、該リッド基板側面と
該リッド基板下面が交差する部分に切欠面を有し、該リ
ッド基板下面および該切欠面をメタライズし封着部を形
成することを特徴とする半導体パッケージ用リッド基板
である。B6 Structure of the Invention Means for Solving the Problems The first invention provides for a portion where the lid substrate side surface and the lid substrate bottom surface intersect in the metallized sealing surface of the bottom surface of the lid substrate that is sealed to the top surface of the base substrate. The lid substrate for a semiconductor package is characterized in that the lower surface of the lid substrate and the notch surface are metallized to form a sealing part.
本第２発明は、ベース基板の上面に封着するりラド基板
下部のメタライズ封着面において、該リッド基板下面お
よび、該リッド基板側面と該リッド基板下面が直交差す
る該側面下部付近をメタライズし封着部を形成すること
を特徴とする半導体パッケージ用リッド基板である。In the second invention, in the metallized sealing surface of the lower part of the RAD substrate that is sealed to the upper surface of the base substrate, the lower surface of the lid substrate and the vicinity of the lower part of the side surface where the side surface of the lid substrate and the lower surface of the lid substrate intersect perpendicularly are metalized. This is a lid substrate for a semiconductor package, characterized in that a sealing portion is formed.
色ｌ萩↓因夫１乱
本第１発明の切欠部の構成と寸法関係を第１図（ａ）お
よび（’ｂ ）にで説明する。′同図（ａ）はリッド基
板１の側面下部切欠部７′をテーパ状にし、切欠部の高
さ１１とリッド基板厚みＨ（）ｌ＝０．５１〜０．８０
ｍｍ）との関係は、ｈ ＝’０．１ Ｈ〜０．’５ Ｈ
５また同図（ｂ）は同部分を階段状のノツチ付にし、切
欠部の底辺長さρと封着部底辺長さＬ （Ｌ ＝′０．
５〜１．０ｍｍ＞の関係は、４−１／２ Ｌ 〜１’
／３Ｌである。The configuration and dimensional relationship of the cutout portion of the first invention will be explained with reference to FIGS. 1(a) and ('b). ' In the same figure (a), the side lower notch 7' of the lid board 1 is tapered, and the height 11 of the notch and the lid board thickness H()l = 0.51 to 0.80.
mm) is h = '0.1 H~0. '5 H
5 In addition, in FIG. 5(b), the same part is provided with a stepped notch, and the bottom length ρ of the notch and the bottom length L of the sealing part (L = '0.
5 to 1.0 mm> is 4-1/2 L to 1'
/3L.
本第２発明の構成および寸法関係を第２図で説明する。The configuration and dimensional relationship of the second invention will be explained with reference to FIG.
すなわち、切欠部は有しないがリッド基板の下面および
側面下部付近にもメタライズ、Ｎｉ、ソルダーが施され
ている。側面下部の封着高さｌ］とリッド基板厚みＨの
関係は
ｈ＝ｏ。ＩＨ〜１．ＯＨである。That is, although there is no notch, metallization, Ni, and solder are also applied to the lower surface and the vicinity of the lower side of the lid substrate. The relationship between the sealing height l at the bottom of the side surface and the lid substrate thickness H is h=o. IH~1. It's OH.
本第１発明および本第２発明の実施したとき封着部の構
成を第３図および第４図に示すが、何れも極めて優れた
メニスカス８を示していることがわかる。即ち、従来法
の第８図と比較すると封着不良の発生の防止、外観検査
を確実になし得る等の利点が明白である。The structure of the sealed portion when the first invention and the second invention are implemented is shown in FIGS. 3 and 4, and it can be seen that the meniscus 8 is extremely excellent in both cases. That is, when compared with the conventional method shown in FIG. 8, advantages such as prevention of sealing defects and reliable appearance inspection are obvious.
次に、本発明の切欠部の形成方法及びリッド基板の製造
方法について説明する。Next, a method for forming a notch and a method for manufacturing a lid substrate according to the present invention will be explained.
コファイアド品は、グリーンテープにＷペースト印刷後
、第５図（ａ）および（ｂ）に示すようにスナップ刃１
０、または、プレス刃１１で押圧しブレークして切欠部
を形成する。また、必要に応じてテープノツチをつけて
焼成し、Ｎｉメツキし１ｏｏｏ℃で焼結後ブレークして
基板を製造することもできる。After printing the W paste on the green tape, the coffarded product has a snap blade 1 as shown in Fig. 5 (a) and (b).
0, or by pressing and breaking with the press blade 11 to form a notch. Alternatively, a substrate can be manufactured by adding a tape notch as necessary, baking it, plating it with Ni, sintering it at 100° C., and then breaking it.
ブレークした基板にクリーム半田印刷、リフ口、その後
、洗浄してリッド基板とする。The broken board is printed with cream solder, refinished, and then cleaned to become a lid board.
厚膜品の場合は、プレス成形によって第１図（ａ）およ
び（ｂ）の形状のテーパーまたは、ノツチのついた生基
板を成形し、その後、従来法に従って焼成して基板を製
造する。その基板の上にＣｕ、Ａｇ／Ｐ＋７． Ａｇ／
Ｐｔメタライズ層を印刷し焼成する。In the case of a thick film product, a green substrate with a taper or notch in the shape shown in FIGS. 1(a) and 1(b) is formed by press molding, and then fired according to a conventional method to manufacture the substrate. Cu, Ag/P+7. Ag/
Print and bake a Pt metallized layer.
次にクリーム半田印刷、リフロー１洗浄によってリッド
基板とする。Next, a lid board is formed by cream solder printing and reflow 1 cleaning.
ハ０発明の効果
本発明は、リッド基板の封着面の形状またはメタライズ
面を改善することにより、半導体パッケージのメタライ
ズ封着の気密性とその信頼性の向上に大きく寄与するも
のである。Effects of the Invention The present invention greatly contributes to improving the airtightness and reliability of metallized sealing of semiconductor packages by improving the shape of the sealing surface or the metallized surface of the lid substrate.
第１図（ａ）および（ｂ）本第１発明の切欠部の構成を
説明する断面図である。
第２図は、本第２発明の詳細な説明する断面図である。
第３図は本第１発明の詳細な説明する断面図である。
第４図は本第２発明の詳細な説明する断面図である。
第５図は本発明の切欠部の形成方法例を説明する断面図
である。
第６図は従来の半導体パッケージの概念図の一例である
。
第７図はリッド基板の平面図である。
第８図は第７図のＡ−Ａ面の断面図である。
第９図は第６図Ｂ部の断面図である。
第１０図（ａ）および（ｂ）は従来の封着部の不良状態
を説明する断面図である。
１、セラミックリッド基板、２． Ｉｌｌメタライズ層
＋Ｎｉ層、４．ソルダー（半田）、５．セラミックベー
ス基板、６半導体チップ、７．切欠部、８．メニスカス
９、リッド基板の側面下部、１０．スナップ刃、１１゜
プレス刃、１２．テープノツチ。FIGS. 1(a) and 1(b) are sectional views illustrating the structure of a cutout portion of the first invention. FIG. 2 is a sectional view illustrating details of the second invention. FIG. 3 is a sectional view illustrating the first invention in detail. FIG. 4 is a sectional view illustrating the second invention in detail. FIG. 5 is a sectional view illustrating an example of the method of forming a notch according to the present invention. FIG. 6 is an example of a conceptual diagram of a conventional semiconductor package. FIG. 7 is a plan view of the lid substrate. FIG. 8 is a sectional view taken along the line AA in FIG. 7. FIG. 9 is a sectional view of section B in FIG. 6. FIGS. 10(a) and 10(b) are cross-sectional views illustrating a defective state of a conventional sealing portion. 1. Ceramic lid substrate, 2. Ill metallized layer + Ni layer, 4. Solder (solder), 5. Ceramic base substrate, 6 semiconductor chips, 7. Notch portion, 8. Meniscus 9, lower side of lid board, 10. Snap blade, 11° press blade, 12. Tape knot.
Claims (2)
板下面のメタライズ封着面において、該リッド基板側面
と該リッド基板下面が交差する部分に切欠面を有し、該
リッド基板下面および該切欠面をメタライズし封着部を
形成することを特徴とする半導体パッケージ用リッド基
板。(1) The metallized sealing surface of the lower surface of the lid substrate that is sealed to the upper surface of the ceramic base substrate has a cutout surface at the intersection of the side surface of the lid substrate and the lower surface of the lid substrate, and the lower surface of the lid substrate and the cutout surface A lid substrate for a semiconductor package, characterized in that a sealing part is formed by metallizing.
板下部のメタライズ封着面において、該リッド基板下面
および、該リッド基板側面と該リッド基板下面が直交差
する該側面下部付近をメタライズし封着部を形成するこ
とを特徴とする半導体パッケージ用リッド基板。(2) On the metallized sealing surface of the lower part of the lid substrate that is sealed to the upper surface of the ceramic base substrate, the lower surface of the lid substrate and the vicinity of the lower part of the side surface where the side surface of the lid substrate and the lower surface of the lid substrate intersect perpendicularly are metalized and sealed. 1. A lid substrate for a semiconductor package, characterized in that the lid substrate forms a portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33500288A JPH02180053A (en) | 1988-12-30 | 1988-12-30 | Lead substrate for semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33500288A JPH02180053A (en) | 1988-12-30 | 1988-12-30 | Lead substrate for semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02180053A true JPH02180053A (en) | 1990-07-12 |
Family
ID=18283638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33500288A Pending JPH02180053A (en) | 1988-12-30 | 1988-12-30 | Lead substrate for semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02180053A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0313743U (en) * | 1989-06-26 | 1991-02-12 | ||
| WO2007037365A1 (en) * | 2005-09-29 | 2007-04-05 | Nippon Telegraph And Telephone Corporation | Optical module |
| JP2008047701A (en) * | 2006-08-16 | 2008-02-28 | Nippon Telegr & Teleph Corp <Ntt> | Optical module |
| JP2015018872A (en) * | 2013-07-09 | 2015-01-29 | 日機装株式会社 | Window member, semiconductor module and window member manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5498178A (en) * | 1978-01-20 | 1979-08-02 | Hitachi Ltd | Electronic device |
| JPS60115247A (en) * | 1983-11-28 | 1985-06-21 | Fujitsu Ltd | Semiconductor device |
-
1988
- 1988-12-30 JP JP33500288A patent/JPH02180053A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5498178A (en) * | 1978-01-20 | 1979-08-02 | Hitachi Ltd | Electronic device |
| JPS60115247A (en) * | 1983-11-28 | 1985-06-21 | Fujitsu Ltd | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0313743U (en) * | 1989-06-26 | 1991-02-12 | ||
| WO2007037365A1 (en) * | 2005-09-29 | 2007-04-05 | Nippon Telegraph And Telephone Corporation | Optical module |
| JP2008047701A (en) * | 2006-08-16 | 2008-02-28 | Nippon Telegr & Teleph Corp <Ntt> | Optical module |
| JP2015018872A (en) * | 2013-07-09 | 2015-01-29 | 日機装株式会社 | Window member, semiconductor module and window member manufacturing method |
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