JPH0217937B2 - - Google Patents
Info
- Publication number
- JPH0217937B2 JPH0217937B2 JP56019462A JP1946281A JPH0217937B2 JP H0217937 B2 JPH0217937 B2 JP H0217937B2 JP 56019462 A JP56019462 A JP 56019462A JP 1946281 A JP1946281 A JP 1946281A JP H0217937 B2 JPH0217937 B2 JP H0217937B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- substrate
- semiconductor
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 51
- 238000002955 isolation Methods 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 239000005360 phosphosilicate glass Substances 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 17
- 238000000926 separation method Methods 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 16
- 238000000034 method Methods 0.000 description 14
- 230000003647 oxidation Effects 0.000 description 12
- 238000007254 oxidation reaction Methods 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 6
- 241000293849 Cordylanthus Species 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- DLYUQMMRRRQYAE-UHFFFAOYSA-N tetraphosphorus decaoxide Chemical compound O1P(O2)(=O)OP3(=O)OP1(=O)OP2(=O)O3 DLYUQMMRRRQYAE-UHFFFAOYSA-N 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
Description
【発明の詳細な説明】
本発明は半導体集積回路装置の製造方法に係
り、特に素子分離構造の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of forming an element isolation structure.
従来から一般に用いられている半導体集積回路
装置に於ける誘電体分離構造は、例えば第１図に
示すように、第１誘電型を有する半導体基板１上
に第２導電型半導体層２が積層形成されてなる半
導体集積回路基板の表面に、第２導電型半導体層
２を貫いて第１導電型半導体基板１内に達する例
えばＶ溝状の分離溝３を設け、該分離溝３の表面
のみに選択的に5000〔Å〕程度の厚さを有する熱
酸化膜４ａを形成し、該熱酸化膜４ａを有する分
離溝内を多結晶シリコン層５で充たし、該多結晶
シリコン層５の表出面に、例えば8000〔Å〕程度
の厚さの熱酸化膜４ｂを形成してなつていた。
（図中２′は第２導電型埋没層）
そして上記従来の誘電体分離構造に於いて、分
離溝３内面の熱酸化膜４ａ及び分離溝内に充され
た多結晶シリコン層５表面の熱酸化膜４ｂは、第
２導電型半導体層２の活性領域６上に半導体酸化
膜４ｃを介して窒化シリコン（Si3N4）膜７を設
け、該Si3N4膜７を耐酸化マスクとして選択熱酸
化により形成され、従つて熱酸化膜４ａ及び４ｂ
は前記Si3N4膜７の縁部の下層にも成長するの
で、図に示すようなバーズ・ビーク（bird′s
beak）８や突起９を生ずることは公知である。
そのため従来構造に於ては、次のような問題があ
つた。即ち上記バーズ・ビーク８は１〜1.5〔μ
ｍ〕程度に達するため、分離領域の幅を拡大しめ
て集積度を低下せしめ、且つ分離領域にセルフ・
アラインされる拡散窓や電極窓の寸法が不正確に
なり機能素子の特性が変動するという問題、前記
突起部に形成される鋭角状の段差部１０に於て配
線の断線が生ずるという問題、更に鋭角状の段差
部１０に残留しがちな配線材料により配線間の短
絡を生ずる問題等である。 A dielectric isolation structure in a semiconductor integrated circuit device that has been commonly used in the past includes, for example, as shown in FIG. 1, a semiconductor layer 2 of a second conductivity type is laminated on a semiconductor substrate 1 having a first dielectric type. For example, a V-groove-shaped separation groove 3 penetrating through the second conductivity type semiconductor layer 2 and reaching into the first conductivity type semiconductor substrate 1 is provided on the surface of the semiconductor integrated circuit board formed by the semiconductor integrated circuit board, and only the surface of the separation groove 3 is formed. A thermal oxide film 4a having a thickness of about 5000 [Å] is selectively formed, and the isolation groove having the thermal oxide film 4a is filled with a polycrystalline silicon layer 5, and the exposed surface of the polycrystalline silicon layer 5 is For example, a thermal oxide film 4b having a thickness of about 8000 [Å] was formed.
(2' in the figure is a buried layer of the second conductivity type.) In the conventional dielectric isolation structure described above, the thermal oxide film 4a on the inner surface of the isolation trench 3 and the surface of the polycrystalline silicon layer 5 filled in the isolation trench For the oxide film 4b, a silicon nitride (Si 3 N 4 ) film 7 is provided on the active region 6 of the second conductivity type semiconductor layer 2 via a semiconductor oxide film 4 c, and the Si 3 N 4 film 7 is used as an oxidation-resistant mask. Thermal oxide films 4a and 4b are formed by selective thermal oxidation.
also grows under the edge of the Si 3 N 4 film 7, resulting in a bird's beak as shown in the figure.
beak) 8 and protrusions 9 are known.
Therefore, the conventional structure had the following problems. That is, the bird's beak 8 is 1 to 1.5 [μ
m], the width of the isolation region is expanded to reduce the degree of integration, and self-
There is a problem that the dimensions of the aligned diffusion window and electrode window become inaccurate and the characteristics of the functional element fluctuate, and a problem that wiring breaks occur at the acute-angled step portion 10 formed in the protrusion. The problem is that wiring material that tends to remain on the acute-angled step portion 10 causes short circuits between wirings.
本発明は上記問題点を除去し、半導体集積回路
装置の集積度、製造歩留まり、信頼性等の向上を
図る目的で、バーズ・ビークや突起がほとんど発
生することのない半導体集積回路装置の製造方法
を提供する。 The present invention aims to eliminate the above-mentioned problems and improve the degree of integration, manufacturing yield, reliability, etc. of semiconductor integrated circuit devices.The present invention aims to eliminate the above-mentioned problems and improve the degree of integration, manufacturing yield, reliability, etc. of semiconductor integrated circuit devices. I will provide a.
即ち本発明は、被処理基板上に半導体酸化膜を
介在させて窒化シリコン膜を被着形成する工程、
該被処理基板面に前記窒化シリコン膜及び半導体
酸化膜を貫いて分離溝を形成する工程、該分離溝
内に表出する半導体表面に選択的に半導体酸化膜
を形成する工程、該分離溝の半導体酸化膜及び該
窒化シリコン膜上に多結晶シリコン層を堆積形成
する工程、該被処理基板上にりん珪酸ガラス層を
形成し、該りん珪酸ガラス層で該分離溝を埋める
工程、該りん珪酸ガラス層を該分離溝内にその一
部を残してエツチング除去する工程、該工程によ
り表出された該多結晶シリコン層を選択的に底面
まで酸化して、該窒化シリコン膜及び該分離溝開
口部を覆う二酸化シリコン膜を形成する工程、該
被処理基板上に絶縁層を形成して該分離溝を埋め
る工程、該絶縁層及びその下層の該二酸化シリコ
ン膜を、該窒化シリコン膜を表出させるまで上面
より順次除去する工程、該窒化シリコン膜を除去
する工程とを有することを特徴とする半導体集積
回路装置の製造方法に関するものである。 That is, the present invention includes a step of depositing a silicon nitride film on a substrate to be processed with a semiconductor oxide film interposed therebetween;
forming an isolation trench on the surface of the substrate to be processed through the silicon nitride film and the semiconductor oxide film; selectively forming a semiconductor oxide film on the semiconductor surface exposed in the isolation trench; a step of depositing a polycrystalline silicon layer on the semiconductor oxide film and the silicon nitride film; a step of forming a phosphosilicate glass layer on the substrate to be processed; and a step of filling the isolation groove with the phosphosilicate glass layer; A step of removing the glass layer by etching leaving a portion of the glass layer in the isolation trench, selectively oxidizing the polycrystalline silicon layer exposed by this step to the bottom surface, and removing the silicon nitride film and the opening of the isolation trench. forming a silicon dioxide film covering the substrate, forming an insulating layer on the substrate to fill the isolation trench, exposing the insulating layer and the silicon dioxide film thereunder, and exposing the silicon nitride film. The present invention relates to a method of manufacturing a semiconductor integrated circuit device, comprising the steps of sequentially removing the silicon nitride film from the upper surface until the silicon nitride film is completely removed.
以下本発明を第２図に示す一実施例の最終工程
の断面図及び第３図ａ乃至ｇに示す工程断面図を
用いて詳細に説明する。 The present invention will be explained in detail below with reference to the final process cross-sectional view of an embodiment shown in FIG. 2 and the process cross-sectional views shown in FIGS. 3a to 3g.
本発明により得られた半導体集積回路装置
（IC）は、例えば第２図に示すように、第１の導
電型を有する半導体基板即ちＰ型シリコン（Si）
基板１１上に第２導電型をする半導体層即ちＮ型
Siエピタキシヤル層１２が積層形成されてなる半
導体IC基板の表面に、前記Ｎ型Siエピタキシヤル
層１２を貫いてＰ型Si基板１１内に達する例えば
Ｖ字形の分離溝１３と、該分離溝１３の内面に形
成された厚さ1000〔Å〕程度の薄い半導体酸化膜
１４と、分離溝１３の開口部近傍領域を除く前記
半導体酸化膜１４上に形成された例えば厚さ2000
〔Å〕程度の多結晶Si層１５と、該多結晶Si層１
５が形成するＶ字形の溝内を埋めるりん珪酸ガラ
ス層（PSG）層１６と、該PSG層１６、多結晶
Si層１５及び半導体酸化膜１４が配設された分離
溝１３の開口部を覆う例えば厚さ１〜1.5〔μｍ〕
程度の二酸化シリコン（SiO2）膜１７とを少な
くとも有してなる誘電体分離領域１８により、Ｎ
型Siエピタキシヤル層１２からなる活性領域１９
が分離された構造を有している。（図中２０はN+
型埋込み層、２１は活性領域を覆うSiO2膜を示
す。）
そして上記構造を有する半導体ICを形成する
には、第３図ａに示すように例えばＰ型Si基板１
１上にN+型埋込み層２０を内蔵して、厚さ２〜
３〔μｍ〕程度Ｎ型Siエピタキシヤル層１２が積
層形成されてなる半導体IC基板上に、先ず窒化
シリコン（Si3N4）膜の下敷きSiO2膜２１を熱酸
化法により1500〔Å〕程度の厚さに形成して後、
該下敷きSiO2膜２１上に2000〔Å〕程度の厚さの
Si3N4膜２２を化学気相成長（CVD）法により形
成し、次いで該Si3N4膜２２上に通常のフオト・
プロセスを用いて活性領域１９上を覆うフオト・
レジスト・パターン２３を形成する。次いで該フ
オト・レジスト・パターン２３をマスクとして、
例えばドライ・エツチング法を用い、先ず四弗化
炭素（CF4）＋酸素（O2）等をエツチヤントとし
てフオト・レジスト・パターン２３間に表出する
Si3N4膜２２をエツチング除去し、続いて三弗化
メタン（CHF3）等をエツチヤントとして下敷き
SiO2膜２１をエツチング除去し、次いで前記フ
オト・レジスト・パターン２３を除去して後、
Si3N4膜２２パターン間に表出せしめられたSi層
を水酸化カリウム（KOH）等の異方性エツチン
グ液を用いてエツチングして、該領域にＮ型Siエ
ピタキシヤル層１２を貫いてＰ型Si基板１１内に
達するＶ字形の分離溝１３を形成し、Ｎ型Siエピ
タキシヤル層１２を複数の活性領域１９に分離す
る。 The semiconductor integrated circuit device (IC) obtained according to the present invention has a semiconductor substrate having a first conductivity type, that is, P-type silicon (Si), as shown in FIG.
A semiconductor layer of the second conductivity type, that is, N type, is formed on the substrate 11.
A V-shaped separation groove 13, for example, which penetrates the N-type Si epitaxial layer 12 and reaches into the P-type Si substrate 11, is formed on the surface of the semiconductor IC substrate on which the Si epitaxial layer 12 is laminated. A thin semiconductor oxide film 14 with a thickness of about 1000 [Å] formed on the inner surface of the semiconductor oxide film 14 and a thin semiconductor oxide film 14 with a thickness of about 2000 [Å] formed on the semiconductor oxide film 14 except for the region near the opening of the isolation trench 13.
A polycrystalline Si layer 15 of about [Å] and the polycrystalline Si layer 1
A phosphosilicate glass layer (PSG) layer 16 filling the V-shaped groove formed by
For example, the thickness is 1 to 1.5 [μm] to cover the opening of the isolation trench 13 in which the Si layer 15 and the semiconductor oxide film 14 are provided.
A dielectric isolation region 18 having at least a silicon dioxide (SiO 2 ) film 17 of approximately
active region 19 consisting of type Si epitaxial layer 12;
has a separate structure. (20 in the figure is N +
A mold burying layer 21 indicates a SiO 2 film covering the active region. ) In order to form a semiconductor IC having the above structure, for example, a P-type Si substrate 1 is used as shown in FIG. 3a.
1 with a built-in N + type buried layer 20 and a thickness of 2~
On a semiconductor IC substrate on which an N-type Si epitaxial layer 12 of approximately 3 [μm] thickness is laminated, a silicon nitride (Si 3 N 4 ) film is first underlaid, and an SiO 2 film 21 is deposited to a thickness of approximately 1500 [Å] by thermal oxidation. After forming to a thickness of
A film with a thickness of about 2000 [Å] is deposited on the underlying SiO 2 film 21.
A Si 3 N 4 film 22 is formed by chemical vapor deposition (CVD), and then conventional photolithography is performed on the Si 3 N 4 film 22.
A process is used to create a photo film covering the active area 19.
A resist pattern 23 is formed. Then, using the photoresist pattern 23 as a mask,
For example, using a dry etching method, carbon tetrafluoride (CF 4 ) + oxygen (O 2 ) or the like is first exposed between the photoresist patterns 23 using an etchant.
The Si 3 N 4 film 22 is removed by etching, and then trifluoromethane (CHF 3 ) or the like is used as an etchant.
After removing the SiO 2 film 21 by etching and then removing the photoresist pattern 23,
The Si layer exposed between the Si 3 N 4 film 22 patterns is etched using an anisotropic etching solution such as potassium hydroxide (KOH), and the N-type Si epitaxial layer 12 is etched into the area. A V-shaped isolation trench 13 reaching into the P-type Si substrate 11 is formed to separate the N-type Si epitaxial layer 12 into a plurality of active regions 19 .
次いで前記Si3N4膜２２を耐酸化マスクとして
該基板の選択熱酸化を行つて、第３図ｂに示すよ
うに前記分離溝１３の表面に、選択的に1000〔Å〕
程度の薄い半導体酸化膜１４（SiO2膜）を形成
し、次いで該基板上に前記分離溝１３内面も含め
て、2000〜3000〔Å〕程度の厚さの第１の多結晶
Si層１５を通常の気相成長法を用いて形成し、次
いで該第１の多結晶Si層１５上にCVD法を用い
て1.5〜２〔μｍ〕程度の厚さで例えば８〔wt％〕
程度の五酸化りん（P2O5）濃度を有するりん珪
酸ガラス（PSG）層を堆積形成する。ここに於
て、分離溝１３内のPSG層１６中に含まれるり
ん（Ｐ）が、後の工程に於て行われる高温処理に
於てＮ型Siエピタキシヤル層１２及びＰ型Si基板
１１内に拡散し、半導体ICの性能がそこなわれ
ることを防ぐストツパとしての役割を前記第１の
多結晶Si層１５が果たすので、分離溝１３の内面
に形成する半導体酸化膜１４（SiO2膜）は該第
１の多結晶Si層１５とＮ型Siエピタキシヤル層１
２及びＰ型Si基板１１との絶縁が保てるだけの厚
さがあれば良く、従つて前述のように1000〔Å〕
程度に極めて薄くすることができる。そのため該
半導体酸化膜１４（SiO2膜）を選択熱酸化によ
り形成する際、分離溝１３の上縁部にバーズ・ビ
ークや突起は殆んどあらわれない。 Next, selective thermal oxidation of the substrate is performed using the Si 3 N 4 film 22 as an oxidation-resistant mask, and as shown in FIG.
A thin semiconductor oxide film 14 (SiO 2 film) is formed on the substrate, and then a first polycrystalline film with a thickness of about 2000 to 3000 Å is formed on the substrate, including the inner surface of the separation groove 13.
A Si layer 15 is formed using a normal vapor phase growth method, and then a CVD method is used on the first polycrystalline Si layer 15 to a thickness of about 1.5 to 2 [μm], for example, 8 [wt%].
A layer of phosphosilicate glass (PSG) having a phosphorus pentoxide (P 2 O 5 ) concentration of about 100% is deposited. Here, phosphorus (P) contained in the PSG layer 16 in the separation groove 13 is absorbed into the N-type Si epitaxial layer 12 and the P-type Si substrate 11 during high-temperature treatment performed in a later process. Since the first polycrystalline Si layer 15 plays the role of a stopper to prevent the semiconductor IC from being diffused and deteriorating the performance of the semiconductor IC, the semiconductor oxide film 14 (SiO 2 film) formed on the inner surface of the isolation groove 13 is is the first polycrystalline Si layer 15 and the N-type Si epitaxial layer 1
2 and the P-type Si substrate 11, it is sufficient to have a thickness of 1000 [Å] as described above.
It can be made extremely thin. Therefore, when the semiconductor oxide film 14 (SiO 2 film) is formed by selective thermal oxidation, almost no bird's beak or protrusion appears on the upper edge of the isolation trench 13.
次いで該基板を1050〜1150〔℃〕程度の高温に
加熱し、前記PSG層１６を溶融し、第３図ｃに
示すように前記分離溝１３をPSG層１６により
完全に埋め、次いで第３図ｄに示すように弗酸
（HF）系の液を用いるウエツト・エツチング或
るいはCHF3を用いるドライ・エツチング法によ
り前記PSG層１６を上面から順次エツチングし
て行き、分離溝内１３の一部のPSG層１６を残
留せしめ、他の領域のPSG層１６をエツチング
除去する。 Next, the substrate is heated to a high temperature of about 1050 to 1150 [°C] to melt the PSG layer 16 and completely fill the separation groove 13 with the PSG layer 16 as shown in FIG. As shown in d, the PSG layer 16 is sequentially etched from the top surface by wet etching using a hydrofluoric acid (HF)-based solution or dry etching using CHF 3 , and a part of the inside of the separation groove 13 is etched. The PSG layer 16 in other areas is left and the PSG layer 16 in other areas is removed by etching.
次いで通常の熱酸化法に従つて上記エツチング
処理によつて表出せしめられた領域の第１の多結
晶Si層１５を選択的に底面まで酸化し、第３図ｅ
に示すように分離溝１３の開口部及びSi3N4膜２
２上に4000〜6000〔Å〕程度の厚さの第１のSiO2
膜２４を形成する。なお該選択酸化処理に於て分
離溝１３内の第１の多結晶Si層１５の下層には、
前述のように予め半導体酸化膜（SiO2膜）１４
が形成されているので、Ｎ＋Siエピタキシヤル層
１２に酸化が及ぶのがある程度阻止されるので、
分離溝１３開口部の周囲にバーズ・ビークや突起
を発生させずに第１の多結晶Si層１５のみを完全
に酸化せしめることが可能である。 Next, the first polycrystalline Si layer 15 in the area exposed by the etching process is selectively oxidized down to the bottom surface according to a normal thermal oxidation method, as shown in FIG. 3e.
As shown in FIG .
A first SiO 2 film with a thickness of about 4000 to 6000 [Å] is deposited on top of 2.
A film 24 is formed. In addition, in the selective oxidation treatment, the lower layer of the first polycrystalline Si layer 15 in the isolation groove 13 is
As mentioned above, the semiconductor oxide film (SiO 2 film) 14 is
is formed, so that oxidation is prevented to some extent from reaching the N+Si epitaxial layer 12.
It is possible to completely oxidize only the first polycrystalline Si layer 15 without generating bird's beaks or protrusions around the opening of the isolation trench 13.
次いで通常の気相成長法を用いて、該基板上
に、前記分離溝１３上に形成されている凹部を充
たすに充分な厚さ、例えば0.5〜１〔μｍ〕程度の
厚さの第２の多結晶Si層を堆積形成し、次いで該
第２の多結晶Si層をO2圧５〔Kg／cm2〕、温度1050
〔℃〕程度の条件で行う通常の高圧酸化法により
底面まで酸化して、第３図ｆに示すように該基板
上に厚さ１〜２〔μｍ〕程度の厚い第２のSiO2膜
２５を形成する。なお、該高圧酸化処理に於て分
離溝１３の開口部は前記1000〔Å〕程度の厚さの
半導体酸化膜１４と更にその上層の厚さ4000〜
6000〔Å〕程度の第１のSiO2膜２４で保護されて
いるため、酸化がＮ型Siエピタキシヤル層１２に
及ぶことがなく、従つてバーズ・ビークや突起等
は形成されない。 Next, a second layer having a thickness of about 0.5 to 1 μm, for example, sufficient to fill the recess formed on the separation groove 13, is deposited on the substrate using a normal vapor phase growth method. A polycrystalline Si layer is deposited and then the second polycrystalline Si layer is heated at an O 2 pressure of 5 [Kg/cm 2 ] and a temperature of 1050°C.
A thick second SiO 2 film 25 with a thickness of about 1 to 2 [μm] is formed on the substrate by oxidizing it to the bottom surface by a normal high-pressure oxidation method carried out at about [°C], as shown in FIG. 3f. form. In addition, in the high-pressure oxidation process, the opening of the isolation groove 13 is formed by forming the semiconductor oxide film 14 with a thickness of about 1000 [Å] and the upper layer having a thickness of 4000 [Å].
Since it is protected by the first SiO 2 film 24 with a thickness of about 6000 Å, oxidation does not reach the N-type Si epitaxial layer 12, and therefore bird's beaks, protrusions, etc. are not formed.
次いでラツピング法等を用いて上記第２の
SiO2膜２５とその下層の第１のSiO2膜２４を、
活性領域１９上に形成されているSi3N4膜２２の
上面が完全に表出するまで上面から順次研摩除去
して後、煮沸りん酸（H3PO4）等を用いてSi3N4
膜２２を溶解除去し、第３図ｇに示すように該半
導体IC基板の表面に、前記SiO2膜２１を表面に
有するＮ型Siエピタキシヤル層１２を貫いてＰ型
Si基板１１内に達するＶ字形の分離溝１３内に、
該分離溝１３の内面に形成された厚さ1000〔Å〕
程度の薄い半導体酸化膜１４と該半導体酸化膜１
４上に形成された多結晶Si層１５を介してPSG層
１６が配設され、開口部が厚さ4000〜6000〔Å〕
程度の第１のSiO2膜２４を介して第２のSiO2膜
２５で埋められた構造を有し、且つ前記Ｎ型Siエ
ピタキシヤル層１２を複数の活性領域１９に分離
する誘電体分離領域１８を形成する。 Then, using wrapping method etc., the second
The SiO 2 film 25 and the first SiO 2 film 24 below it,
After removing the Si 3 N 4 film 22 formed on the active region 19 by sequential polishing from the top surface until the top surface is completely exposed, the Si 3 N 4 film 22 is removed using boiled phosphoric acid (H 3 PO 4 ) or the like.
The film 22 is dissolved and removed, and a P -type film is formed on the surface of the semiconductor IC substrate as shown in FIG.
In the V-shaped separation groove 13 that reaches into the Si substrate 11,
A thickness of 1000 [Å] formed on the inner surface of the separation groove 13
A somewhat thin semiconductor oxide film 14 and the semiconductor oxide film 1
A PSG layer 16 is disposed through a polycrystalline Si layer 15 formed on 4, and the opening has a thickness of 4000 to 6000 [Å].
a dielectric isolation region that has a structure filled with a second SiO 2 film 25 through a first SiO 2 film 24 of about 100-degrees, and that separates the N-type Si epitaxial layer 12 into a plurality of active regions 19; form 18.
次いで図示しないが、前記活性領域１９に、通
常の方法に従つてトランジスタ、抵抗等の形成を
行つて、バイポーラ型半導体ICが提供される。 Next, although not shown, transistors, resistors, etc. are formed in the active region 19 according to a conventional method to provide a bipolar semiconductor IC.
なお上記実施例に於ては、本発明をバイポーラ
型半導体ICについて説明したが、本発明はMIS
型半導体ICにも適用することができる。 In the above embodiments, the present invention was explained with respect to a bipolar semiconductor IC, but the present invention also applies to MIS.
It can also be applied to type semiconductor ICs.
又、分離溝の形状はＶ字形に限らず、Ｕ字形で
も勿論さしつかえない。 Further, the shape of the separation groove is not limited to a V-shape, but may of course be a U-shape.
以上説明したように本発明によれば、バーズ・
ビークや急峻な突起部の殆んどない誘電体分離領
域が提供される。従つて本発明によれば、分離領
域の拡大が防止できるので半導体ICの集積度の
向上が図れる。又平坦な配線形成面が得られるの
で配線品質が確保され、半導体ICの製造歩留ま
りが向上する。そして又本発明の誘電体分離領域
内には前述のようにりん珪酸ガラス層が設けられ
ているので、該りん珪酸ガラスのアルカリ・イオ
ンに対するゲツタ作用により半導体ICの信頼度
も向上する。 As explained above, according to the present invention, the birds
A dielectric isolation region is provided that is substantially free of peaks and sharp protrusions. Therefore, according to the present invention, it is possible to prevent the separation region from expanding, thereby improving the degree of integration of the semiconductor IC. Furthermore, since a flat wiring formation surface is obtained, wiring quality is ensured and the manufacturing yield of semiconductor ICs is improved. Furthermore, since the phosphosilicate glass layer is provided in the dielectric isolation region of the present invention as described above, the reliability of the semiconductor IC is also improved due to the getter action of the phosphosilicate glass on alkali ions.
第１図は従来の誘電体分離構造の断面図、第２
図は本発明の一実施例の最終工程の断面図で、第
３図ａ乃至ｇは本発明の半導体集積回路装置の製
造方法に於ける一実施例の工程断面図である。
図に於て、１１はＰ型シリコン基板、１２はＮ
型シリコン・エピタキシヤル層、１３は分離溝、
１５は多結晶シリコン層（第１の多結晶シリコン
層）、１６はりん珪酸ガラス層、１７は二酸化シ
リコン層、１８は誘電体分離領域、１９は活性領
域、２０はN+型埋込み層、２１は活性領域を覆
う二酸化シリコン膜（窒化シリコン膜の下敷き二
酸化シリコン膜）、２２は窒化シリコン膜、２３
はフオト・レジスト・パターン、２４は第１の二
酸化シリコン膜、２５は第２の二酸化シリコン膜
を示す。
Figure 1 is a cross-sectional view of a conventional dielectric isolation structure;
The figure is a cross-sectional view of the final step of an embodiment of the present invention, and FIGS. 3a to 3g are cross-sectional views of the process of an embodiment of the method of manufacturing a semiconductor integrated circuit device of the present invention. In the figure, 11 is a P-type silicon substrate, 12 is an N
type silicon epitaxial layer, 13 is an isolation trench,
15 is a polycrystalline silicon layer (first polycrystalline silicon layer), 16 is a phosphosilicate glass layer, 17 is a silicon dioxide layer, 18 is a dielectric isolation region, 19 is an active region, 20 is an N + type buried layer, 21 is a silicon dioxide film covering the active region (silicon dioxide film underlying the silicon nitride film), 22 is a silicon nitride film, 23
24 represents a photoresist pattern, 24 represents a first silicon dioxide film, and 25 represents a second silicon dioxide film.
Claims (1)
化シリコン膜を被着形成する工程、 該被処理基板面に前記窒化シリコン膜及び半導
体酸化膜を貫いて分離溝を形成する工程、 該分離溝内に表出する半導体表面に選択的に半
導体酸化膜を形成する工程、 該分離溝の半導体酸化膜及び該窒化シリコン膜
上に多結晶シリコン層を堆積形成する工程、 該被処理基板上にりん珪酸ガラス層を形成し、
該りん珪酸ガラス層で該分離溝を埋める工程、 該りん珪酸ガラス層を該分離溝内にその一部を
残してエツチング除去する工程、 該工程により表出された該多結晶シリコン層を
選択的に底面まで酸化して、該窒化シリコン膜及
び該分離溝開口部近傍を覆う二酸化シリコン膜を
形成する工程、 該被処理基板上に絶縁層を形成して該分離溝を
埋める工程、 該絶縁層及びその下層の該二酸化シリコン膜
を、該窒化シリコン膜を表出させるまで上面より
順次除去する工程、 該窒化シリコン膜を除去する工程 とを有することを特徴とする半導体集積回路装置
の製造方法。[Claims] 1. A step of depositing and forming a silicon nitride film on a substrate to be processed with a semiconductor oxide film interposed therebetween, and forming a separation groove penetrating the silicon nitride film and the semiconductor oxide film on the surface of the substrate to be processed. a step of selectively forming a semiconductor oxide film on the semiconductor surface exposed in the isolation trench; a step of depositing a polycrystalline silicon layer on the semiconductor oxide film and the silicon nitride film in the isolation trench; Forming a phosphosilicate glass layer on the substrate to be processed,
a step of filling the separation groove with the phosphosilicate glass layer; a step of etching and removing the phosphosilicate glass layer leaving a portion of it in the separation groove; and selectively removing the polycrystalline silicon layer exposed by the step. oxidizing to the bottom surface to form a silicon dioxide film covering the silicon nitride film and the vicinity of the opening of the isolation trench; forming an insulating layer on the substrate to be processed to fill the isolation trench; and a step of sequentially removing the silicon dioxide film underlying the silicon dioxide film from the upper surface until the silicon nitride film is exposed, and a step of removing the silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1946281A JPS57133645A (en) | 1981-02-12 | 1981-02-12 | Semiconductor integrated circuit device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1946281A JPS57133645A (en) | 1981-02-12 | 1981-02-12 | Semiconductor integrated circuit device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57133645A JPS57133645A (en) | 1982-08-18 |
| JPH0217937B2 true JPH0217937B2 (en) | 1990-04-24 |
Family
ID=11999986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1946281A Granted JPS57133645A (en) | 1981-02-12 | 1981-02-12 | Semiconductor integrated circuit device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57133645A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0834242B2 (en) * | 1988-12-08 | 1996-03-29 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4869485A (en) * | 1971-12-22 | 1973-09-20 | ||
| JPS5379473A (en) * | 1976-12-24 | 1978-07-13 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1981
- 1981-02-12 JP JP1946281A patent/JPS57133645A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4869485A (en) * | 1971-12-22 | 1973-09-20 | ||
| JPS5379473A (en) * | 1976-12-24 | 1978-07-13 | Fujitsu Ltd | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57133645A (en) | 1982-08-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4853343A (en) | Method for fabricating a semiconductor integrated circuit device having thick oxide films and groove etch and refill | |
| EP0072966B1 (en) | Integrated circuit structure and method for forming a recessed isolation structure for integrated circuits | |
| KR950000096B1 (en) | Formation of insulated contact aperture of semiconductor article | |
| JPH0216574B2 (en) | ||
| JPH02102556A (en) | Method of forming isolation region in substrate of integrated circuit structure | |
| JPH0217937B2 (en) | ||
| JPH0338741B2 (en) | ||
| JPS6040701B2 (en) | Method for manufacturing a semiconductor device having a polycrystalline silicon layer | |
| JPS6359538B2 (en) | ||
| JP2812013B2 (en) | Method for manufacturing semiconductor device | |
| KR100895824B1 (en) | Method for forming isolation layer of semiconductor device | |
| JPH0521592A (en) | Manufacture of semiconductor device and semiconductor device | |
| KR19990021366A (en) | Device Separation Method of Semiconductor Device | |
| JPH079930B2 (en) | Method for manufacturing semiconductor device | |
| JPS60161632A (en) | Semiconductor device and manufacture thereof | |
| JPH01244635A (en) | Manufacture of semiconductor device | |
| KR100416813B1 (en) | Field Oxide Formation Method of Semiconductor Device | |
| KR100204418B1 (en) | Method for forming an element isolation in a semiconductor device | |
| JPS6322065B2 (en) | ||
| JPS59149030A (en) | Manufacture of semiconductor device | |
| JPH023257A (en) | Semiconductor device having field shield structure and its manufacture | |
| JPH04326549A (en) | Semiconductor device | |
| KR19990021358A (en) | Device Separation Method of Semiconductor Devices | |
| JPS6117143B2 (en) | ||
| JPH0669066B2 (en) | Method for manufacturing semiconductor device |