JPH02178974A - Composite mos type semiconductor element - Google Patents

Abstract

PURPOSE:To make regions for a mainly functioning MOS type switching element larger than a region as an amplifier by combining and unifying a region working at the ON time of the amplifier for driving a gate compounded with the mainly functioning switching element and a region working at the OFF time. CONSTITUTION:When a first conductivity type takes an n-type, an n-channel is formed in a third channel region 12 when positive voltage is applied to a gate terminal G when positive voltage is applied to a drain electrode 15, and an n-channel is shaped in a first channel region 7 and a mainly functioning switching element is turned ON. When negative voltage is applied to the gate terminal G, p-channels are formed in second channel regions 10 among a fifth region 5 between the dividing sections of a sixth region 6 and third regions 3 on both sides, the potential of the third regions 3 is brought to the same potential as the potential of an intermediate electrode 16 and a gate electrode 17 through the channels, and the mainly functioning switching element is turned OFF. Accordingly, regions for the mainly functioning switching element can be made larger than a region as an amplifier.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is a composite MOS type semiconductor that integrates a vertical power MOSFET used as a power switching element, an insulated gate bipolar transistor (IGBT), and an input amplifier. Regarding elements.

[Conventional technology]

Vertical power M used as a power switching element
In recent years, the chip size of OSFETs and the like has been increasing due to the increase in current. Along with this, the input capacitance has increased, so the input impedance has become smaller, and it can no longer necessarily be called a voltage-driven element. To avoid this, a power M with a complex gate drive amplifier is used.
OSFETs have been proposed. Its configuration is as shown in FIG. That is, a high-resistance n-layer 2 (second region) is formed on the n-substrate 1 (first region), and this n-
A p'' layer 3 (third region) and a p'' layer 5 (fifth region) are selectively formed on the surface of the layer 2, and further a p'' layer 3p'' layer 5 is formed.
n' layer 4 (fourth region) and n' layer 6 (
The sixth region) is formed. 94 layer 3 n - layer 2 and n
+ The surface area sandwiched by layer 4 is the main power MOSFET.
A gate electrode 9 (first gate electrode) is formed thereon via a gate insulating film 8 so as to form a channel region 7 (first channel region) of T. A gate electrode 11 (second gate electrode) is formed on the surface of the n-layer 2 with a gate insulating film 8 interposed therebetween, so that the portion sandwiched between the p'layer 3p'' layer 5 serves as a second channel region 10. is formed.p layer 5
A gate electrode 13 (third gate electrode) is formed on the surface region sandwiched between the n'' layer 2 and the n'' layer 6 with a gate insulating film 8 interposed therebetween, so as to define a third channel region 12. and a source electrode 14 in contact with the 94 layer 3 and the n4 layer 4.
A drain electrode 15 is provided in contact with the surface of the n+ substrate 1. Further, an intermediate electrode 16 is provided which contacts the p' layer 5 and the n' layer 6, and is electrically connected to the gate electrode 9. Furthermore, the gate electrode 11 and the gate electrode 13 are electrically connected and become the gate electrode of the composite element. In this element, when a positive voltage is applied to the gate terminal G connected to the gate electrodes 11 and 13 while a positive voltage is applied to the drain electrode 15, a positive voltage is applied to the intermediate electrode 16 through the third channel region 12. A charging current flows through the gate electrode 9,
An n-channel is formed in the first channel region 7 by the gate electric field, and the main power MOSFET is turned on. Furthermore, when a negative voltage is applied to the gate electrode 11, the potential of the p' layer 3 becomes equal to the potential of the p' layer 5 which is in contact with the electrode 16 via the p channel formed in the second channel region 10, so that the gate electrode The potential of layer 9 becomes equal to that of layer 3, and no gate electric field is applied to the first channel region 7, making it the main power MOSF.
ET turns off.

[Problem to be solved by the invention]

In such a composite device, the second channel region 10 and the third channel region 12, which serve as input amplifiers for turning on and off the main power MOSFET, are connected to the main power MOSFET.
Since it is placed on one side of the first channel region 7 of the SFET, it has been difficult to increase the size of the main power MOSFET.

An object of the present invention is to provide a composite MOS type semiconductor device in which the area for the main switching element is larger than the area for the amplifier.

[Means to solve the problem]

In order to solve the above problems, the present invention includes a first region of a first conductivity type with a high impurity concentration, a second region of the first conductivity type with a low impurity concentration provided on the first region, and a second region of the first conductivity type with a low impurity concentration provided on the first region. A third region and a fifth region of the second conductivity type and independent from each other are selectively formed on the surface of the two regions, and a third region and a fifth region of high impurity concentration are selectively formed on the surface of the third region and the fifth region. It has a fourth region and a sixth region of one conductivity type, and the part sandwiched between the second region and the fourth region on the surface of the third region is called the first channel region and the third region on the surface of the second region. The part sandwiched between the fifth region and the second channel region is the second channel region, and the part of the surface of the fifth region sandwiched between the second region and the sixth region is the third channel region. first gate electrode, through the membrane
a second gate electrode and a third gate electrode, the second and third gate electrodes are connected to each other to the gate terminal, a source electrode simultaneously contacts the surfaces of the third region and the fourth region, and a source electrode that contacts the surfaces of the third region and the fourth region simultaneously; In a composite MOS type semiconductor device in which an intermediate electrode is formed in simultaneous contact with the surface of the region and connected to the first gate electrode, and a drain electrode is formed in the surface of the first region, a sixth region is formed on the surface of the fifth region. The region is divided into parts arranged in two parallel rows, and gate electrodes that also serve as second and third gate electrodes are provided on the edges of each divided row and connected to the gate terminals, and the third region are formed on both sides of the fifth region.

[Effect]

Now, if the first conductivity type is n-type, if a positive voltage is applied to the gate terminal while a positive voltage is applied to the drain electrode, the third channel region under the second and third gate electrodes will be An n-channel is formed in the first channel region of the third region provided on both sides, and the main switching element is turned on. When a negative voltage is applied to the gate terminal, an n-channel is formed in the second channel region between the fifth region between the divided portions of the sixth region and the third regions on both sides, and the n-channel is formed in the third region through the channel. The potential becomes equal to the potential of the fifth region, that is, the intermediate electrode and the gate electrode, and the main switching element is turned off.

Even when the first conductivity type is p-type, the polarity is reversed, so that exactly the same effect is performed.

〔Example〕

FIG. 1 is a perspective view showing a cross section of a semiconductor element of a power MO5FET according to an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals.

As can be seen from the figure, a pair of n' layers 6 (sixth region) are formed on the surface of the p' layer 5 (fifth region), and p
A gate electrode 17 is provided spanning the 91 layer 3 and the p' layer 5 and connected to the gate terminal G via the gate insulating film. It is divided into 6 island-like layers and arranged in two rows on both sides.

This gate electrode 17 is the second gate electrode 1 in FIG.
1 and the third gate electrode 13.

That is, when a positive voltage is applied to the drain electrode 15 and a positive voltage is applied to the gate electrode 17, an n channel is formed in the surface region 12 sandwiched between the p layer 5, the n+ layer 6, and the n− layer 2. from the intermediate electrode 16 to the first gate electrode 9
Charging current flows through, turning on the MOSFETs on both sides. Furthermore, when a negative voltage is applied to the gate electrode 17, the divided n
An n-channel is formed in the second channel region 10 between the p" layer 5 in the intermediate region of the layers and the opposing p" layer 3, and the p" layer 3 intermediate electrode 16. Since the potential is equal to that of the first gate electrode 9, no channel is formed in the first channel region 7, and the MOSFETs on both sides are turned off. Therefore, the MOS constituted by the third region 3 on both sides by one fifth region 5 serving as an amplifier.
Can switch FET and is the main MOS
The area for the FET is larger than the area for the amplifier. It is clear that the above explanation holds true even if the n-type and p-type are interchanged.

Furthermore, the above explanation applies to a composite MOS type semiconductor device having the structure shown in FIG. 1 and having an IGBT as a main switching element with a p' layer added between the first region 1 and the drain electrode 15.

〔Effect of the invention〕

According to the present invention, in order to combine and integrate a region that works when the gate drive amplifier is combined with the main MOS switching element and a region that works when it turns off, the ratio of the area occupied by the main element of the amplifier is increased. becomes smaller,
A composite MOS type semiconductor element with reduced dimensions can be obtained as a power switching element with a small input capacitance.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing a cross section of a semiconductor element of a power MOSFET according to an embodiment of the present invention, and FIG. 2 is a conventional composite MOS.
It is a sectional view of FET. ■=First region (n” substrate), 2: Second region (n layer)
3: Third region (p” layer) 4: Fourth region (n layer)
5: Fifth region (p" layer) 6: Sixth class kA (n" layer) 7: First channel region, 8: Gate insulating film, 9:
First gate electrode, 10: second channel region, 12: third channel region, 14: source electrode, 15 drain electrode, 16: intermediate electrode, 17: second and third) gate electrode. ″・１４．・、N

Claims (1)

[Claims] (1) Selectively formed in the first region of the first conductivity type with high impurity concentration, the second region of the first conductivity type with low impurity concentration provided on the first region, and the surface portion of the second region A third region and a fifth region of the second conductivity type, which are independent from each other, and a fourth region and a sixth region of the first conductivity type with a high impurity concentration selectively formed on the surfaces of the third region and the fifth region. The part of the surface of the third region sandwiched between the second region and the fourth region is the first channel region, and the part of the surface of the second region sandwiched between the third region and the fifth region is the first channel region. A portion of the surface of the second channel region and the fifth region sandwiched between the second region and the sixth region is defined as a third channel region. a gate electrode, and a third gate electrode, the second and third gate electrodes are connected to each other to the gate terminal, and a source electrode and the surfaces of the sixth and fifth regions are in simultaneous contact with the surfaces of the third region and the fourth region. An intermediate electrode is formed which is simultaneously in contact with the first gate electrode and connected to the first gate electrode.
In the device in which the drain electrode is formed on the surface of the first region, the sixth region formed on the surface of the fifth region is divided into two parts arranged in parallel rows, and the edge of each divided partial row is A composite MOS type semiconductor device, characterized in that gate electrodes serving as second and third gate electrodes are provided above the gate electrodes and are connected to the gate terminals, and the third region is formed on both sides of the fifth region.