JPH02178964A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase latch-up resistance by forming a crystal defect region into a substrate except a depletion layer region spread from each source, drain and channel region of a MOS transistor and the depletion layer region of the junction section of the substrate and a well. CONSTITUTION:Oxygen O<+> is implanted for shaping a crystal defect layer 5 into an n-well 4. Acceleration energy is selected so that the crystal defect layer 5 is formed near the peak value of the impurity concentration of the retrograde n-well 4 at that time. An element isolation 6, an nMOSFET 7 and a pMOSFET 8 are shaped, thus completing a CMOS structure semiconductor device. Since the crystal defect layer 5 has no effect on the operation of the pMOSFET 8, however, the crystal defect layer 5 is formed to a section lower than a depletion layer spread from each source, drain and channel region of the pMOSFET 8 in the n-well 4. Consequently, minority carriers causing latch-up are trapped to the crystal defect region 5, thus shortening the lifetime of minority carriers. Accordingly, latch-up resistance is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to controlling the lifetime of minority carriers in semiconductors,
In particular, the present invention relates to a semiconductor device used as a CMOS latch-up resistant structure and a method for manufacturing the same.

Conventional technology Latch-up is a major problem in semiconductor devices with a CMOS structure, but one way to suppress this is to use retrograde 6-wells, which are formed using ion implantation with high acceleration energy of several hundred keV or more. is being actively researched. Ion implantation with high acceleration energy can form a highly concentrated impurity region at a position deeper than the surface of the semiconductor substrate with good controllability. Therefore, it is possible to form a log grade type well with a peak impurity concentration in the lower region of the well, or to form a buried layer with a high degree of 1 degree.
The resistance of the base region of the parasitic bipolar formed by the structure can be lowered, and the trigger current that induces latch-up can be suppressed. In addition, by using high acceleration energy ion implantation, the heat treatment time can be shortened, so it is possible to suppress the lateral migration of impurities.

From the above two points, the latch-up resistance can be improved to some extent by high acceleration energy ion implantation, and the separation distance between wells (n"-p" distance) can be reduced.

Furthermore, in high acceleration energy ion implantation, there is a phenomenon in which crystal defects are more likely to occur as the acceleration energy is increased or the dose is increased.

For example, phosphorus (p+) ions are applied to a silicon substrate at a voltage of 2 MeV.
For example, Japanese Journal of Aplyst Physics 25.6 (1986), pp. 474 to 477 ( JAPANESE JOllRNAL O
F APPLIED PHYSICS, VOL, 25.
NO, [i, 198 [i, PP, L474-L477,
M, TAMURA and N, NATSUAKl,
“5econdary Defects in
2MeV Pb.

5phorus l11planted 5ilico
n”).

In addition, as another means for suppressing latch-up more than the L-log grade type well, a shrimp substrate or SOI structure is used, but the process is complicated and the cost is high.

Problems to be Solved by the Invention However, with such a structure, the process is complicated and the cost is high, or it is difficult to prevent latch-up even when semiconductor devices having an 0NO8 structure are further integrated. There was a problem.

The present invention has been attempted in view of the above-mentioned problems, and an object of the present invention is to provide a semiconductor device that is easy to process, low in cost, and has improved latch-up resistance, and a method for manufacturing the same.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides an 0NO semiconductor substrate having at least a well of a second conductivity type in a semiconductor substrate of a first conductivity type.
8 structure, the first NO formed on the well
a first depletion layer region extending from each source, drain, and channel region of the 8 transistor; and a source of a second MOS transistor formed on the substrate other than the well;
A structure including a crystal defect region in the substrate except for each depletion layer region of a second depletion layer region extending from each drain and channel region and a third depletion layer region at a junction between the substrate and the well. It is something that

Effects of the present invention Due to the dual configuration, the minority carriers that cause latch-up are trapped in the crystal defect region, and the lifetime of the minority carriers is reduced, so that the effect of suppressing latch-up can be further enhanced.

Example (Example 1) FIG. 1 is a process diagram for forming a crystal defect layer inside a well layer of a semiconductor device having an 0NO8 structure in a first example of the present invention. The process of forming a crystal defect layer inside the well layer will be described below with reference to FIG.

An oxide film 2 is formed as an ion implantation protective film on a p-type silicon substrate 1, and a resist 3 is further applied and patterned, and the resist in the n-well layer formation area is selectively developed and removed. Thereafter, phosphorus p''' is implanted by high acceleration energy φ ion implantation at 700 keV] under the conditions of 0XIQI3·cm-2 to form a retrograde n-well 4. Furthermore, a crystal defect layer 5 is placed inside the n-well 4. In order to form the crystal defect layer 5, oxygen 0+ is implanted here. At this time, the acceleration energy is selected so that the crystal defect layer 5 is formed near the peak value of the impurity concentration of the retrograde n-well 4 (
(See Figure 1(a)). Furthermore, element isolation 6, n M OS
FET7.9NO8FET8 is formed and CNO
An eight-structure semiconductor device (FIG. 1(b)) is completed. However, since the crystal defect layer 5 does not affect the operation of the 9NO8FET 8, the crystal defect layer 5 is
It is necessary to form it below the depletion layer extending from the source, drain, and channel regions of the 8FET8.

In the semiconductor device of this example configured as described above, minority carriers generated due to noise or the like increase in the crystal defect layer 5 formed in the retrograde n-well 4, thereby reducing the lifetime.

Therefore, latch-up resistance can be improved. Furthermore, in this embodiment, since the crystal defect layer 5 is formed near the peak value of the impurity concentration in the retrograde n-well 4,
It has the lowest resistance and the ability to collect the minority carriers is high.

Therefore, latch-up resistance can be more effectively improved.

(Example 2) FIG. 2 is a process diagram for forming a crystal defect layer inside a buried layer of a semiconductor device in a second example of the present invention. The process of forming a crystal defect layer inside the buried layer will be described below with reference to FIG.

After forming an oxide film 2 as an ion implantation protective film on a p-type silicon substrate 1, boron B4 is applied to the entire surface at 1.5 MeV for 3.5 minutes to form a p-type buried layer 9. OX 1013cm-2
High acceleration energy ion implantation. Further, oxygen 04 is implanted to form a crystal defect layer 10. At this time, acceleration energy is selected so as to form the crystal defect layer IO inside the buried layer. After that, in the same manner as in the first embodiment,
A retrograde n-well 4 (see FIG. 2(a)), an element isolation 6, and a MOSFET 7.8 are formed to complete a CMOS structure semiconductor device (see FIG. 2(b)).

In the semiconductor device of this embodiment configured as described above, minority carriers generated due to noise etc. are collected in the buried layer 9 with low resistance, and further passed through the crystal defect layer IO formed inside the buried layer. This will reduce the lifetime. Therefore, latch-up resistance can be improved. Moreover, since the crystal defect layer 10 is formed inside the buried layer, M
OSFET7.8 and retrograde n-well 4 are not affected. Furthermore, the crystal defect layer 10 is formed in the n-well 4.
If the region is closer to the lower part of the depletion layer region at the junction between the substrate 1 and the substrate 1, the latch-up resistance can be further improved.

Note that the crystal defect layer is formed inside the well in the first embodiment, and in the second embodiment.
In the embodiment described above, it was formed inside the buried layer, but it is not limited to these regions and may be formed inside the substrate.

However, if a crystal defect layer exists in the depletion layer region spreading from the source, drain, and channel regions of the MOS transistor and the depletion layer region at the junction between the substrate and the well, this will cause leakage current, so these regions are excluded. be done. Further, although a silicon substrate was used in the first and second embodiments, a semiconductor substrate other than a silicon substrate may be used. Although a p-type silicon substrate was used, the same effect can be obtained with an n-type silicon substrate, but other conductivity types must be reversed.

Further, the well structure may be a twin Φ well structure.

Further, although oxygen 0+ was ion-implanted to form a crystal defect layer, S 11 A ul P t or the like may be used. Furthermore, in order to form a crystal defect layer, the impurity concentration must be at least I ”
/cm2 or more, crystal defects can be generated at the same time. Furthermore, the same effect can be obtained by combining low-dose ion implantation and a semiconductor substrate with a high oxygen concentration.

Effects of the Invention As is clear from the second explanation, the present invention provides a depletion layer region extending from the source, drain, and channel regions of a MOS transistor, and a depletion layer region at the junction between the substrate and the well in the substrate. By providing a crystal defect region in
Minority carriers that cause latch-up are trapped in crystal defect regions, and the lifetime of the minority carriers is reduced, so latch-up resistance can be improved, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 is a process diagram showing a method of manufacturing a semiconductor device according to a first embodiment of the invention, and FIG. 2 is a process diagram showing a method of manufacturing a semiconductor device according to a second embodiment of the invention. 4...Retrograde n-well, 5.10...
Crystal defect layer, 9...p-type buried waste.

Claims (2)

[Claims] (1) In a CMOS structure having at least a well of a second conductivity type in a semiconductor substrate of a first conductivity type, a first depletion that spreads from the source, drain, and channel regions of a first MOS transistor formed on the well layer area;
a second MOS formed on the substrate other than the well;
A crystal defect region is formed in the substrate except for each depletion layer region of a second depletion layer region extending from each source, drain, and channel region of the transistor and a third depletion layer region at a junction between the substrate and the well. A semiconductor device comprising: (2) In a CMOS structure having at least a well of a second conductivity type in a semiconductor substrate of a first conductivity type, a first depletion that spreads from the source, drain, and channel regions of a first MOS transistor formed on the well; layer area;
a second MOS formed on the substrate other than the well;
Crystals are formed by ion implantation into the substrate except for the second depletion layer region extending from the source, drain, and channel regions of the transistor and the third depletion layer region at the junction between the substrate and the well. A method for manufacturing a semiconductor device, the method comprising forming a defective region.