JPH0217545A - Information processing system - Google Patents

Abstract

PURPOSE:To communicate trouble with a normal operation processor by providing a communication means which reports an operation processor being in trouble to higher-order operation processor in the non-trouble state and all operation processors connected to the other ports. CONSTITUTION:This information processing system consists of a main storage device 1, a system controller 2, operation processors 300, 301, 310, and 311, and a diagnosing device 4. Operation processors 301 and 311 are connected to operation processors 300 and 310 and are connected to the system controller 2 in series. When detecting internal trouble, each operation processor reports the occurrence of trouble to the diagnosing device 4 through signal lines 11, 12, 13, and 14. The diagnosing processor 4 is internally provided with a trouble factor register 40, a trouble communication circuit 41, and a trouble processing controller 42 and performs maintenance and diagnosis of the system.

Description

[Detailed description of the invention] [Industrial application field]

The present invention includes a main storage device, a system control device connected to the main storage device, a plurality of arithmetic processors connected in series to each of one or more ports of the system control device, and each arithmetic processor. The present invention relates to an information processing system having a diagnostic processor that performs fault processing.

[Conventional technology]

In conventional large-scale information processing systems, multiple processors are typically connected one by one to a pre-prepared port on a system control device, and failure handling for each processor is performed independently. . For example, if a failure occurs in any arithmetic processor, failure processing (logout processing, retry processing, etc.) is performed only for that arithmetic processor. During this time, other normal processors can operate without any problem, and a communication is sent to these processors to notify them of the faulty processor, and a fault report is sent to the operating system. In recent years, information processing systems such as supercomputers that perform high-speed calculations have appeared, and the number of calculation processors tends to increase in proportion to system performance. In such systems, it has become difficult to connect all the processors directly to the system control device as in the past, and a method has been proposed in which the processors are connected in series by limiting the number of connection ports. However, in a system where arithmetic processors are connected in series, if a failure occurs in any arithmetic processor, the arithmetic processors connected on the opposite side of the system control unit from the perspective of that arithmetic processor will have access to the system control unit. is cut off, making it impossible to continue normal operation. [Problems to be Solved by the Invention] In the conventional information processing system described above, when a failure occurs in any processor, the failure report (communication) to the normal processor is only sent to the processor in which the failure has occurred. Therefore, in an information processing system configured with arithmetic processors connected in series, it is not only the arithmetic processor in which the failure has occurred, but also the one connected to the side opposite to the system control device from the perspective of that arithmetic processor. Although it is necessary to recognize a group of processors, including a group of processors that have failed, as a failure state, if the range of transition to a failure state differs depending on the physical location of the processor where the failure has occurred, it is possible to The disadvantage is that it does not allow necessary and effective fault communication to the computer processor.

[Means to solve the problem]

In the information processing system of the present invention, the diagnostic processor has a bit corresponding to each arithmetic processor, inputs and holds a fault report signal from the arithmetic processor, activates a fault processing control unit, and executes a fault processing program for the corresponding arithmetic processor. Among the arithmetic processors, for each port of the system control device, the arithmetic processor group connected to the system control device side as seen from any arithmetic processor is connected to the upper arithmetic processor group, and also to the system control device. When a group of arithmetic processors connected on the opposite side of the device is a lower processor group, when any bit of the failure cause register is turned on, the corresponding arithmetic processor and its lower arithmetic processor group are placed in a failure state, It has a failure communication means that performs failure communication to inform all the arithmetic processors connected to the upper arithmetic processor group and other ports that are in a non-failure state of the arithmetic processor that has transitioned to a failure state. r Effect] In the diagnostic processor, the fault cause register with bits corresponding to the arithmetic processor inputs and holds the fault report signal from the arithmetic processor in which the fault has occurred, starts the fault processing control unit, and executes the fault processing program for the arithmetic processor. At the same time, the fault communication means sets the arithmetic processor corresponding to the turned-on bit of the fault factor register and its lower arithmetic processor group into a fault state, and connects it to the upper arithmetic processor group in a non-fault state and other ports. Since failure communication is carried out to notify all processors of the processor that has entered the fault state, the processor in an information processing system having multiple processors connected in series to one or more ports of the system control Necessary and effective failure communication becomes possible in the event of a failure. [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the information processing system of the present invention, FIG. 2 is a circuit diagram of the fault cause register 40 shown in FIG. 1, and FIG. 3 is a circuit diagram of the fault communication circuit 41 shown in FIG. be. This information processing system includes a main storage device 1, a system control device 2, and arithmetic processors 300, 301, 310 and 3.
11 and a diagnostic processor 4. The three ports of the system control device 2 have main storage devices 1.
Arithmetic processors 300 and 310 are connected to each other, and access to the main storage device 1 from the arithmetic processors 300 and 310 and arithmetic processors 301 and 311 described later is controlled. Arithmetic processors 300.301.310 and 3
11 are processors of the same type, including arithmetic processors 301 and 3;
11 are connected to the arithmetic processors 300 and 310, respectively, and the arithmetic processors 300 and 310 are connected to the system control device 2.
．． 301 and arithmetic processors 310 and 311 are each connected in series. Further, when the arithmetic processors 300, 301, 310 and 311 detect an internal failure, the signal lines I21. β2゜β3 + 1
The failure occurrence is reported to the diagnostic processor 4 via 24. Furthermore, the arithmetic processors 300, 301, 310, and 311 each receive fault information consisting of 4 bits from the diagnostic processor 4 through the signal line β5. The diagnostic processor 4, which is configured to receive the signal via the β6°βt4g, has an internal fault factor register 40. It includes a fault communication circuit 41 and a fault processing control device 42, and executes system maintenance diagnosis. The failure factor register 40 is the arithmetic processor 300.30.
1. This is a 4-bit register that holds the failure factors of 310 and 311. As shown in FIG.
24 respectively arithmetic processor 300.301.3
10 and 311 are input and held, and their output signals are sent to signal lines β400. I2401. β402
and I2403 are input to the fault communication circuit 41 through the signal line fi40, and the fault processing control unit 42
is input. The fault processing control unit 42 executes a system fault processing program and activates a desired fault processing program according to the contents of the fault cause register 40 input via the signal line β40. Table 1 shows the correspondence between the values of the failure cause register 40 and the failure programs to be started. Table 1 The failure communication circuit 41 inputs the contents of the failure factor register 40 via the signal line β40, recognizes the arithmetic processor in the failure state based on the information, and indicates the failure state to the arithmetic processor that can continue normal operation. Communicate processor information to be transferred to. The failure communication circuit 41 is shown in FIG. 3 below.
Explain the details. The fault communication circuit 41 includes two OR gates 440.441 and 16 AND gates 400-403.410-413.
．． - It is composed of 420-423 and 430-433. 1400°I240! , ρ402.1403 is a 4-bit signal line output from the failure factor register 40 as shown in FIG.
01. β402 inputs failure signals from the arithmetic processor 310 and arithmetic processor 311 to the failure communication circuit 41. In addition, signal lines f1400 to I240
3 is inside the failure communication circuit 41, and I2400 is the OR gate 440. ANDGATE 401-403.420.4
30, β401 is ORGATE 440. and gate 4
01, β402 is ORGATE 441. and gate 4
02.412.420.421.423 and also β40
3 is orgate 441. The inputs are connected to AND gates 423 as shown in the figure. or gate 440
．． 441 is connected as described above, its output signal line I2406. The logic of I2407 is 4406 = 12400 + 1240112407
=β402+4403, and the signal line ℃406 is an AND gate 412.413
421 and 431, and the signal line f2407 is input connected to AND gates 403 and 413, 430, and 431, respectively, as shown in the figure. Also, and gate 40
0°410.411.422.432.433 inputs have a logic “0” and level signal input through signal line β405.AND gates 400-403.410-41
3. 420 to 423 and 430 to 433 are gate circuits that generate fault communication signals to the arithmetic processors 300, 301, 310 and 311, respectively, and are AND gates.
400-403 output signal lines 124000-I2400
3 are arithmetic processors 300, 301, 310, respectively.
．． When 311 transitions to a failure state, it becomes "l". Also, AND gates 410 to 413.
0~433 output signal line 124100~! 241O3,
Similarly, β4200 to β4203.14300 to I24303 are each arithmetic processor 300.301.31.
The output logic of these AND gates, which becomes "L" when 0.311 goes into a fault state, is as follows from the input connections described above. Below is the margin and therefore the arithmetic processors 300.301.310.
The failure communication contents when a failure occurs in each of the processors 311 and 311 are as shown in Table 2.
When a failure occurs in the system controller 2, the arithmetic processors 301 and 311 are notified that the arithmetic processor 301 has also entered the failure state, and the arithmetic processors 300 and 30 connected in series in a superior/subordinate relationship to the system control device 2 are notified.
1, 310, and 311, necessary and effective failure communication is realized. [Effects of the Invention] As explained above, the present invention has a diagnostic processor having a bit corresponding to each arithmetic processor, inputs and holds a fault report signal from the arithmetic processor, activates the fault processing unit, and performs the corresponding arithmetic operation. When a fault factor register that causes a processor fault handling program to be executed and any bit in the fault factor register are turned on, the corresponding arithmetic processor and its lower arithmetic processor group are placed in a fault state, and the upper arithmetic processor group and other ports are By providing a failure communication means that performs failure communication to notify all connected processors of the processor that wants to transition to a failure state, the main storage, the system control device connected to the main storage, and one of the system control devices In an information processing system that has a plurality of processors connected in series to one or more ports, a failure occurs in any processor, cutting off access to the system control unit and preventing normal operation from continuing. Since the lower-level processing processors that have become enabled are also notified as a failure state to other processing processors in a normal state, an information processing system capable of necessary and effective fault communication when a fault occurs in a processing processor can be realized. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the information processing system of the present invention, FIG. 2 is a circuit diagram of the fault cause register 40 shown in FIG. 1, and FIG. 3 is a circuit diagram of the fault communication circuit 41 shown in FIG. be. l... ・・・・・・ ・Main storage device,
2 ・・・・・・・・・・・・・・・System control device, 300, 301.310.311...
Arithmetic processor, 4・・・・・・・・・・・・・・・
...Diagnostic processor, 40... ...
・・・・・・Fault cause register, 41・・・・・・・
...... Faulty communication circuit, 42...
......Fault processing control unit, 440,
441・・・・・・・・・・・・・・・Or Gate,
124200~124203°β4300~I24303...Signal line. [Calculation aΩ7ヅ廿1fiElbu'0Sezusa sacrilege]17'fl
300b'5 301b et al.
310 force ゛b 31ii"6Irl: 1 door 1 1 blind l atmosphere 41 block number processing Itl opening part Otsu part 4 22 figure

Claims (1)

[Claims] 1. A main storage device, a system control device connected to the main storage device, and a plurality of arithmetic processors connected in series to each of one or more ports of the system control device. , and a diagnostic processor that performs fault processing for each arithmetic processor, wherein the diagnostic processor has a bit corresponding to each arithmetic processor, inputs and holds a fault report signal from the arithmetic processor, and includes a fault processing control unit. an arithmetic processor connected to the system control device side as viewed from an arbitrary arithmetic processor for each port among the arithmetic processors; If the group is an upper arithmetic processor group and the arithmetic processor group connected on the opposite side of the system control device is a lower processor group, when any bit of the fault factor register is turned on, the corresponding arithmetic processor and its A failure communication means is provided for placing a lower arithmetic processor group in a failure state and performing failure communication to inform the upper arithmetic processor group in a non-fault state and all arithmetic processors connected to other ports of the arithmetic processor that has transitioned to a fault state. An information processing system characterized by: