JPH02174329A - External synchronizing clock generating circuit - Google Patents

Abstract

PURPOSE:To prevent the influence of a code error or the like on the system by supplying the detection output of a phase comparator to a voltage controlled oscillating circuit and synchronizing the output clock of the voltage controlled oscillating circuit with an external selection input clock. CONSTITUTION:Phase difference absorbing circuits (20-1)-(20-n) provided corresponding to each of external input clocks (1-1)-(1-n) use an output clock 7 whose frequency is nf as a common reference clock to synchronize all phases of phase synchronizing clocks (4-1)-(4-n) to a clock selection circuit 30. Thus, even if an external input clock with different phase exists in the external input clocks (1-1)-(1-n), no frequency jump is caused in the output clock 7 to switch the selected external input clock 5. Thus, the fluctuation of the phase difference detected by the phase comparator 40 and the frequency jump of the output clock 7 are not caused and the influence of the code error or the like on the system is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an external synchronous clock generation circuit suitable for use in a digital communication device.

[Conventional technology]

Conventionally, this type of external synchronous clock generation circuit includes a voltage controlled oscillation circuit, a phase comparison circuit, and a clock selection circuit.
Selecting one of the plurality of external input clocks by a clock selection circuit, detecting the phase difference between the selected external input clock (selected external input clock) and the output clock of the voltage controlled oscillation circuit by a phase comparison circuit, By supplying the detection power of this phase comparison circuit to the voltage controlled oscillation circuit,
The output clock of the voltage controlled oscillation circuit is synchronized in frequency with the external input clock.

[Problem to be solved by the invention]

However, according to such a conventional external synchronous clock generation circuit, when the selected external input clock is switched in the clock selection circuit, if the selected external input clock before switching and the selected external input clock after switching have different phases, In the phase comparator circuit, a phase difference instantaneously occurs from the phase synchronization state before switching. As a result, a frequency jump occurs in the output clock of the voltage controlled oscillator circuit, which was synchronized with the selected external input clock before switching.
A problem has arisen in that the system is affected by code errors and the like.

[Means to solve the problem]

The present invention has been made to solve such problems, and includes a flip-flop that is provided corresponding to each of the first to Nth external input clocks and samples the external input clock, and a flip-flop that samples the external input clock. An elastic memory that adjusts the phase of a sampled external input clock, and a write address reset pulse generation circuit and a read address reset pulse generation circuit that generate write address reset pulses and read address reset pulses to the elastic memory. and first to Nth phase difference absorption circuits that synchronize the phases of the first to Nth external input clocks, and first to Nth phase difference absorption circuits that are phase synchronized by the first to Nth phase difference absorption circuits. a clock selection circuit that selects one of the N external input clocks, and a divided output clock obtained by dividing the selected external input clock selected by the clock selection circuit and the output clock of the voltage controlled oscillation circuit. The output clock of the voltage controlled oscillator circuit is synchronized with the selected external input clock by providing the detection power of the phase comparing circuit to the voltage control unit oscillation circuit. This is what I did.

[Effect]

Therefore, according to the present invention, even if the selected external input clock is switched, no phase difference occurs between the selected external input clock before switching and the selected external input clock after switching.

〔Example〕

The external synchronous clock generation circuit according to the present invention will be explained in detail below.

FIG. 1 is a block circuit diagram showing one embodiment of this external synchronous clock generation circuit. In the same figure, 20-1
~20-n are the first to Nth external input cloths 1 to 1 to 1
-n, the first to Nth phase difference absorption circuits are provided corresponding to each of the external input cloths 1-1 to 1-n, and 30 is the phase difference absorption circuit 20-1 to 20-n. -n
The external input clocks (phase synchronized clocks) 4-1 to 4-n whose phase has been synchronized are input, one of the phase synchronized clocks 4-1 to 4-n is selected, and the selected external input clock 5 is selected. 40 is a frequency-divided output clock obtained by dividing the selected external input clock 5 selected by the clock selection circuit 30 and the output clock 7 of the voltage controlled oscillation circuit 50 by n in a frequency dividing circuit 60. This is a phase comparator circuit that detects the phase difference with 8.

The phase comparison circuit 40 provides a DC voltage (frequency control signal) 6 based on the detected phase difference to the voltage controlled oscillation circuit 50,
The output clock 7 is synchronized with the selected external input clock 5 based on the supplied frequency control signal 6. This output clock 7 is then supplied to the subsequent stage as an external synchronization clock. On the other hand, the output clock 7 of the voltage controlled oscillation circuit 50 is
It is also used as a reference clock for 0-1 to 20-n.

Next, the configurations of the phase difference absorption circuits 20-1 to 20-n will be explained using the phase difference absorption circuit 20-1 as a representative. That is, since the configurations of the phase difference absorption circuits 20-2 to 20-n are the same as the phase difference absorption circuit 20-1, the explanation thereof will be omitted by showing only the configuration of the phase difference absorption circuit 20-1. The phase difference absorption circuit 20-1 includes a flip-flop 21 that samples the external input clock 1-1 as its data input, and an external input clock (phase absorption clock) 2 sampled by the flip-flop 21 as its data input and its phase. a write address reset pulse generation circuit 22 that generates a write address reset pulse 3 for the elastic memory 23 based on the phase of the phase absorption clock 2; The read address reset pulse generation circuit 24 generates the address reset pulse 9. The clock input terminal of the flip-flop 21, the write address reset pulse input terminal of the write address reset pulse generation circuit 22, the write [ ] input terminal and the read clock input terminal of the elastic memory 23, the read address reset pulse Departure'J
The output clock 7 is applied to each of the read address reset pulse input terminals of the E times 124.

Note that the read address reset pulse 9 sets the frequency of the external input clock being selected based on the output clock 7 given to the read address reset pulse generation circuit 24.
When , it occurs at a circumference of Ml/r.

Furthermore, when the frequency of the external input clock being selected is r, the output clock 7 is obtained at a frequency nf (n is an integer) that is n times that frequency, and is supplied to the read clock input terminal of the elastic memory 23. In accordance with the timing of the output clock 7 and the read address reset pulse 9 from the read address reset pulse generation circuit 24, a phase-adjusted phase synchronized clock 4-1 is obtained from the elastic memory 23 as its data output. It has become.

FIG. 2 shows the clock waveforms of each part showing the operation of this external synchronous clock generation circuit. C) is the phase absorption clock 2 obtained as the data output of the flip-flop 21, (d) is the write address reset pulse 3 to the elastic memory 23 generated by the write address reset circuit 22, (e
l is the read address reset pulse 9 to the elastic memory 23 generated by the read address reset pulse generation circuit 24, (fl is the phase-adjusted phase synchronized clock 41 obtained as the data output of the elastic memory 23). .

That is, the phase difference absorbing circuits 20-1 to 20-0 provided corresponding to each of the external input clocks 1-1 to 1-n use the output clock 7 of frequency nf as a common reference clock, and the clock selection circuit Phase synchronized clock 4-1 to 30
Since all phases of ~4.0 are synchronized, even if there are external input clocks with different phases in external input clocks 1-1 to l-n, the selected external clock will not cause a frequency jump in output clock 7. The input clock 5 can now be switched. In other words, even if there are external input clocks with different phases, all of the phase synchronized clocks 4-1 to 4-n are phase-synchronized by the phase difference absorption circuits 20-1 to 20-n. 5, no phase difference occurs between the selected external input clock 5 before switching and the selected external input clock 5 after switching. For this reason,
There is no fluctuation in the phase difference detected by the phase comparator circuit 40, no frequency jump occurs in the output clock 7, and the effects of code errors and the like on the system can be prevented.

〔Effect of the invention〕

As explained above, according to the external synchronous clock generation circuit according to the present invention, a flip-flop is provided corresponding to each of the first to Nth external input clocks and samples the external input clock; an elastic memory that adjusts the phase of an external input clock, and a write address reset pulse generation circuit and a read address reset pulse generation circuit that generate a write address reset pulse and a read address reset pulse to the elastic memory, Since the first to Nth phase difference absorption circuits that synchronize the phases of the first to Nth external input clocks are provided, even if the selected external input clock is switched, the selected external input clock before switching will be different from the selected external input clock after switching. Assuming that there is no phase difference with the selected external input clock, and therefore no fluctuation occurs in the phase difference detected by the phase comparator circuit, and no frequency jump occurs in the output clock of the voltage controlled oscillation circuit, This makes it possible to prevent the effects of code errors and the like from affecting the system.

[Brief explanation of the drawing]

FIG. 1 is a block circuit configuration diagram showing one embodiment of an external synchronous clock generation circuit according to the present invention, and FIG. 2 is a waveform diagram of each part showing the operation of this circuit. 20-1 to 20-n...phase difference absorption circuit, 21...
Flip-flop, 22...Write address recent pulse generation circuit, 23...Erastenk memory, 24.
...Read address recent pulse generation circuit, 30...
Clock selection circuit, 40... Phase comparison circuit, 50...
- Voltage controlled oscillation circuit, 60... frequency divider circuit.

Claims (1)

[Claims] A flip-flop is provided corresponding to each of the first to Nth external input clocks and samples the external input clock, and the phase of the external input clock sampled by the flip-flop is adjusted. an elastic memory; a write address reset pulse generation circuit and a read address reset pulse generation circuit that generate a write address reset pulse and a read address reset pulse to the elastic memory; First to Nth phase difference absorption circuits that synchronize the phases of the clocks, and one of the first to Nth external input clocks whose phases are synchronized by the first to Nth phase difference absorption circuits. a clock selection circuit that selects a clock, and a phase comparison circuit that detects a phase difference between the selected external input clock selected by the clock selection circuit and a divided output clock obtained by dividing the output clock of the voltage controlled oscillation circuit. An external synchronization clock generation circuit that synchronizes the output clock of the voltage controlled oscillation circuit with the selected external input clock by providing the detection power of the phase comparison circuit to the voltage controlled oscillation circuit.