JPH02172771A - Manufacture of led array head substrate - Google Patents
Manufacture of led array head substrateInfo
- Publication number
- JPH02172771A JPH02172771A JP63328001A JP32800188A JPH02172771A JP H02172771 A JPH02172771 A JP H02172771A JP 63328001 A JP63328001 A JP 63328001A JP 32800188 A JP32800188 A JP 32800188A JP H02172771 A JPH02172771 A JP H02172771A
- Authority
- JP
- Japan
- Prior art keywords
- led array
- insulating layer
- head substrate
- pattern
- array head
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000004020 conductor Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 15
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 9
- 239000011889 copper foil Substances 0.000 claims abstract description 7
- 229910052737 gold Inorganic materials 0.000 claims abstract description 5
- 239000010931 gold Substances 0.000 claims abstract description 5
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract 2
- 230000017525 heat dissipation Effects 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims description 2
- 238000009429 electrical wiring Methods 0.000 claims 1
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052802 copper Inorganic materials 0.000 abstract description 6
- 239000010949 copper Substances 0.000 abstract description 6
- 229910002092 carbon dioxide Inorganic materials 0.000 abstract description 5
- 239000001569 carbon dioxide Substances 0.000 abstract description 5
- 239000000835 fiber Substances 0.000 abstract description 5
- 229920003002 synthetic resin Polymers 0.000 abstract description 5
- 239000000057 synthetic resin Substances 0.000 abstract description 5
- BERDEBHAJNAUOM-UHFFFAOYSA-N copper(I) oxide Inorganic materials [Cu]O[Cu] BERDEBHAJNAUOM-UHFFFAOYSA-N 0.000 abstract description 2
- KRFJLUBVMFXRPN-UHFFFAOYSA-N cuprous oxide Chemical compound [O-2].[Cu+].[Cu+] KRFJLUBVMFXRPN-UHFFFAOYSA-N 0.000 abstract description 2
- 229940112669 cuprous oxide Drugs 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 238000000354 decomposition reaction Methods 0.000 abstract 1
- 239000012212 insulator Substances 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010030 laminating Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は電子写真記録装置の記録用光源として用いら
れるＬＥＤ （発光ダイオード）アレイヘッド基板の製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method of manufacturing an LED (light emitting diode) array head substrate used as a recording light source of an electrophotographic recording apparatus.
〔従来の技術］
最近、装置の小型、低価格化を目的とした記録装置とし
て半導体レーザを光源としたもの、光源の機械的スキャ
ンニングをなくし、併せて装置の小型化を図ったＬＥＤ
アレイ光源等が開発されている。[Prior Art] Recently, recording devices that use a semiconductor laser as a light source have been developed with the aim of making the device smaller and cheaper, and LEDs have been developed that eliminate mechanical scanning of the light source and also make the device more compact.
Array light sources and the like have been developed.
このＬＥＤアレイは、発光部の分解能がそのまま印刷の
分解能となるが、一般に上記した記録装置、すなわち、
光プリンタは高い分解能をもっていることが特徴で、例
えば分解能が１０本／ ｍ ｍの場合、発光部の配列ピ
ッチは０．１ｍｍという小さな値になる。またＬＥＤア
レイの駆動回路は現在、ＬＥＤアレイと同じ材料で構成
するが技術が未開発のため、現状ではシリコン集積回路
（ＩＣ）が使われており、従って上記ＬＥＤアレイとｔ
Ｃとを何らかの手段で接続する必要があり、この接続も
極めて高度になる。In this LED array, the resolution of the light emitting part directly becomes the printing resolution, but generally the above-mentioned recording device, that is,
Optical printers are characterized by high resolution; for example, when the resolution is 10 lines/mm, the arrangement pitch of the light emitting parts is as small as 0.1 mm. In addition, the drive circuit for the LED array is currently constructed from the same material as the LED array, but because the technology is undeveloped, silicon integrated circuits (ICs) are currently used, and therefore, the driver circuit for the LED array is made of the same material as the LED array.
It is necessary to connect it to C by some means, and this connection is also extremely sophisticated.
これらの接続には通常、高密度端子フレキシブルケーブ
ルを用いるか、又は１枚の絶縁性基板上に上記又種類の
部品を搭載し、部品間の接続を基板上に形成された高密
度配線で行う方法がとられる。These connections usually use high-density terminal flexible cables, or the above and other types of components are mounted on a single insulating board, and connections between the components are made with high-density wiring formed on the board. method is taken.
第３図及び第４図は例えば特公昭６１
２５０９号公報に示された図で、第３図は従来のＬＥＤ
アレイを示す外観図、第４図は第３図のＡ−Ａ断面図で
ある。図において、３１は絶縁性基板、３２は複数の発
光部を一列に有すると共に、その個別電極側の端子を発
光部列の両側に交互に取出したＬＥＤアレイ、３３゜３
４はＬＥＤアレイ駆動用ＩＣである。この駆動用ＩＣ３
３，３４とＬＥＤアレイ３２は上記絶縁性基板３１上に
塔載される。この場合、駆動用ＩＣ３３，３４は上記Ｌ
ＥＤアレイ３２の片側において絶縁性基板３１上に搭載
される。３５は駆動用ＩＣ３３，３４、およびＬＥＤア
レイ３２を外部回路と接続するための端子群で絶縁性基
板３１上に形成される配線群により接続される。第３図
ではこの配線群を省略した。Figures 3 and 4 are diagrams shown in, for example, Japanese Patent Publication No. 61 2509, and Figure 3 shows the conventional LED.
FIG. 4 is an external view showing the array, and is a sectional view taken along line AA in FIG. 3. In the figure, 31 is an insulating substrate, 32 is an LED array having a plurality of light emitting parts in a row, and terminals on the individual electrode side are taken out alternately on both sides of the row of light emitting parts, 33°3
4 is an LED array driving IC. This driving IC3
3 and 34 and the LED array 32 are mounted on the insulating substrate 31. In this case, the driving ICs 33 and 34 are
The ED array 32 is mounted on an insulating substrate 31 on one side. Reference numeral 35 denotes a terminal group for connecting the drive ICs 33 and 34 and the LED array 32 to an external circuit, and is connected by a wiring group formed on the insulating substrate 31. In FIG. 3, this wiring group is omitted.
次に第４図を参照してＬＥＤアレイの製造法について説
明する。まず、３６〜３８は絶縁性基板３１上に直接形
成された第１の配線である。前記第１の配線３６〜３８
のうち配線３６上にはその両端を除いて絶縁物３９が形
成される。前記絶縁物３９上には第２の配線４０〜４３
が形成される。そして該第２の配線４０上にＬＥＤアレ
イ３２が搭載される一方、同第２の配線４２上に駆動用
ＩＣ３３が搭載されており、更に第１の配線３７上に駆
動用ＩＣ３４が搭載される。第１の配線３６〜３８及び
第２の配線４０〜４３のうち、第１の配線３６は駆動用
ＩＣ３３，３４を配置した片側からＬＥＤアレイ３２の
反対側に引出される。この第１の配線３６は上記反対側
に端子が取出されているＬＥＤアレイ３２の例えば奇数
番の発光部とこれに電流を供給する駆動用ＩＣ３４の端
子とを結ぶもので、両端子と第１の配線３６との接続は
ワイヤ４４．４５で行われる。なお、この接続にはワイ
ヤ４４゜４５のほか例えばビームリード、あるいはテー
プキャリアなどのボンデング技術を用いてもよい。Next, a method for manufacturing the LED array will be explained with reference to FIG. First, 36 to 38 are first wirings formed directly on the insulating substrate 31. Said first wiring 36 to 38
An insulator 39 is formed on the wiring 36 except for its both ends. On the insulator 39 are second wirings 40 to 43.
is formed. The LED array 32 is mounted on the second wiring 40, a driving IC 33 is mounted on the second wiring 42, and a driving IC 34 is further mounted on the first wiring 37. . Among the first wirings 36 to 38 and the second wirings 40 to 43, the first wiring 36 is drawn out from one side where the driving ICs 33 and 34 are arranged to the opposite side of the LED array 32. This first wiring 36 connects, for example, the odd-numbered light emitting parts of the LED array 32 whose terminals are taken out on the opposite side and the terminal of the driving IC 34 that supplies current thereto, and connects both terminals and the first wiring 36. Connection with wiring 36 is made by wires 44, 45. In addition to wires 44.degree. 45, bonding techniques such as beam leads or tape carriers may be used for this connection.
一方、第２の配線４１は駆動用ＩＣ３３゜３４を配置し
た側であるところの上記片側に端子が取出されているＬ
ＥＤアレイ３２の偶数番の発光部と駆動用ＩＣ３３の端
子を結ぶもので、両端子と第２の配線４１との接続は奇
数番の場合と同様にワイヤ４６．４７で行われる。On the other hand, the second wiring 41 is an L with a terminal taken out on one side, which is the side where the driving IC 33 and 34 are arranged.
It connects the even numbered light emitting parts of the ED array 32 and the terminals of the driving IC 33, and the connection between both terminals and the second wiring 41 is made by wires 46 and 47 as in the case of the odd numbered ones.
また、第１の配線３８は駆動用ＩＣ３４の信号入出力、
クロック、電源などの端子とを結ぶもので、外部回線と
の接続用端子となる。この部分の接続はワイヤ４８で行
われる。Further, the first wiring 38 is used for signal input/output of the driving IC 34,
Connects to clock, power, etc. terminals, and serves as a terminal for connecting to external lines. Connections in this part are made with wires 48.
更に、第２の配線４３は駆動用ＩＣ３３の信号入出力、
クロック、電源などの端子を結ぶもので駆動用ＩＣ３４
の場合と同様であり、この部分の接続はワイヤ４９で行
われる。Furthermore, the second wiring 43 is for signal input/output of the driving IC 33,
Drive IC34, which connects terminals such as clock and power supply.
This is the same as in the case of , and the connection in this part is made by wire 49.
更に、第１の配線３７、第２の配線４２は駆動用ＩＣ３
４，３３に下面とダイボンドにより接続される配線で、
通常グランドレベルに落される。また、第２の配線４０
はＬＥＤアレイ３２の下面とダイボンドにより接続され
る配線で通常はマイナス電極となる。これらのダイボン
ドされる夫々の配線３７，４２．４０は外部回路との接
続用端子として引出される。Furthermore, the first wiring 37 and the second wiring 42 are connected to the driving IC 3.
4, 33 with the wiring connected to the bottom surface by die bonding,
Usually dropped to ground level. In addition, the second wiring 40
is a wiring connected to the lower surface of the LED array 32 by die bonding, and normally serves as a negative electrode. These die-bonded wires 37, 42, 40 are drawn out as terminals for connection to an external circuit.
なお、第１の配線３６〜３８、第２の配線４０〜４３は
絶縁性基板３１がアルミナなどのセラミックの場合、厚
膜、薄膜などの技術を用いて形成される。Note that, when the insulating substrate 31 is made of ceramic such as alumina, the first wirings 36 to 38 and the second wirings 40 to 43 are formed using a thick film technique, a thin film technique, or the like.
一方、配線間の絶縁物３９はアルミナ、ガラス、ＳｉＯ
□、樹脂などで形成される。On the other hand, the insulator 39 between the wirings is made of alumina, glass, SiO
□, made of resin, etc.
（発明が解決しようとする課題）
従来のＬＥＤアレイヘッド基板の製造方法は以上のよう
に実施されているので、このＬＥＤアレイヘッド基板を
用いて安定な発光出力を得るにはＬＥＤアレイ駆動用Ｉ
Ｃ３３，３４が発生する熱の放熱性を上げ、熱抵抗を下
げることが必要である。またＬＥＤ素子を複数配列した
ＬＥＤアレイは、絶縁物３９を介し、第１の配線３６と
ワイヤ４４で電気的に導通をとっているため放熱性が優
れず安定した発光出力が得られないなどの課題があった
。(Problems to be Solved by the Invention) Since the conventional method for manufacturing an LED array head substrate is carried out as described above, in order to obtain stable light emitting output using this LED array head substrate, the LED array driving I
It is necessary to improve the heat dissipation of the heat generated by C33 and C34 and to lower the thermal resistance. In addition, an LED array in which a plurality of LED elements are arranged is electrically connected to the first wiring 36 and the wire 44 through the insulator 39, so heat dissipation is poor and stable light output cannot be obtained. There was an issue.
本発明は上記のような課題を解決するためになされたも
ので、ＬＥＤアレイヘッド基板の製造方法において、支
持導体（銅板）に黒化処理を施し、アルミナペーパと合
成樹脂とから成る熱抵抗の低い絶縁層（プリプレグシー
ト）を課用することによって、ＬＥＤアレイやＬＥＤア
レイ駆動用ＩＣが発生する熱の放熱性を向上させ、発光
出力の安定性を図ると共に、支持導体と絶縁層との高接
着力を得るＬＥＤアレイヘッド基板の製造方法を得るこ
とを目的とする。The present invention was made in order to solve the above-mentioned problems, and in a method of manufacturing an LED array head board, a support conductor (copper plate) is subjected to blackening treatment, and a heat resistor made of alumina paper and synthetic resin is used. By applying a low-temperature insulating layer (pre-preg sheet), we can improve the heat dissipation of the heat generated by the LED array and LED array driving IC, stabilize the light output, and also improve the An object of the present invention is to obtain a method for manufacturing an LED array head substrate that obtains adhesive strength.
本発明によるＬＥＤアレイヘッド基板の製造方法は黒化
処理した支持導体上にアルミナ短繊維を主成分とするア
ルミナペーパと合成樹脂による絶縁層を形成し、その上
に銅箔を積層して加熱加圧成形すると共に、前記絶縁層
の一部を炭酸ガスレーザによって分解除去してＬＥＤア
レイの配列パターンを形成するようにしたものである。The method for manufacturing an LED array head board according to the present invention is to form an insulating layer made of alumina paper containing short alumina fibers as a main component and a synthetic resin on a supporting conductor that has been blackened, and then to deposit copper foil on top of the insulating layer and heat it. At the same time as pressure molding, a part of the insulating layer is decomposed and removed using a carbon dioxide laser to form an arrangement pattern of the LED array.
この発明におけるＬＥＤアレイヘッド基板は黒化処理を
施した支持導体上にアルミナペーパと合成樹脂とから成
る絶縁層を積層し、さらに該絶縁層上に銅箔を積層して
加熱加圧成形する。そして次に導体パターンの形成には
サブトラフト法により行い炭酸ガスレーザによって絶縁
層の一部を分解除去してＬＥＤアレイを配列するパター
ンを形成するので熱抵抗が小さく絶縁耐圧の高いものが
製造できる。The LED array head substrate according to the present invention is produced by laminating an insulating layer made of alumina paper and synthetic resin on a support conductor that has been subjected to a blackening treatment, and further laminating a copper foil on the insulating layer, followed by heat-pressing molding. Next, a conductor pattern is formed by a sub-traft method, and a part of the insulating layer is decomposed and removed using a carbon dioxide laser to form a pattern for arranging the LED array, so it is possible to manufacture a conductor pattern with low thermal resistance and high dielectric strength.
以下、本発明の製造方法を第２図のフローチャートを用
いて説明する。図中、第３図と同一の部分は同一の符号
をもって図示した第１図において、１はＬＥＤアレイ３
２やＬＥＤアレイ駆動用ＩＣ３３を電気的に溶着固定す
るダイボンド材、２はワイヤ４４を接続するため導体パ
ターン３上に施したニッケル・金メッキ、４は絶縁層（
プリプレグシート）、５は支持導体（銅板）である。The manufacturing method of the present invention will be explained below using the flowchart shown in FIG. In FIG. 1, the same parts as in FIG. 3 are designated by the same reference numerals. In FIG.
2 and a die-bonding material for electrically welding and fixing the LED array driving IC 33, 2 is a nickel/gold plating applied on the conductor pattern 3 to connect the wire 44, and 4 is an insulating layer (
5 is a supporting conductor (copper plate).
次にこの発明のＬＥＤアレイヘッド基板の製造法につい
て説明する。まず絶縁層４を製造するには次の材料を用
いて行われる。すなわち、材料としては繊維径が３〜５
μｍ、ｉａ維長が５〜５００μｍの範囲で繊維長分布を
有するアルミナ短繊維を主とするアルミナペーパを合成
樹脂で加熱成型してプリプレグシートを得る（ステップ
、５ＴＩ）。該アルミナペーパの坪量は約１１０ｇ／ｍ
２である。次に厚さ、約１ｍｍの支持導体５に黒化処理
を施し酸化第一銅を銅表面に形成させて作る（ステップ
、５ＴＹ）。Next, a method of manufacturing the LED array head substrate of the present invention will be explained. First, the insulating layer 4 is manufactured using the following materials. In other words, the material has a fiber diameter of 3 to 5.
A prepreg sheet is obtained by heat molding an alumina paper mainly composed of short alumina fibers having a fiber length distribution in the range of μm and ia from 5 to 500 μm using a synthetic resin (step 5TI). The basis weight of the alumina paper is approximately 110g/m
It is 2. Next, the support conductor 5 having a thickness of about 1 mm is subjected to blackening treatment to form cuprous oxide on the copper surface (step 5TY).
この支持導体５、すなわち銅板上に絶縁層４（プリプレ
グシート）を１枚重ね、さらにその上に片面粗面化銅箔
（例えば古河サーキット社製）１８μｍを重ね合せ、プ
レス圧力６０ ｋｇ／ｃｍ２、温度１８５℃で約９０分
間加熱加圧成形をして積層板を作成する（ステップ、５
Ｔ３）。そして次に公知のサブトラフト法により導体パ
ターン３の回路形成を行った後（ステップ、５Ｔ４）、
ＬＥＤアレイ３２を配列するためのダイボンド用の回路
、すなわち支持導体５の露出パターン（幅、約１．５ｍ
ｍ ）を形成するため炭素ガスレーザ（例えば、出力約
５００Ｗ）を用いて絶縁層４を分解除去する（ステップ
、５Ｔ５）。そして、前記サブトラフト法により形成さ
れた導体パターン３に電解ニッケル・金メッキを施して
ＬＥＤアレイヘッド基板を製作する（ステップ、５ＴＹ
）。このようにして製造されたＬＥＤアレイヘッド基板
の特性例を以下に示す。One insulating layer 4 (prepreg sheet) is superimposed on this supporting conductor 5, that is, a copper plate, and on top of that, a single-sided roughened copper foil (for example, manufactured by Furukawa Circuit Co., Ltd.) of 18 μm is superimposed, and a press pressure of 60 kg/cm2 is applied. A laminate is created by heat-pressing molding at a temperature of 185°C for about 90 minutes (step 5).
T3). Then, after forming a circuit of the conductor pattern 3 by a known sub-traft method (step 5T4),
A die-bonding circuit for arranging the LED array 32, that is, an exposed pattern of the supporting conductor 5 (width, approximately 1.5 m)
Insulating layer 4 is decomposed and removed using a carbon gas laser (for example, output of about 500 W) to form (step 5T5). Then, electrolytic nickel/gold plating is applied to the conductor pattern 3 formed by the sub-traft method to produce an LED array head substrate (step 5TY).
). Examples of the characteristics of the LED array head substrate manufactured in this manner are shown below.
ここで、上記Ｎｏ、 ６の冷熱衝撃試験の条件は一６５
℃、１５分間と＋１２５℃、１５分間を１サイクルとす
る１５０サイクル経過時点の材買変化の状況である。Here, the conditions for the thermal shock test in No. 6 above are -65
This shows the change in material purchase after 150 cycles, one cycle being 15 minutes at +125°C and 15 minutes at +125°C.
以上のように本発明によれば絶縁層にアルミナペーパを
用いＬＥＤアレイを配設するパターンの形成を炭酸ガス
レーザによって該絶縁層を分解除去し回路パターンを形
成するようにしたので、熱抵抗が小で放熱性に優れたＬ
ＥＤアレイヘッド基板を確実・容易に製造できる効果が
ある。As described above, according to the present invention, alumina paper is used as the insulating layer, and the pattern for arranging the LED array is formed by decomposing and removing the insulating layer using a carbon dioxide laser to form the circuit pattern, so that the thermal resistance is small. L with excellent heat dissipation
This has the effect of making it possible to reliably and easily manufacture the ED array head substrate.
第１図は本発明によるＬＥＤアレイヘッド基板の断面図
、第２図は第１図の基板を製造するための手順を示した
フローチャート、第３図は従来のＬＥＤアレイヘッド基
板の外観図、第４図は第３図のＡ−Ａ断面図である。
図において、１はダイボンド材、２はニッケル・金メッ
キ、３は導体パターン（銅箔）、４は絶縁層、５は支持
導体（銅板）、３２はＬＥＤアレイ、３３はＬＥＤアレ
イ駆動用ＩＣ，４４はワイヤである。
なお、図中、同一符号は同一または相当部分を示す。
寸FIG. 1 is a sectional view of an LED array head substrate according to the present invention, FIG. 2 is a flowchart showing the procedure for manufacturing the substrate of FIG. 1, FIG. 3 is an external view of a conventional LED array head substrate, and FIG. FIG. 4 is a sectional view taken along line AA in FIG. 3. In the figure, 1 is die bonding material, 2 is nickel/gold plating, 3 is a conductor pattern (copper foil), 4 is an insulating layer, 5 is a support conductor (copper plate), 32 is an LED array, 33 is an IC for driving the LED array, 44 is a wire. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. size
Claims (1)
の導体パターンにダイボンド材を介して固定し、ワイヤ
で電気配線を施して成るＬＥＤアレイヘッド基板の製造
方法において、前記ＬＥＤアレイ、及びＬＥＤアレイ駆
動用ＩＣと放熱用の支持導体間を絶縁する絶縁層をアル
ミナ短センイを主成分として樹脂加工して成形し、前記
支持導体を黒化処理した該支持導体上に絶縁層と銅箔を
重ねて加熱加圧成形し、前記銅箔にサブトラクト法によ
り導体パターンを形成し、前記絶縁層の一部をレーザに
よって分解除去し、前記導体パターンに電解ニッケル・
金メッキを施したことを特徴とするＬＥＤアレイヘッド
基板の製造方法。In a method of manufacturing an LED array head substrate, the LED array and an LED array driving IC are fixed to a conductor pattern on the same substrate via a die bonding material, and electrical wiring is performed using wires, An insulating layer that insulates between the IC and a supporting conductor for heat dissipation is formed by processing a resin with alumina short wire as the main component, and the insulating layer and copper foil are stacked on the supporting conductor, which has been blackened, and heated. A conductive pattern is formed on the copper foil by a subtracting method, a part of the insulating layer is decomposed and removed by a laser, and the conductive pattern is coated with electrolytic nickel.
A method for manufacturing an LED array head substrate characterized by gold plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63328001A JPH02172771A (en) | 1988-12-27 | 1988-12-27 | Manufacture of led array head substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63328001A JPH02172771A (en) | 1988-12-27 | 1988-12-27 | Manufacture of led array head substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02172771A true JPH02172771A (en) | 1990-07-04 |
Family
ID=18205398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63328001A Pending JPH02172771A (en) | 1988-12-27 | 1988-12-27 | Manufacture of led array head substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02172771A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001230450A (en) * | 2000-02-21 | 2001-08-24 | Hiroshi Ninomiya | Manufacturing method for surface emitting body |
| US7210957B2 (en) | 2004-04-06 | 2007-05-01 | Lumination Llc | Flexible high-power LED lighting system |
| WO2007139195A1 (en) * | 2006-05-31 | 2007-12-06 | Denki Kagaku Kogyo Kabushiki Kaisha | Led light source unit |
| WO2008093440A1 (en) * | 2007-01-30 | 2008-08-07 | Denki Kagaku Kogyo Kabushiki Kaisha | Led light source unit |
| US7429186B2 (en) | 2004-04-06 | 2008-09-30 | Lumination Llc | Flexible high-power LED lighting system |
| JP2009081194A (en) * | 2007-09-25 | 2009-04-16 | Sanyo Electric Co Ltd | Light emitting module and its manufacturing method |
-
1988
- 1988-12-27 JP JP63328001A patent/JPH02172771A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001230450A (en) * | 2000-02-21 | 2001-08-24 | Hiroshi Ninomiya | Manufacturing method for surface emitting body |
| US7210957B2 (en) | 2004-04-06 | 2007-05-01 | Lumination Llc | Flexible high-power LED lighting system |
| US7429186B2 (en) | 2004-04-06 | 2008-09-30 | Lumination Llc | Flexible high-power LED lighting system |
| US8348469B2 (en) | 2004-04-06 | 2013-01-08 | Ge Lighting Solutions Llc | Flexible high-power LED lighting system |
| WO2007139195A1 (en) * | 2006-05-31 | 2007-12-06 | Denki Kagaku Kogyo Kabushiki Kaisha | Led light source unit |
| JPWO2007139195A1 (en) * | 2006-05-31 | 2009-10-15 | 電気化学工業株式会社 | LED light source unit |
| WO2008093440A1 (en) * | 2007-01-30 | 2008-08-07 | Denki Kagaku Kogyo Kabushiki Kaisha | Led light source unit |
| JP5410098B2 (en) * | 2007-01-30 | 2014-02-05 | 電気化学工業株式会社 | LED light source unit |
| JP2009081194A (en) * | 2007-09-25 | 2009-04-16 | Sanyo Electric Co Ltd | Light emitting module and its manufacturing method |
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