JP2023005240A - Wiring board manufacturing method and intermediate product - Google Patents

Abstract

To provide a wiring board manufacturing method which is capable of standardizing a core board, reducing costs, increasing wiring density, and improving the degree of freedom in wiring design.SOLUTION: A release layer 3a and a seed layer 4a are formed in this order on one surface of a support substrate 3, and a plurality of columnar rising conductor layers are formed on the seed layer 4a so as to be arranged in a matrix at equal intervals. An insulating substrate layer 11 covering the conductor layer 12 is formed on the seed layer 4a, and the release layer 3a is irradiated with an ultraviolet laser or an infrared laser to peel off the support substrate 3, thereby obtaining a core substrate 10 consisting of the insulating substrate layers 11 including the conductor layer 12. Wiring layers 22 electrically connected to predetermined conductor layers 12 are formed on the front and back surfaces of the core substrate 10, respectively, and the wiring layer 22 on the front surface and the wiring layer 22 on the back surface are in one-to-one conduction via the conductor layers 12. Some of the plurality of conductor layers 12 do not participate in conduction between the wiring layer 22 on the front side and the wiring layer 22 on the back side.SELECTED DRAWING: Figure 1

Description

TECHNICAL FIELD The present invention relates to a wiring board used for mounting electronic components such as semiconductor elements (chips), and more particularly to a wiring board having a core board used as a base material, and wiring layers laminated on both sides of the core board. The present invention relates to a method for manufacturing a wiring board having a structure and an intermediate product.

When manufacturing a semiconductor package such as FC-BGA (Flip Chip-Ball Grid Array), in general, a core layer (core substrate) provided as a base material of the package is prepared, and on both sides or one side For example, by a build-up method, the formation of an insulating layer, the formation of a via hole in the insulating layer, and the formation of a conductor pattern (wiring layer) including the inside of the via hole are sequentially repeated to form a multilayer wiring structure, and finally a protective film is formed on the outermost surface. , and the protective film is opened at desired locations to expose part of the conductor pattern (pad). Furthermore, a solder ball or the like as an external connection terminal is joined to the exposed pad.

Such a semiconductor package has a chip component such as a semiconductor element mounted on one surface, and is mounted on a mounting board such as a mother board via external connection terminals provided on the other surface. In other words, the chip component and the mounting board are electrically connected via the semiconductor package. For this reason, through holes are formed in the core substrate, which is used as the base material of the package, as means for electrically conducting between the two surfaces thereof. At both ends (on the surface of the core substrate) of the conductors formed in the through holes, connection pads are provided for facilitating interlayer connection with wiring layers on both sides of the core substrate.

Conventionally, a base material (for example, a double-sided copper-clad laminate for a plastic package) of a predetermined size and thickness is prepared according to the type of package and the function of the chip component to be mounted. After forming through-holes (about 200 μm in diameter) at required locations by mechanical drilling or the like, a conductive pattern is formed inside the through-holes by electroplating or the like in the case of a plastic package.
In other words, a specific core board is prepared for each required package, and drilling (formation of through-holes) and filling (formation of conductors in the through-holes) are performed on the core board. I needed it.

An example of technology related to such conventional technology is described in Patent Document 1. In the structure of the wiring substrate disclosed in Patent Document 1, through-filled vias having the same diameter of 300 μm or less and a pitch of 2 mm or less are formed in a matrix on the core substrate. A plane wiring pattern is formed on the wiring pattern, and each pad portion of the wiring pattern is electrically connected to each corresponding via of the filled via via a connecting via penetrating the insulating layer.
Further, as another technique related to this, there is a wiring board using a core substrate having a large number of through holes as a base, as described in Japanese Patent Application Laid-Open No. 2002-200013. A conductive material is embedded in each through-hole provided in the substrate, and a group of a plurality of through-holes are electrically connected to connection pads on both sides of the core substrate in a one-to-many manner.

JP-A-10-308565 JP 2010-283056 A

As described above, in the conventional wiring board (package), through holes are formed in the core board as a means for electrically connecting the wiring layers on both sides of the core board, and the through holes are connected to both sides of the through holes. It was necessary to form a pad for In forming the through-holes, specific core substrates are prepared one by one according to the type of the package and the functions of the chip components to be mounted, and the core substrate is drilled and filled. had to be processed.

Therefore, it takes a long time to manufacture a core substrate suitable for the package, and especially when a relatively hard substrate such as a glass epoxy substrate is used as the core substrate, it is necessary to make holes in the hard substrate. Therefore, the target core substrate cannot be manufactured efficiently, and the time required for manufacturing the core substrate is prolonged, which increases the cost.
On the other hand, it was necessary to increase the diameter of the connection pads depending on the processing accuracy and alignment accuracy of the through holes with respect to the core substrate, the lamination accuracy of the wiring layers, and the like. For this reason, there is also the problem that the degree of freedom in wiring design is hindered and the wiring density is restricted. In particular, with the demand for further miniaturization of electronic devices, the diameter and arrangement pitch of through-holes have reached their limits with current technology, so the wiring density of the entire wiring board is further restricted. .

The present invention has been created in view of such problems in the prior art, and provides a wiring substrate manufacturing method and an intermediate product capable of reducing costs, increasing wiring density, and improving the degree of freedom in wiring design. is intended to provide

In order to solve the above problems, according to one aspect of the present invention, a separation layer is formed on one surface of a support substrate; a seed layer is formed on the separation layer; a step of forming a plurality of columnar rising conductor layers so as to be arranged in a matrix at equal intervals; A step of forming an insulating base layer having the surface as the surface, and irradiating the peeling layer with an ultraviolet laser or an infrared laser to cause laser ablation, thereby peeling the insulating base layer containing the conductor layer from the supporting substrate. By doing so, a step of obtaining a core substrate composed of an insulating base layer including a conductor layer, and a wiring layer electrically connected to a predetermined conductor layer among a plurality of conductor layers are formed on each of the front and back surfaces of the core substrate. and a step of connecting the wiring layer on the front side and the wiring layer on the back side through the conductor layer in a one-to-one manner, wherein a part of the plurality of conductor layers is connected to the wiring layer on the front side and the wiring layer on the back side. A method for manufacturing a wiring board is provided that does not involve conduction with a wiring layer.

According to another aspect of the present invention, a step of forming a release layer that undergoes plastic deformation due to heat on both the front and back surfaces of a support substrate; forming a seed layer on the release layer; a step of forming a plurality of columnar rising conductor layers on the layer so as to be arranged in a matrix at equal intervals; forming an insulating substrate layer having a surface flush with the portion; a step of obtaining a core substrate composed of an insulating base layer including a layer; a step of conducting one-to-one between the wiring layer and the wiring layer on the back side via the conductor layer, wherein a part of the plurality of conductor layers is electrically connected between the wiring layer on the front side and the wiring layer on the back side. Provided is a method of manufacturing a wiring board that does not involve

Furthermore, according to another aspect of the present invention, it includes an insulating substrate layer, and a plurality of conductor layers penetrating between the front surface and the back surface of the insulating substrate layer and arranged in a matrix at equal intervals. A supporting substrate, a peeling layer formed on at least one surface of the supporting substrate, a seed layer formed on the peeling layer, and a seed layer formed on the seed layer. and a plurality of conductor layers penetrating between the front and back surfaces of the insulating base layer and arranged in a matrix at equal intervals. A product is provided.

According to the wiring board of the present invention, the conductors in the through-holes can be adjusted without preparing specific core boards one by one according to the type of mounting board and the function of the chip component to be mounted, as in the conventional art. The two sides of the core substrate can be easily connected through the .
Also, the wiring density can be improved, and the degree of freedom in wiring design can be increased.

1 is a cross-sectional view showing the configuration of a wiring board (semiconductor package) according to one embodiment of the present invention; FIG. 1 is a cross-sectional view showing a conductive layer of a wiring board according to one embodiment of the present invention; FIG. FIG. 4A is a cross-sectional view showing an example of a manufacturing process of a support for manufacturing a core substrate according to one embodiment of the present invention. FIG. 4 is a plan view showing an arrangement in which a conductor layer is formed above a support substrate; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of the core substrate; This is a continuation of the manufacturing process of the core substrate. FIG. 4 is a cross-sectional view showing an example of a manufacturing process for forming wiring layers on a core substrate; This is a continuation of the manufacturing process for forming the wiring layer on the core substrate. 1 is a cross-sectional view showing an example of a semiconductor device in which a semiconductor element is mounted on a wiring board according to one embodiment of the present invention; FIG.

An embodiment of the present invention will be described below with reference to the drawings.
In addition, in the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimension, the ratio of thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. In addition, it is a matter of course that there are portions with different dimensional relationships and ratios between the drawings.
Further, the embodiments shown below are examples of devices and methods for embodying the technical idea of the present invention. etc. are not specified below. Various modifications can be made to the technical idea of the present invention within the technical scope defined by the claims.

FIG. 1 shows an example of the configuration of a wiring board (semiconductor package) according to one embodiment of the present invention in the form of a cross-sectional view.
A wiring board (package) 30 according to an embodiment of the present invention has a semiconductor element (silicon chip) mounted on one surface as described later, and a motherboard or the like via external connection terminals provided on the other surface. It is intended to be mounted on a mounting board and used.

A wiring board 30 according to one embodiment of the present invention comprises a core board 10 used as a base material thereof, and buildup layers laminated on both sides of the core board 10 by a required number of layers. I have. Each build-up layer consists of an insulating layer 21 formed on the core substrate 10 and a single layer patterned into a desired shape on the insulating layer 21 by filling via holes formed in the required portions of the insulating layer 21. a second wiring layer 22, an insulating layer 23 formed on the insulating layer 21 including the wiring layer 22, and filling via holes formed in the required portions of the insulating layer 23 to form the required wiring layers on the insulating layer 23. and a second wiring layer 24 patterned into a shape, and a protective film formed to cover the surface of the wiring layer 24 by exposing the pad portion defined at a desired location of the wiring layer 24. and an insulating layer (solder resist layer) 25 as a Copper (Cu) is typically used as the material for the wiring layers 22 and 24, and resin such as epoxy resin is typically used as the material for the insulating layers 21, 23, and 25. FIG.

The core substrate 10 used as the base substrate is a member characterizing the present invention, and includes an insulating substrate layer 11 having a required thickness and conductive layers 12 penetrating in the thickness direction thereof at predetermined equal intervals. It has a structure provided in a matrix. The diameter and arrangement intervals of the conductor layers 12 will be described later.
The conductor layer 12 is formed so that both ends in the longitudinal direction are exposed on both sides of the insulating base layer 11 . By forming a plurality of conductor layers 12 in a matrix at regular intervals in this way, it is possible to eliminate the need to prepare specific core substrates according to the types of mounting substrates and the functions of chip parts such as semiconductor elements to be mounted. However, the two surfaces of the core substrate 10 can be easily connected via the conductor layer 12 for general purposes, and the core substrate 10 can be shared.

For the insulating base layer 11, it is desirable to use an organic resin mixed with an inorganic filler such as silica at a high density. Since the coefficient of thermal expansion (CTE) of silica is as small as 0.5 ppm/° C., it contributes to lowering the CTE of the core substrate 10 as a whole. That is, by lowering the CTE of the core substrate 10, which is the base material of the wiring board 30, the CTE of the wiring board 30 as a whole is brought closer to the CTE of the semiconductor element to be mounted. As a result, the stress (thermal stress) that may occur between the chip and the wiring board 30 due to the difference in CTE between the chip and the wiring board 30 when the chip is mounted can be effectively relieved in the core board 10 . In addition to silica, alumina, silicon nitride, aluminum nitride, or the like can be used as the inorganic filler added to the resin. As the organic resin, generally used epoxy resin, polyimide resin, or the like is used. As for the type of resin, both thermosetting resin and photosensitive resin can be used, but in this embodiment, thermosetting epoxy resin is used.
In addition, by using resin mixed with inorganic filler at a high density as the insulating base layer 11, the posture change of the conductor layer 12 is suppressed and the self-supporting state is maintained.

Further, on both surfaces of the core substrate 10, pads are arranged at respective required locations, which are composed of a part of the wiring layer 22 (that is, are formed at the same time when the wiring layer 22 is formed).
As will be described later, the conductor layer 12 is formed by filling a group of rising columnar conductors arranged in a matrix at equal intervals on a support with an insulating resin. The role of the conductor layer 12 is to receive a signal at one end of the conductor layer 12 and transmit it to the other end. That is, in order to electrically connect the wiring layers 22 and 24 on one surface side and the wiring layers 22 and 24 on the other surface side through the core substrate 10, and to electrically connect the front and back surfaces of the wiring substrate 30. play the role of

Further, since the conductor layers 12 are arranged in a matrix at equal intervals, as shown in FIG. There is also a conductor layer (non-conducting conductor layer) 12b that does not participate in electrical connection. As shown in FIG. 2, conductor layers 12b not involved in the electrical connection between the front and back surfaces of the wiring board 30, excluding the conductor layers 12a for electrically connecting the front and back surfaces of the wiring board 30, include wiring layers 22, 24, and preferably connected to the mounting substrate through external connection terminals. By connecting to the mounting substrate, for example, by connecting to the ground, the potential can be controlled and stabilized.

Insulating layers 21 are formed on both surfaces of the core substrate 10 configured as described above. More precisely, after the insulating layers 21 are formed on both sides of the core substrate 10 as will be described later, the via holes formed in the required portions of the insulating layers 21 are filled with the conductive material. The first wiring layer 22 is also formed at the same time when the conductive material is filled. Further, an insulating layer 23, a second wiring layer 24, and an outermost insulating layer (solder resist layer) 25 are sequentially formed on each wiring layer 22, and via holes formed in the outermost insulating layer 25 Solder 44 is formed.

A method of manufacturing the wiring board 30 according to the first embodiment will be described below with reference to FIGS. 3 to 6 showing an example of the manufacturing process.
First, referring to FIGS. 3(a) and 3(b), the process of forming the support 40 for manufacturing the core substrate 10 will be described. First, a release layer 3 a is formed on the support substrate 3 . Although the support substrate 3 is not particularly limited, for example, a heat-resistant resin plate such as a bismaleimide-triazine resin plate, a fiber-reinforced resin plate such as a glass-fiber-reinforced epoxy resin plate, or alkali-free glass can be used. The peeling layer 3a is made of amorphous silicon, black carbon, or an acrylic resin containing a component that foams when heated, and is coated on either side or one side of the support substrate 3 by CVD, sputtering, vapor deposition, spin coating, vacuum lamination, or the like. formed in In FIG. 3, a release layer 3a is formed on both sides of the support substrate 3. As shown in FIG.
Next, a seed layer 4a is formed on the release layer 3a. The seed layer 4a is mainly made of copper and is formed by a sputtering method, a vapor deposition method, a vacuum lamination method, or an electroless plating method. Thus, the support 40 for manufacturing the core substrate 10 is formed.

Next, the process of forming the core substrate 10 will be described with reference to FIGS. 4(a) and 4(b) and FIGS.
First, an etching resist is formed on both surfaces of the support 40 using a patterning material, and openings are formed at desired locations (formation of a resist layer having openings). Each opening is patterned according to the pattern shape of the conductor layer 12 to be formed so that only the pattern portion remains. As a patterning material, a photosensitive dry film (a film having a structure in which a resist material is sandwiched between a polyester cover sheet and a polyethylene separator sheet), or a liquid photoresist (for example, novolac resin, epoxy resin, etc.) can be used. liquid resist) can be used.

For example, when a dry film is used as the patterning material, after the surface of the seed layer 4a is washed, a dry film (from which the separator sheet has been removed) is laminated on the surface by thermocompression bonding, and the dry film is subjected to a predetermined treatment. After the position is exposed to ultraviolet (UV) irradiation and cured, and the cover sheet is peeled off, a predetermined developing solution (developing solution containing an organic solvent in the case of a negative resist, The portion is etched using an alkaline developer) to form a required resist layer (not shown). Similarly, when a liquid photoresist is used, a resist layer (not shown) patterned into a desired shape can be formed through the steps of cleaning the surface, coating the surface with resist, drying, exposing, and developing. can.

In the next step, a conductive layer 12 having a required thickness is formed by electrolytic Cu plating using the seed layer 4a as a power supply layer on both surfaces of the support 40 on which the resist layer has been patterned.
The arrangement of the conductor layers 12 in plan view of the support 40 will be described with reference to FIGS. 4(a) and 4(b).
As shown in FIG. 4A, the support 40 has a plurality of wiring board forming regions, and a large number of wiring boards are formed from one support 40 size.

As shown in FIG. 4B, which is an enlarged view of area A in FIG. 4A, conductor layers 12 are arranged on the seed layer 4a in a matrix at equal intervals. The conductor layer 12 is formed in a matrix at regular intervals over the entire surface of the seed layer 4a. By forming the cores in a matrix at regular intervals over the entire surface, the cores can be generally passed through the conductor layer 12 without preparing a specific core substrate according to the type of the wiring substrate and the functions of the chip components to be mounted. Both sides of the substrate can be easily connected, and the core substrate 10 can be shared. The arrangement interval of the conductor layers 12 is preferably 100 μm or more and 1000 μm or less, and more preferably 200 μm or more and 400 μm or less in consideration of high wiring density and ease of manufacture. In addition, the diameter of the columnar conductor layer 12 is preferably about half the distance between the conductor layers 12, and is 50 μm or more and 500 μm or less. is 100 μm or more and 200 μm or less. It should be noted that the shape of the conductor layer 12 is determined in consideration of the fact that the orientation of the conductor layer 12 changes during molding, which will be described later, when forming the insulating base layer 11, and the aspect ratio of the conductor layer 12, that is, may define the thickness and diameter of the

Next, as shown in FIG. 5A, the resist layer used as the etching resist is removed. When a dry film is used as an etching resist, it can be removed using an alkaline chemical solution such as sodium hydroxide or monoethanolamine. can be removed using acetone, alcohol, or the like. Then, predetermined surface cleaning is performed.

Next, as shown in FIG. 5B, an insulating base layer 11 is formed. The insulating base material layer 11 uses a resin material to which an inorganic filler is added, and is formed by compression molding, transfer molding, or the like. In this embodiment, the insulating base layer 11 is collectively formed on both sides of the support 40, but the conductor layer 12 and the insulating base layer 11 may be formed on each side. The resin material used for forming the insulating base material layer 11 contains an inorganic filler to the extent that the conductive layer 12 can maintain its self-supporting state when the wiring board 30 is formed using this core substrate 10 . It has become. The inorganic filler preferably has a filler diameter of 0.1 μm or more and 10 μm or less, more preferably 0.1 μm or more and 5 μm or less. Moreover, the content of the inorganic filler is preferably 50% or more and 90% or less, more preferably 60% or more and 90% or less.

Next, as shown in FIG. 5C, both surfaces are polished and flattened by mechanical polishing, chemical mechanical polishing (CMP), or the like, and both ends of the conductor layer 12 are exposed on both surfaces of the insulating base layer 11. Next, as shown in FIG. The thickness of the core substrate 10 can be controlled by the polishing amount. The thickness of the core substrate 10 is preferably 100 μm or more and 3000 μm or less, more preferably 400 μm or more and 1000 μm or less, in consideration of the rigidity for forming wiring on each of the front and back surfaces, ease of manufacture, and the like. As a result, a structure in which the conductive layer 12 penetrating through the insulating base layer 11 in the thickness direction is formed as the intermediate product 15 as shown in the drawing.

Next, as shown in FIG. 6A, peeling is performed at the interface between the seed layer 4a and the peeling layer 3a. The peeling method differs depending on the type of the peeling layer 3a. It can be peeled off by causing ablation. When peeling is performed by laser ablation, it is preferable to use non-alkali glass as the support substrate 3 .
On the other hand, as shown in FIG. 6A, when the release layers 3a are formed on both sides of the support substrate 3 and the core substrates 10 are formed on both sides, the separation is performed by thermal history such as heating and cooling. In this case, it is preferable to use a material having a characteristic of causing plastic deformation by heat as the release layer 3a, and to use an organic resin material as the support substrate 3. FIG.

Next, the seed layer 4a adhering to the core substrate 10 is removed to expose the insulating base layer 11. Next, as shown in FIG. The seed layer 4a can be removed by chemical etching using, for example, a hydrogen peroxide solution-sulfuric acid-based etchant. As a result, as shown in FIG. 6B, the core substrate 10 having the structure in which the conductor layer 12 penetrating through the insulating base layer 11 in the thickness direction is provided is produced.

In the next step, as shown in FIG. 7A, insulating layers 21 are formed on both surfaces of the manufactured core substrate 10 respectively. As a material for the insulating layer 21, an epoxy-based resin, a polyimide-based resin, or the like, which is generally used in build-up multilayer wiring boards, is used. As for the type of resin, both thermosetting resin and photosensitive resin can be used, but in this embodiment, thermosetting epoxy resin is used. Moreover, the form of the resin is not limited to a liquid form, and a film-shaped form can also be used. That is, the required insulating layer 21 is formed by coating the core substrate 10 with a thermosetting epoxy resin or laminating a thermosetting epoxy resin film and thermally curing it.

In the next step, as shown in FIG. 7(b), each insulating layer 21 formed on both sides of the core substrate 10 is opened at a desired location by a carbon dioxide gas laser, an excimer laser, or the like, and the core substrate is formed. A via hole 10a reaching 10 is formed. Of all the conductor layers 12, the via holes 10a are formed only in the conductor layers 12 that are present at positions corresponding to the connection terminals of the semiconductor element to be mounted and the mounting board.

In the next step, as shown in FIG. 7C, wiring layers 22 are formed on the insulating layers 21 on both sides of the core substrate 10 so as to fill the via holes formed in the insulating layers 21 respectively. The wiring layer 22 can be formed, for example, as follows.
First, seed layers are formed on both surfaces of the core substrate 10 by sputtering, electroless plating, or the like. For example, a titanium (Ti) conductor layer having a thickness of about 0.1 μm is formed on both surfaces by sputtering, and a copper (Cu) conductor layer having a thickness of about 0.5 μm is further formed thereon by sputtering. , forming a seed layer of a two-layer structure (Ti/Cu). The Ti layer under the seed layer is a metal layer for increasing the adhesion between the insulating layer 21 and the Cu layer. Chromium (Cr) may be used instead of Ti.

Thereafter, an etching resist is formed on both surfaces of the core substrate 10 using a patterning material, and openings are formed at desired locations (formation of a resist layer having openings). Each opening is patterned according to the pattern shape of the wiring layer 22 to be formed so that only the pattern portion remains. Next, a wiring layer having a required thickness is formed according to a pattern defined by a resist by electrolytic Cu plating using the seed layer as a power feeding layer. Thereafter, the wiring layer 22 is formed by removing the resist layer used as the etching resist and removing the seed layer. As a result, the wiring layer 22 including the contact portion filling the via hole and the wiring portion formed on the insulating layer 21 is formed.

Next, as shown in FIG. 8A, the insulating layers 23 are formed on both surfaces of the core substrate 10 on which the wiring layers 22 are formed, in the same procedure as that of the insulating layer 21 . As a material for the insulating layer 23, an epoxy-based resin, a polyimide-based resin, or the like, which is generally used in build-up multilayer wiring boards, is used. As for the type of resin, both thermosetting resin and photosensitive resin can be used, but in this embodiment, thermosetting epoxy resin is used. Moreover, the form of the resin is not limited to a liquid form, and a film-shaped form can also be used. That is, the required insulating layer 23 is formed by coating the core substrate 10 with a thermosetting epoxy resin or laminating a thermosetting epoxy resin film and thermally curing it.

In the next step, the insulation layers 23 formed on both sides of the core substrate 10 are opened at desired locations by a carbon dioxide gas laser, an excimer laser, or the like, in the same procedure as when the openings were formed in the insulation layer 21 . to form After that, by forming the wiring layer 24 in the same procedure as when forming the wiring layer 22, multilayer wiring can be obtained (FIG. 8(b)). In this embodiment, a two-layer wiring board is shown as an example, but the number of layers is not limited, and a desired number of layers can be obtained by repeating this process.

In the final step, on the wiring layers 24 formed on both surfaces of the core substrate 10 and the exposed insulating layers 23, the pad portions defined at desired locations of the respective wiring layers 24 are exposed and the surfaces thereof are exposed. A solder resist layer 25 is formed to cover the . For example, the solder resist layer 25 is formed by applying a photosensitive epoxy resin (solder resist) to the surface and patterning each resin layer into a desired shape (a shape in which the pad portion is exposed). can do.

Each pad (a part of the wiring layer 24) exposed from the opening of each solder resist layer 25 has an electrode terminal of a chip mounted on the wiring board 30, and an electrode terminal for mounting the wiring board 30 on a mother board or the like. Since the external connection terminals (solder balls, metal pins, etc.) to be used are joined, the pads (Cu) are subjected to Ni plating and Au plating in this order as surface treatment. Here, the Ni layer is provided to improve adhesion between the Cu layer and the Au layer and to prevent Cu from diffusing into the Au layer. It is provided to improve contactability when electrode terminals and the like are joined. The above is an example, and surface treatments such as electroless Ni/Pd/Au plating, OSP, electroless tin plating, and electroless Ni/Au plating may be applied.

As a result, the wiring board 30 of the present embodiment is produced as shown in FIG. 8(b). As described above, the wiring board 30 is intended to be used by mounting a semiconductor element on one surface and mounting it on a mounting substrate such as a motherboard through external connection terminals provided on the other surface. there is

FIG. 9 shows an example of the mounting state, showing a state (semiconductor device) in which a semiconductor element 41 (silicon chip) is mounted on the wiring substrate 30. As shown in FIG. In this semiconductor device, the electrode terminals 42 of the semiconductor element 41 are electrically connected to corresponding pads of the wiring layer 24 on the wiring substrate 30 via conductive materials such as solder bumps (flip chip mounting). Furthermore, the gap between the mounted chip 41 and the wiring board 30 is filled with an underfill resin 43 such as a thermosetting epoxy-based resin, which is heat-cured to form a mechanical bond between the chip 41 and the wiring board 30. A good connection is ensured.

On the other hand, solder 44 used as an external connection terminal is joined to the pad of the wiring layer 24 exposed from the solder resist layer 25 on the side opposite to the chip mounting surface. The wiring board 30 is mounted on a motherboard or the like through the solder 44 .
The wiring board 30 may be separated into individual pieces, for example, when the wiring board 30 shown in FIG. 8B is manufactured. It may be done while the device is formed.

As described above, according to the wiring board 30 according to the present embodiment, the conductor layers 12 penetrating the insulating base layer 11 of the core board 10 in the thickness direction thereof are provided at equal intervals. Pads made of a portion of the wiring layer 22 are formed at required locations on both surfaces of the substrate 10 .

As a result, the wiring layer 22 (and the wiring layer 24 connected thereto) formed on one surface side of the core substrate 10 and the wiring layer 22 (and the wiring layer 24 connected thereto) formed on the other surface side are formed. can be electrically connected via a pair of pads opposed to each other on the core substrate 10 and a conductor layer 12 connected thereto. In other words, there is no need to prepare specific core substrates one by one according to the type of package and the functions of chip components to be mounted, as in the conventional art. The two surfaces of the core substrate 10 can be easily connected via the conductor layer 12 formed on the core substrate 10 simply by appropriately changing the size and position of the pads arranged on the core substrate 10 .

Although not shown in FIG. 7, as shown in FIG. 2, the conductor layers 12b that are not involved in the electrical connection between the front and back surfaces of the wiring board 30 are bundled using the wiring layers 22 and 24, and connected to the outside. The potential can be controlled and stabilized by being connected to the mounting board through the connection terminal, which is preferable.
As described above, according to the present embodiment, the core substrate 10 can be shared, so that the manufacturing cost can be reduced.
Further, on both surfaces of the support 40 on which the resist layer is patterned, the conductor layer 12 having a required thickness is formed by electrolytic Cu plating using the seed layer 4a as a power supply layer. Therefore, the conductor layers 12 arranged in a matrix at predetermined intervals can be easily produced, and even when the arrangement intervals and diameters of the conductor layers 12 are short, the conductor layers 12 can be produced with high accuracy.

In particular, in the case of forming a conductor layer by making a hole in the substrate and filling the hole with a conductor as in the conventional method, in the case of forming a plurality of conductor layers with a relatively small diameter at relatively short intervals. are particularly time consuming and potentially costly, and may be limited in spacing and diameter. However, as described above, after producing the columnar conductor layer 12, by producing the insulating base layer 11 by molding using a resin material containing a filler, when the arrangement interval and diameter are relatively short, However, the conductor layer 12 can be manufactured easily and with high accuracy. In addition, since the arrangement interval and diameter of the conductor layers 12 can be shortened, the wiring density can be improved, and the degree of freedom in wiring design can be increased.

In addition, when the insulating base material layer 11 is produced using a resin material, the conductor layer 12 may not be able to stand on its own. However, the insulating base material layer 11 is produced using a resin material containing an inorganic filler. Therefore, the resin material containing the inorganic filler is in a state equivalent to assisting the self-standing of the conductor layer 12, and the posture change of the conductor layer 12 can be suppressed. Continuity can be maintained.

The wiring board 30 formed in this manner may be shipped in the form of an intermediate product in which wiring is formed in accordance with the semiconductor element to be mounted and the mounting board, and furthermore, solder balls or the like are connected to the pads. You may ship in the state of the intermediate product which formed the terminal. Further, for example, as shown in FIG. 5C, the intermediate product 15 in which the insulating base layer 11 is formed on the surface of the support 40 and the conductor layer 12 is exposed on the surface of the insulating base layer 11 , and the wiring layer may be formed after cutting out the core substrate 10 at the shipping destination. Alternatively, the core substrate 10 shown in FIG. The wiring layer may be formed at the shipping destination.

The above-described embodiment is an example of the present invention, and the present invention is not limited to the above-described embodiment. It goes without saying that the specific details of the structure and the like can be changed as appropriate within a range not departing from the above.

3 Support substrate 3a Separation layer 4a Seed layer 10 Core substrate 11 Insulating base layer,
Reference Signs List 12 Conductor layer 12a Conductor layer 12b for electrically connecting the front and back surfaces of the wiring board Conductor layers 21, 23 not involved in electrical connection between the front and back surfaces of the wiring board 21, 23 Insulating layers 22, 24 Wiring layers 25... Solder resist layer (insulating layer),
DESCRIPTION OF SYMBOLS 30... Wiring board 40... Support body 41... Semiconductor element 42... Electrode terminal 43... Underfill resin 44... Solder

Claims (7)

forming a release layer on one surface of the support substrate;
forming a seed layer on the release layer;
a step of forming a plurality of columnar rising conductor layers on the seed layer so as to be arranged in a matrix at equal intervals;
forming, on the seed layer, an insulating base layer covering the conductor layer and having a surface flush with the end of the conductor layer on the side opposite to the support substrate;
The insulating substrate including the conductor layer by irradiating the release layer with an ultraviolet laser or an infrared laser to cause laser ablation and peeling the insulating substrate layer including the conductor layer from the supporting substrate. obtaining a core substrate consisting of layers;
A wiring layer that conducts to a predetermined conductor layer among the plurality of conductor layers is formed on each of the front surface and the back surface of the core substrate, and the wiring layer on the front surface side and the wiring layer on the back surface side are connected to the conductor layer. and conducting one-to-one through
A method of manufacturing a wiring board, wherein a part of the plurality of conductor layers does not participate in electrical conduction between the wiring layer on the front surface side and the wiring layer on the back surface side. 2. The method of manufacturing a wiring board according to claim 1, wherein the supporting substrate is made of alkali-free glass. a step of forming a release layer that undergoes plastic deformation due to heat on both the front and back surfaces of the support substrate;
forming a seed layer on the release layer;
a step of forming a plurality of columnar rising conductor layers on the seed layer so as to be arranged in a matrix at equal intervals;
forming, on the seed layer, an insulating base layer covering the conductor layer and having a surface flush with the end of the conductor layer on the side opposite to the support substrate;
obtaining a core substrate composed of the insulating base layer including the conductor layer by plastically deforming the release layer with heat to separate the insulating base layer including the conductor layer from the support substrate; When,
A wiring layer that conducts to a predetermined conductor layer among the plurality of conductor layers is formed on each of the front surface and the back surface of the core substrate, and the wiring layer on the front surface side and the wiring layer on the back surface side are connected to the conductor layer. and conducting one-to-one through
A method of manufacturing a wiring board, wherein a part of the plurality of conductor layers does not participate in electrical conduction between the wiring layer on the front surface side and the wiring layer on the back surface side. 4. The method of manufacturing a wiring board according to claim 3, wherein the supporting substrate is made of an organic resin material. 5. The method of manufacturing a wiring board according to claim 1, wherein the insulating base layer is made of a resin material containing an inorganic filler. 6. The method of manufacturing a wiring board according to claim 1, further comprising exposing the conductor layer by polishing after the step of forming the insulating base layer. Produced in the manufacturing process of a wiring board having a core substrate including an insulating base layer and a plurality of conductor layers penetrating between the front and back surfaces of the insulating base layer and arranged in a matrix at equal intervals. is,
a support substrate;
a release layer formed on at least one surface of the supporting substrate;
a seed layer formed on the release layer;
the insulating base layer made of a resin material containing an inorganic filler formed on the seed layer;
a plurality of the conductor layers penetrating between the front surface and the back surface of the insulating base layer and arranged in a matrix at equal intervals;
An intermediate product characterized by comprising

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