JPH02170591A - Ceramic wiring board - Google Patents

Abstract

PURPOSE:To reduce a parasitic capacitance between viaholes or the viahole and the conductor on a dielectric and cross talk noises by a method wherein a dielectric whose dielectric constant is lower than that of a capacitor layer is provided around the conductor of the viahole which penetrates through the capacitor layer. CONSTITUTION:Both the side faces of a capacitor layer dielectric 1a are coated with a capacitor layer 2a, which is filled into a viahole guide hole 3a and dried up. Furthermore, a copper film is formed, which is etched to be formed into a conductor wiring 5a. A viahole 6a is bored by a drill, and a conductor 7a formed through a viahole plating of copper or like is formed on the inner wall of the viahole 6a. And, a dielectric 4a whose dielectric constant is lower than that of the capacitor layer 2a is arranged around the conductor of the viahole 6a. By this setup, a parasitic capacitance between the viahole 6a and the conductor 7a on the dielectric 4a becomes small to enable cross talk noises to decrease.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a ceramic wiring board, and in particular, a ceramic wiring board that has a small stray capacitance between a via hole or a conductor on a dielectric material, and has low crosstalk noise. Regarding wiring boards.

[Conventional technology]

Conventionally, as shown in FIG. 3, in the via hole 6C of this type of ceramic wiring board, the conductor 7C is connected to the capacitor layer dielectric 1c.
It was formed by penetrating the wiring layer dielectric 4c.

[Problem to be solved by the invention]

In the conventional via holes described above, when the relative dielectric constant of the dielectric material is large, the capacitance of the capacitor formed between the via holes or between the via hole and the conductor on the dielectric material becomes large, resulting in an increase in stray capacitance and cross-contamination. This has the disadvantage of increasing talk noise.

An object of the present invention is to provide a ceramic wiring board with low stray capacitance between via holes or between a via hole and a conductor on a dielectric material, and with low crosstalk noise.

[Means to solve the problem]

The present invention provides a ceramic wiring board incorporating a capacitor layer, in which a dielectric material having a lower dielectric constant than the capacitor layer is disposed around a conductor of a via hole penetrating the capacitor layer.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a main part of a first embodiment of the present invention.

In the first embodiment, as shown in FIG. 1, the capacitor layer dielectric 1a is made by adding lead composite perovskite ceramic powder with an average particle size of 1 μm and a relative permittivity of 12.000 to an organic solvent and polyvinyl butyral. A via hole guide hole 3a with a diameter of 1.5 mm was formed on the ceramic green sheet with a thickness of 1.5 mm, which was mixed using a doctor blade and dried, and a conductive paste of silver and palladium containing 20% palladium was applied to the capacitor. The electrode 2a was formed by printing, the binder was removed at 500°C for 100 hours, and then baked at 900°C for 3 hours.

The wiring layer dielectric 4a has a thickness of 0.8 mm and a relative permittivity of 3.2.
The polyimide resin is coated on both sides of the capacitor layer dielectric 1a using a spin coater, filled in the via hole guide hole 3a, and then dried.

Furthermore, a copper film is formed on the surface by electroless copper plating and electrolytic copper plating, and conductor wiring 5 is formed by etching.
Let it be a. The via hole 6a is formed by a cemented carbide drill having a diameter of 0.4 mm, and a conductor 7a made of via hole plating of copper or the like is formed on the inner wall of the via hole 6a.

Table 1 shows the measurement results of the stray capacitance of the conventional via hole and the via hole of this embodiment, and the crosstalk noise of the via hole with a spacing of 2.54 am.

Table 1 FIG. 2 is a sectional view of a main part of a second embodiment of the present invention.

In the second embodiment, as shown in FIG. 2, the capacitor layer dielectric 1b is made of lead composite perovskite ceramic with a thickness of 0.3mm, and the wiring layer dielectric 4b is made of alumina and porcelain with a thickness of 0.5mm. It is an alumina glass ceramic mixed with acid glass in a ratio of 1:1, and the capacitor electrode 2b and the conductor wiring 5b are formed by printing a silver/palladium conductor base in a green sheet state, and the temperature is 10
Diameter 2.5 after thermocompression bonding at 0℃ and pressure 50kg/c+F
A via hole guide hole 3b of mm in diameter is punched out using a cemented carbide punch and die, and then the binder is removed and fired.

Separately, a copper wire with a diameter of 0.4 mm was used as a center conductor 8, and a silicone resin with a diameter of 2.0 mm was coated around the copper wire to form a coated dielectric material 9, and the coated copper wire was cut into a length of 1.3 mm. Electrodes 10 are formed on both end faces by electroless and electrolytic copper plating. The via hole guide hole 3 is made of this material.
b, and connect the electrode 10 and the wiring conductor 5b with the solder 11 by soldering to obtain a via hole.

Table 2 shows the measurement results of the stray capacitance of the conventional via hole and the via hole of this embodiment and the crosstalk noise at a spacing of 2.54 mm.

Table 2 [Effects of the Invention] As explained above, the present invention has the advantage that by arranging a dielectric material having a lower dielectric constant than the capacitor layer around the conductor of the via hole that penetrates the capacitor layer, the via holes can be connected to each other or This has the effect of reducing stray capacitance between the hole and the conductor on the dielectric, and reducing crosstalk noise.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a first embodiment of the invention, FIG. 2 is a sectional view of a main part of a second embodiment of the invention, and FIG. 3 is an example of a via hole in a conventional ceramic wiring board. FIG. la, lb, lc...capacitor layer dielectric, 2 a. 2b, 2c... Capacitor electrode, 3a, 3b... Via hole guide hole, 4a, 4b, 4c... Wiring layer dielectric, 5a, 5b, "IC-conductor wiring, 6a, 6c...
・Via hole, 7a, 7c...Conductor, 8...Center conductor, 9...Coating dielectric, 10...Electrode, 11...
・Solder. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] In ceramic wiring boards with built-in capacitor layers,
A ceramic wiring board characterized in that a dielectric material having a lower dielectric constant than the capacitor layer is disposed around a conductor of a via hole penetrating the capacitor layer.