JPH02170456A - Mounting of integrated circuit structure body - Google Patents
Mounting of integrated circuit structure bodyInfo
- Publication number
- JPH02170456A JPH02170456A JP32556488A JP32556488A JPH02170456A JP H02170456 A JPH02170456 A JP H02170456A JP 32556488 A JP32556488 A JP 32556488A JP 32556488 A JP32556488 A JP 32556488A JP H02170456 A JPH02170456 A JP H02170456A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit structure
- terminals
- substrate
- signal terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000011347 resin Substances 0.000 claims abstract description 8
- 229920005989 resin Polymers 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 238000005452 bending Methods 0.000 description 5
- 230000005489 elastic deformation Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000011093 chipboard Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の属する分野］
本発明は集積回路構体、特に集積回路チップと外部回路
とを接続する信号端子との新規な構造を有した集積回路
構体に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an integrated circuit structure, and more particularly to an integrated circuit structure having a novel structure of signal terminals connecting an integrated circuit chip and an external circuit.
更に本発明は、前記新規な集積回路構体を電気機器に組
み込む新規な集積回路構体の実装方法に関する。Furthermore, the present invention relates to a novel integrated circuit assembly mounting method for incorporating the novel integrated circuit assembly into electrical equipment.
［従来技術］
基板上に微細回路網を形成し基板の端部に信号０１１１
子を固定し、回路網と信号端子をボンディングし、全体
を樹脂材料で成形固化した所謂集積回路構体は、例えば
第６図Ａに示す。[Prior art] A fine circuit network is formed on a substrate and a signal 0111 is attached to the edge of the substrate.
A so-called integrated circuit structure, in which the terminals are fixed, the circuit network and signal terminals are bonded, and the entire structure is molded and solidified with a resin material, is shown, for example, in FIG. 6A.
［従来技術の問題点］
前述従来の集積回路構体の構造の一例を第６図Ｂに示す
、従来の集積回路構体の信号端子１００は第６図Ｂ、Ｃ
に示すように外装成形網ｆ＠ ｌ Ｏ２の側面方向に突
出し、その先端は外部回路基板１０４の回路パターンと
接触するために折曲している。[Problems with the Prior Art] An example of the structure of the conventional integrated circuit structure described above is shown in FIG. 6B.The signal terminal 100 of the conventional integrated circuit structure is shown in FIGS.
As shown in the figure, the outer molding net f@l O2 protrudes in the side direction, and its tip is bent in order to contact the circuit pattern of the external circuit board 104.
このような積回路構体は信号端子の数が多い場合、各信
号端子の折曲部の足論えをぎちんとしないと、一部の折
曲部が外部回路基板の回路パターンとの半田接続の不良
を生じる。又、集積回路構体の側面から信号端子を突出
すると第６図Ｃに示１−ように集積回路構体の外装部分
の寸法Ｌｌに対し信号端子の突出部分の寸法Ｌ３ ＋Ｌ
ｓ ＝２Ｌｓの寸法の長さを必要とする。それ故前記集
積回路構体を外部回路基板に実装する場合に、外部回路
基板の占有面積が大きくなり該外部回路基板を電気機器
に組み込むときに、電気機器の回路実装スペースも機器
設計項目の中の重要項目となる。When such a product circuit structure has a large number of signal terminals, if the bending parts of each signal terminal are not carefully considered, some of the bending parts may cause solder connections with the circuit pattern on the external circuit board. Causes defects. Furthermore, when a signal terminal is protruded from the side surface of the integrated circuit structure, as shown in FIG.
Requires a length of dimension s = 2Ls. Therefore, when the integrated circuit structure is mounted on an external circuit board, the area occupied by the external circuit board increases, and when the external circuit board is incorporated into an electrical device, the circuit mounting space of the electrical device is also considered as a device design item. This is an important item.
［問題点解決のための手段］
本発明は集積回路構体の信号端子の先端の端子部を集積
回路構体の外装部の樹脂成形部の平面部に表出するよう
に前記信号端子を構成した。[Means for Solving the Problems] In the present invention, the signal terminal of the integrated circuit structure is configured such that the terminal portion at the tip thereof is exposed on the flat surface of the resin molded portion of the exterior portion of the integrated circuit structure.
［発明の作用］
外部回路基板と接続する信号端子の端子部を集積回路構
体の外装部を形成する樹脂成形部の平面部に表出するこ
とにより、該平面部に表出した端子部と外部回路基板の
回路パターンのランド部を位置合わせして半田接続する
。又、８！１を回路構体の平面部に表出した端子部と外
部回路基板のランド部との間に導電性の粘弾性部材を介
挿し、集積回路基板と粘弾性部材及び外部回路基板の３
者を機器の実装部に設けた凹部に圧入固定する。[Operation of the invention] By exposing the terminal portion of the signal terminal to be connected to the external circuit board on the flat surface of the resin molded portion forming the exterior portion of the integrated circuit structure, the terminal portion exposed on the flat surface and the outside can be exposed. Align and solder the land portions of the circuit pattern on the circuit board. In addition, a conductive viscoelastic member is inserted between the terminal portion of 8!1 exposed on the flat surface of the circuit structure and the land portion of the external circuit board, so that the integrated circuit board, the viscoelastic member, and the external circuit board are connected to each other. 3
Press-fit and fix the device into the recess provided in the mounting section of the device.
〔実施例の説明］ 第１図Ａ−８は本発明の第１の実施例を示す。[Explanation of Examples] FIG. 1A-8 shows a first embodiment of the invention.
図において、！は集積回路のチップ、２は保持基板、４
は保持基板２上に集積回路チップ１を固定する部材で、
ある、６．８は前記保持基板２の側端部２Ａ・２Ｂに配
置した信号端子であり、１０−１０は信号端子６・８と
集積回路チップ１を接続するボンディングワイヤーを示
す。In the figure! is an integrated circuit chip, 2 is a holding substrate, 4 is
is a member for fixing the integrated circuit chip 1 on the holding substrate 2;
Reference numerals 6 and 8 indicate signal terminals arranged at the side edges 2A and 2B of the holding substrate 2, and 10-10 indicate bonding wires that connect the signal terminals 6 and 8 to the integrated circuit chip 1.
前記信号端子６・８はその一端側６Ａ・８Ａは前記保持
基板２の上面に圧着し、圧着部から保持基板２の側面に
沿って折れ曲げ、更に保持基板２の側面から裏面に沿っ
て折り曲げ、そして４８号端子の他端側６Ｂ・８Ｂは前
記保持基板の裏面側に折り曲げられたところから１８０
°反転して折り曲げられている。１２は＆積回路構体を
構成する前記の集積回路チップト保持基板２・信号端子
６・８及びボンディングワイヤ１０−１０を固定する外
装部材であり、該外装部材１０は前述の各構成部材を樹
脂材料にて成形固定する。One end sides 6A and 8A of the signal terminals 6 and 8 are crimped to the upper surface of the holding board 2, bent from the crimped part along the side surface of the holding board 2, and further bent from the side surface to the back surface of the holding board 2. , and the other end sides 6B and 8B of the No. 48 terminal are 180 degrees from the point where they are bent toward the back side of the holding board.
°Inverted and folded. Reference numeral 12 denotes an exterior member for fixing the integrated circuit chip holding substrate 2, signal terminals 6 and 8, and bonding wires 10-10 constituting the integrated circuit structure, and the exterior member 10 is made of a resin material. Molding and fixing.
第２図Ａ−Ｆは前記第１図Ａ−Ｂに示した集積回路構体
の製造プロセスを説明する図である。FIGS. 2A to 2F are diagrams illustrating the manufacturing process of the integrated circuit structure shown in FIGS. 1A to 1B.
第２図Ａは信号端子の製造プロセスを示し、図において
、１４は信号端子を形成する長尺材であり、該長尺材４
は不図示のプレス工程に送られて符号１４Ｐで示す部分
が扛・ち抜かれ、打ち抜かれた１４Ｐで挟さまれた残余
部分１４Ａは後に信号端子となる。中央部分の１４Ｂは
リードフレームであり、アーム１４Ｃ・１４Ｃ・・・で
支えられている。FIG. 2A shows the manufacturing process of the signal terminal, and in the figure, 14 is a long material forming the signal terminal, and the long material 4
is sent to a press step (not shown), and a portion indicated by reference numeral 14P is punched out, and the remaining portion 14A sandwiched between the punched parts 14P will later become a signal terminal. 14B in the center is a lead frame, which is supported by arms 14C, 14C, . . . .
次に前記第２図Ａに示すプレス工程を経た長尺材１４は
打ち抜いた長尺材の中央のリードフレーム１４Ｂ上に前
記保持基板２を載置して該保持基板２上にｆｉｉｆ記残
余部分１４Ａ・・・、１４Ｂ・・・を固着する。Next, the long material 14 that has undergone the pressing process shown in FIG. 14A..., 14B... are fixed.
この保持基板２をリードフレーム１４Ｂ上に載置する工
程の前に前記打ち抜かれた前記残余部分＋４Ａ・１４Ａ
・・・、１４Ｂ−１４Ｂ・・・の斜線部分には銀メツキ
処理する。The remaining parts +4A and 14A punched out before the step of placing this holding board 2 on the lead frame 14B.
..., 14B-14B... are silver-plated.
次に第２図Ｂに示すＸｌ Ｘｌ、Ｘｌ Ｘｌの線に
沿って信号端子部分を長尺材１４から切断して分離する
。Next, the signal terminal portion is cut and separated from the long material 14 along the lines Xl Xl and Xl Xl shown in FIG. 2B.
長尺材１４から信号端子部分を打ち抜くと保持基板２の
上に第２図Ｃに示すように信号端子１４Ａ・１４Ａ・・
・ １４Ｂ−１４８・・・が点線で示すように真直ぐに
伸びた状態で固着される。真直ぐに伸びた信号端子を保
持基板２の側面に沿って実線のように折り曲げる。更に
信号端子１４Ａ・・・、１４Ｂ・・・の自由端側を線ｙ
１＊ ’ｊｚに沿って各々の信号端子を第２図りに示す
ように折り曲げ、更に、保持基板２の側面辷沿って伸び
ている信号端子を該保持基板２の裏面に沿うように折り
曲げる（第２図Ｅ）、最後に信号端子、の自由端側を１
８０°反対方向に折り返１°（第２図Ｆ）。When signal terminal portions are punched out from the long material 14, signal terminals 14A, 14A, etc. are placed on the holding board 2 as shown in FIG. 2C.
- 14B-148... is fixed in a straight extended state as shown by the dotted line. The straight signal terminal is bent along the side surface of the holding board 2 as shown by the solid line. Furthermore, the free end sides of the signal terminals 14A..., 14B...
1*'jz as shown in the second diagram, and then bend the signal terminals extending along the side surfaces of the holding board 2 along the back surface of the holding board 2 ( 2 E), and finally the free end side of the signal terminal is 1
Turn 80° and turn 1° in the opposite direction (Figure 2 F).
以上のように信号端子を折曲した後に、前述リードフレ
ーム１４Ｂの上に別に用意した集積回路チップ宣を固定
部材４にて固定し、該集積回路チップ１の不図示の入出
力信号端と前記保持基板２に固定した信号端子部分６Ａ
・６Ａ・・・、８Ａ・８Ａ・・・とをワイヤにてボンデ
ィングして接続する。After bending the signal terminals as described above, a separately prepared integrated circuit chip board is fixed on the lead frame 14B using the fixing member 4, and the input/output signal ends (not shown) of the integrated circuit chip 1 and the Signal terminal portion 6A fixed to holding board 2
・Connect 6A..., 8A, 8A... with wire by bonding.
その後、成形工程に送り樹脂材料で前述の保持基板２・
集積回路チップト信号端子６・６・・・８・８・・・を
埋設して固定する。After that, the above-mentioned holding substrate 2 and the resin material are sent to a molding process.
The integrated circuit chip signal terminals 6, 6, 8, 8, . . . are embedded and fixed.
上述の樹脂材料による外装部１２の成形の際に信号端子
の折曲した自由端部分６Ｂ・６Ｂ・・・８Ｂ・８Ｂ・・
・の外向き平面部分は外装部１２の下手面と同一平面上
に位置するように成形する。Free end portions 6B, 6B, . . . 8B, 8B, .
The outward plane portion of * is formed so as to be located on the same plane as the lower surface of the exterior part 12.
以上のプロセスにより第１図Ａに示す集積回路構体を製
造する。第３図は本発明に係る第１図Ａに示した集積回
路構体の実装方法の例を示す。By the above process, the integrated circuit structure shown in FIG. 1A is manufactured. FIG. 3 shows an example of a method of mounting the integrated circuit structure shown in FIG. 1A according to the present invention.
図において＋６は電気機器の不図示本体部の一部分を示
し、該本体部には回路実装用の凹部１６Ａを形成する。In the figure, +6 indicates a part of the main body (not shown) of the electric device, and a recess 16A for circuit mounting is formed in the main body.
１８は一部を断面で示した前述の集積回路構体である。Reference numeral 18 designates the aforementioned integrated circuit structure, a portion of which is shown in cross section.
１０４は外部回路基板を示し該外部回路基板１０４の上
面には不図示の回路パターンが形成され、該回路パター
ンには回路素子を電気接続１−るためのランド部（不図
示）を設ける。Reference numeral 104 denotes an external circuit board, and a circuit pattern (not shown) is formed on the upper surface of the external circuit board 104, and a land portion (not shown) for electrically connecting circuit elements is provided on the circuit pattern.
まず、前記集積回路構体の外装部表面に表出している信
号端子部６Ｂ・６Ｂ・・・、８Ｂ・８Ｂ・・・と外部回
路基板上の前記ランド部の間に導電性を有する粘弾性部
材２０・２０・・・を介挿する。前記回路実装用の凹部
１８Ａの高さ寸法Ｈは、集積回路構体１８・粘弾性部材
２０・外部回路基板１０４を１１を層した厚さより小さ
く形成する。集積回路構体１８と粘弾性部材２０・２０
・・・及び外部回路基板１０４を積層した前記凹部１６
Ａに圧入することにより粘弾性部材２０・２０は前述寸
法Ｈ＝ｈになるように厚さ方向の弾性変形を生じ、この
弾性変形を生じるための！＆積回路構体１８と外部回路
基板１０４の圧接力の反発力が前記凹部の周壁に作用し
これにより集積回路構体１８と外部回路基板１０４は前
記凹部内に保持される。前記集積回路構体の信号端子部
６Ｂ・６Ｂ・・・８Ｂ・８Ｂ・・・と前記外部回路基板
１０４の前記ランド部との電気的接続は粘弾性部材２０
・２ｏ・・・の導電性によって行なわれる。First, a viscoelastic member having conductivity is provided between the signal terminal portions 6B, 6B, . . . , 8B, 8B, . . . exposed on the surface of the exterior portion of the integrated circuit structure and the land portion on the external circuit board. Insert 20.20... The height dimension H of the recess 18A for circuit mounting is formed to be smaller than the thickness of the integrated circuit structure 18, the viscoelastic member 20, and the external circuit board 104 layered together. Integrated circuit structure 18 and viscoelastic members 20, 20
. . . and the recess 16 on which the external circuit board 104 is laminated.
By press-fitting into A, the viscoelastic members 20, 20 cause elastic deformation in the thickness direction so that the above-mentioned dimension H=h, and in order to cause this elastic deformation! & The repulsive force of the pressure contact force between the integrated circuit assembly 18 and the external circuit board 104 acts on the peripheral wall of the recess, thereby holding the integrated circuit assembly 18 and the external circuit board 104 within the recess. Electrical connections between the signal terminal portions 6B, 6B, . . . , 8B, 8B, .
・This is done by the conductivity of 2o...
第４図は本発明に係る集積回路構体の他の実施例を示す
０本実施例は信号端子６Ｂ’ ・８Ｂ’の構成が前記
第１図Ａの構成と異なる６本実施例・の信号端子６Ｂ’
、８Ｂ’は外装部１２の下手面より外側に突出１−る
ように折り曲げられている。FIG. 4 shows another embodiment of the integrated circuit structure according to the present invention. In this embodiment, the configuration of the signal terminals 6B' and 8B' is different from that in FIG. 1A. 6B'
, 8B' are bent so as to protrude outward from the lower surface of the exterior portion 12.
外装部１２の下手面よりの突出部は突出位置ｐ、から自
由端側に向かって折曲角θを有し、自由端側に外力を掛
けたときに前記Ｐ、を支点にして反り返るバネ性を有す
るようにする。The protruding part from the lower surface of the exterior part 12 has a bending angle θ from the protruding position P toward the free end side, and has a spring property that bends around P as a fulcrum when an external force is applied to the free end side. to have.
本実施例の他の構成は前記第１図Ａに示した構成と同様
であり製造プロセスも同様であるので説明を略く。The other configuration of this embodiment is the same as the configuration shown in FIG. 1A, and the manufacturing process is also the same, so the explanation will be omitted.
第４図に示した集積回路構体の実装方法は前記第３図に
示した実装方法と同様である。The method of mounting the integrated circuit structure shown in FIG. 4 is the same as that shown in FIG. 3 above.
即ち、信号端子部６Ｂ’ ・６Ｂ’・・・、８Ｂ。That is, the signal terminal portions 6B', 6B'..., 8B.
８Ｂ’・・・と外部回路基板１０４のランド部を重ね・
〔位置合わせし、該信号端子部とランド部の間に導電＋
’ｔの粘弾性部材を介挿して機器に設けた凹部に圧入す
る。圧入操作によって前記信号端子の突出部６Ｂ’・・
・、８Ｂ°・・・は前記のバネ性が働いて集積回路構体
と外部回路基板を前記凹部の周壁に押圧力が作用するこ
とにより、前述の信号端子部とランド部の電気接続とと
もに集積回路構体と外部回路基板の固定が行なわれる。8B'... overlap the land part of the external circuit board 104.
[Align the position and make sure there is conductivity between the signal terminal part and the land part.]
The viscoelastic member 't is inserted and press-fitted into the recess provided in the device. By press-fitting the signal terminal protrusion 6B'...
, 8B°..., the above-mentioned spring properties act to press the integrated circuit structure and the external circuit board against the circumferential wall of the recess, thereby forming the electrical connection between the signal terminal part and the land part and the integrated circuit. The structure and the external circuit board are fixed.
第５図は本発明の他の実施例の集積回路構体と該集積回
路構体の実装方法を示す。FIG. 5 shows an integrated circuit structure according to another embodiment of the present invention and a method of mounting the integrated circuit structure.
本実施例に示す集積回路構体は信号端子の外部接続部を
外装部の上・下の両表面に表出するように構成する。The integrated circuit structure shown in this embodiment is configured so that the external connection portion of the signal terminal is exposed on both the upper and lower surfaces of the exterior part.
第５図において集積回路チップト保持基板２・１８号端
子６・８及びボンディングワイヤ１０・１０の構成は前
記第１図Ａ−Ｂの構成と同様である。そして本実施例の
集積回路構体は外装部１２の上表面にも信号端子２２・
２４（不図示）を設ける。In FIG. 5, the configurations of the integrated circuit chip holding substrate 2, No. 18 terminals 6 and 8, and bonding wires 10 and 10 are the same as those in FIGS. 1A and 1B. The integrated circuit structure of this embodiment also has signal terminals 22 and
24 (not shown) is provided.
つまり、保持基板２の両側面に配置した信号端子は外装
部の下表面側と上表面側に交互に折曲して、上・下に分
板するように下表面と上表面に配置される。In other words, the signal terminals arranged on both sides of the holding board 2 are bent alternately to the lower and upper surfaces of the exterior part, and are arranged on the lower and upper surfaces so as to be divided into upper and lower parts. .
集積回路の集積密度が向上し回路チップの入出力信号の
数が増えれば信号端子の数の増加が必要となる。As the integration density of integrated circuits increases and the number of input/output signals on a circuit chip increases, the number of signal terminals will need to increase.
本実施例はこの要求に応じることができる。This embodiment can meet this requirement.
上述のように外装部の上・下の両表面に信号端子の外部
接続部を備えた集積回路構体の実装方法は第５図に示さ
れる。A method of mounting an integrated circuit structure having external connection portions for signal terminals on both the upper and lower surfaces of the exterior portion as described above is shown in FIG.
１１０はフレキシブル回路基板を示し、該基板上には回
路パターンと回路素子を接続するためのランド部が設け
られている。Reference numeral 110 indicates a flexible circuit board, and land portions for connecting circuit patterns and circuit elements are provided on the board.
フレキシブル回路基板１１０は図に示すように集積回路
構体を包むように略断面Ｕ字形状に折り込み可能であっ
て折り込んで前記集積回路構体の」二・下表面の１８号
端子の前記外部接続部と対向する位置に前記ランド部（
不図示）が位置１°るように形成する。上・下のフレキ
シブル回路基板のランド部と集積回路構体の外部接続部
の間にそれぞれ導電に１を有する粘弾性部材２０・２０
・・・２６・２６・・・を介挿して、図に示すように機
器に設けた凹部１６Ａに圧入する。前記の圧入操作によ
り粘弾性部材２０・２６の弾性変形を生じ前述のように
集積回路構体とフレキシブル回路基板の固定と、前記外
部接続部と前記ランド部間の電気接続が行なわれる。As shown in the figure, the flexible circuit board 110 can be folded into a substantially U-shaped cross section so as to wrap around the integrated circuit structure, and is folded to face the external connection portion of the No. 18 terminal on the lower surface of the integrated circuit structure. Place the land portion (
(not shown) is formed so that the position is 1°. Viscoelastic members 20 and 20 having conductivity of 1 between the land portions of the upper and lower flexible circuit boards and the external connection portions of the integrated circuit structure, respectively.
...26, 26... are inserted and press-fitted into the recess 16A provided in the device as shown in the figure. The press-fitting operation causes elastic deformation of the viscoelastic members 20 and 26, thereby fixing the integrated circuit assembly and the flexible circuit board and establishing electrical connection between the external connection portion and the land portion as described above.
［発明の効果］
以上のように本発明は集積回路構体の信号端子の外部接
続部６Ｂ・８Ｂ、を回路構体の外装部の平面上に表出す
るように構成したことにより該集積回路構体と電気接続
する外部回路基板の大さぎを従来に比して小さくするこ
とがでミ、これにより回路の実装に要するスペースを小
さくできた。[Effects of the Invention] As described above, the present invention has a structure in which the external connection portions 6B and 8B of the signal terminals of the integrated circuit structure are exposed on the plane of the exterior part of the circuit structure, thereby improving the integrated circuit structure. The size of the external circuit board to which electrical connections are made can be made smaller than in the past, thereby reducing the space required to mount the circuit.
又、信号端子の外部接続部６Ｂ・８Ｂを集積回路構体の
外装部！２の平面上に表出することにより集積回路構体
と外部回路基板との間に導電性の粘弾性部材を介挿して
機器に設けた凹部に圧入することにより、集積回路構体
と外部回路基板との電気接続と固定を一緒に行なうこと
ができ、半田付は作業や外部回路基板の機器へのビス締
め固定に要する部品及び作業時間の大１１】な削減を図
ることができた。Also, the external connection parts 6B and 8B of the signal terminals are the exterior part of the integrated circuit structure! By inserting a conductive viscoelastic member between the integrated circuit structure and the external circuit board and press-fitting it into the recess provided in the device, the integrated circuit structure and the external circuit board can be connected to each other. Electrical connection and fixing can be performed at the same time, and the number of parts and work time required for soldering and fixing external circuit boards to equipment with screws can be greatly reduced.
第１図Ａ−８は本発明に係る集積回路構体の要部６図Ａ
−Ｂ−Ｃは従来の集積回路構体と、該ｕ−４＋’ｉ回路
構休の実装方法の説明図。
１・・・集積回路チップ
２・・・保持基板
６・８・２４・２６・・・１３号端子
６Ｂ・８Ｂ・・・信号端子の外部接続部１４Ａ−１４Ａ
・・・長尺材１４の打ち抜き残余部１６Ａ・・・機器の
凹部
の信号端子６・８の折曲の説明図。
第３図は第１図Ａ−８に示した集積回路４ｂ体を機器内
に組み込む実装方法の説明図。
第４図は＃に積回路構体の他の例を要部断面図。
第５図は本発明の別の実施例の集積回路構体と、該集積
回路構体をフレキシブル回路板とともに機器内に組み込
む実装方法を説明する図。
ｈｉデ
褐
δ
図FIG. 1A-8 is a diagram 6A of the main part of the integrated circuit structure according to the present invention.
-B-C are explanatory diagrams of a conventional integrated circuit structure and a method of mounting the u-4+'i circuit structure. 1... Integrated circuit chip 2... Holding board 6, 8, 24, 26... No. 13 terminal 6B, 8B... Signal terminal external connection part 14A-14A
. . . Punching remaining portion 16A of the long material 14 . . . An explanatory diagram of bending of the signal terminals 6 and 8 in the recess of the device. FIG. 3 is an explanatory diagram of a mounting method for incorporating the integrated circuit 4b shown in FIG. 1A-8 into a device. FIG. 4 is a cross-sectional view of main parts of another example of the integrated circuit structure. FIG. 5 is a diagram illustrating an integrated circuit structure according to another embodiment of the present invention and a mounting method for incorporating the integrated circuit structure into a device together with a flexible circuit board. hi de brown δ diagram
Claims (3)
プと接続した信号端子を有し樹脂部材で外装成形した集
積回路構体において、 前記信号端子の外部接続部は外装成形部の平面に表出し
ていることを特徴とする集積回路構体。(1) In an integrated circuit structure in which an integrated circuit chip is placed on a substrate, a signal terminal is connected to the integrated circuit chip, and the exterior is molded with a resin member, the external connection part of the signal terminal is exposed on the plane of the exterior molded part. An integrated circuit structure characterized by:
曲した外部接続部は前記外装成形部の平面から突出して
該平面の表面に沿って折れ曲げられていることを特徴と
する特許請求の範囲第（１）項記載の集積回路構体。(2) The signal terminal is bent in the exterior molded part, and the bent external connection part protrudes from a plane of the exterior molded part and is bent along the surface of the plane. An integrated circuit structure according to claim (1).
した集積回路構体と、該集積回路構体を保持する保持部
材と及び、前記集積回路構体と電機接続するランド部を
備えた回路基板を有し、前記保持部材に前記集積回路構
体を収納する凹部を形成し、前記集積回路構体の前記外
部接続部と回路基板のランド部の間に導電性の粘弾性部
材を介挿し、前記集積回路構体と前記回路基板を前記保
持部材の凹部に押圧するようにしたことを特徴とする集
積回路構体の実装方法。(3) A circuit comprising an integrated circuit structure in which the external connection portion of the signal terminal is exposed on the plane of the exterior molded part, a holding member that holds the integrated circuit structure, and a land portion that electrically connects to the integrated circuit structure. a substrate, a recessed portion for accommodating the integrated circuit structure is formed in the holding member, a conductive viscoelastic member is inserted between the external connection portion of the integrated circuit structure and the land portion of the circuit board; A method for mounting an integrated circuit assembly, characterized in that the integrated circuit assembly and the circuit board are pressed into a recessed portion of the holding member.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32556488A JPH02170456A (en) | 1988-12-22 | 1988-12-22 | Mounting of integrated circuit structure body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32556488A JPH02170456A (en) | 1988-12-22 | 1988-12-22 | Mounting of integrated circuit structure body |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02170456A true JPH02170456A (en) | 1990-07-02 |
Family
ID=18178302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32556488A Pending JPH02170456A (en) | 1988-12-22 | 1988-12-22 | Mounting of integrated circuit structure body |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02170456A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0969599A (en) * | 1995-08-30 | 1997-03-11 | Nec Corp | Resin encapsulated semiconductor device |
| USRE37413E1 (en) * | 1991-11-14 | 2001-10-16 | Hyundai Electronics Industries Co., Ltd. | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63151058A (en) * | 1986-12-16 | 1988-06-23 | Matsushita Electronics Corp | Resin packaged type semiconductor device |
-
1988
- 1988-12-22 JP JP32556488A patent/JPH02170456A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63151058A (en) * | 1986-12-16 | 1988-06-23 | Matsushita Electronics Corp | Resin packaged type semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE37413E1 (en) * | 1991-11-14 | 2001-10-16 | Hyundai Electronics Industries Co., Ltd. | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
| JPH0969599A (en) * | 1995-08-30 | 1997-03-11 | Nec Corp | Resin encapsulated semiconductor device |
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