JPH02168639A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH02168639A
JPH02168639A JP5422389A JP5422389A JPH02168639A JP H02168639 A JPH02168639 A JP H02168639A JP 5422389 A JP5422389 A JP 5422389A JP 5422389 A JP5422389 A JP 5422389A JP H02168639 A JPH02168639 A JP H02168639A
Authority
JP
Japan
Prior art keywords
layer
pad
bonding
integrated circuit
melting point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5422389A
Other languages
Japanese (ja)
Inventor
Matsuo Ichikawa
市川　松雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP5422389A priority Critical patent/JPH02168639A/en
Publication of JPH02168639A publication Critical patent/JPH02168639A/en
Priority to US08/143,677 priority patent/US5719448A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To prevent imperfect bonding and the decrease of bonding strength by arranging a high melting point metal layer which is hardly scratched by a measuring terminal, under an AL pad. CONSTITUTION:On a single crystal substrate 11, a metal Mo layer 13 and an AL layer 14 are formed via an insulating film 12, and a necessary part is left while the other part is eliminated by photoetching. After a passivation film 15 is formed thereon, the insulating film on a pad part is eliminated and a hole is bored in the pad. In the case where the pin pressure of a measuring terminal is large, the AL layer 14 of the pad part is largely gouged out, but the Mo layer 13 of high melting point metal remains, and no hindrance is caused in bonding. Thereby, imperfect bonding and the decrease of bonding strength can be prevented.

Description

【発明の詳細な説明】 ［産業上の利用分野コ 本発明は半導体集積回路装置のパッド電極部の構造に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a pad electrode portion of a semiconductor integrated circuit device.

［従来の技術］ 半導体集積回路装置はいよいよりブミクロン時代へと進
展し、ｆ産のメインが２５６ＫＤＲＡＭからＩＭＤＲＡ
Ｍへと世代交替しつつあり、４ＭＤＲＡＭも試作が終り
、サンプル出荷されるばかりの状況になってきている。[Conventional technology] Semiconductor integrated circuit devices have finally progressed to the Bumikron era, and the main production has changed from 256K DRAM to IMDRA.
The generation is changing to 4M DRAM, and the prototype of 4M DRAM has been completed and samples are just being shipped.

このようなダイナミックＲＡＭの革新に見られるように
半導体集積回路装置のプロセス、デバイス及び回路面の
進展はめざましいものがある。、特に、微細化、高集積
化はハイスピードで勧められている。As seen in the innovation of dynamic RAM, there have been remarkable advances in the processes, devices, and circuits of semiconductor integrated circuit devices. In particular, miniaturization and high integration are recommended at high speed.

しかし、半導体集積回路装置の外部取シ出し電極である
パッドの構造及びＭｅ状、それに、大きさはほとんど変
化がなくすぎてきている。わずかに変化したと言えば、
過去、パッドはＡＬの一層で形成されていたが、ＡＬ配
線が二層化された工０も登場し、バッド電極も二層のＡ
Ｉ、で形成されるにいたっている。However, there has been little change in the structure, Me shape, and size of pads, which are external electrodes of semiconductor integrated circuit devices. I would say that there has been a slight change,
In the past, pads were formed with a single layer of AL, but now there is also a double-layered AL wiring, and the pad electrode is also made of two layers of AL.
It has come to be formed by I.

このＡＬバッドも昔から問題を有、しており、最近パッ
ド数が多（なるにしたがって間層が顕在化した項目があ
る。その項目は、ウェハー段階で電気測定をするさい、
端子がバクト′のＡＬにキズを付け、キズによっては後
のボンディングＷｔｔに悪影響を与える点である。This AL pad has also had problems for a long time, and recently there are items where the number of pads increases (as the number of pads increases), the interlayer becomes obvious.
The point is that the terminal scratches the AL of Bact', and depending on the scratch, it has an adverse effect on the subsequent bonding Wtt.

第３図（α）と第３図（ｂ）に従来の方法によるパッド
部分の構造を示し、以下に従来の方法についての問題点
について説明する。FIG. 3(α) and FIG. 3(b) show the structure of the pad portion according to the conventional method, and the problems with the conventional method will be explained below.

第３図（α）に示すように単結晶３１基板３１上に絶縁
膜３２をかいして、ＡＬ配線３３を形成する。その上に
バクシベーション膜５４を形成した後、パッド部の絶縁
膜を除去して、パッドの穴あけをおこなう。As shown in FIG. 3(α), an insulating film 32 is formed on a single crystal 31 substrate 31, and an AL wiring 33 is formed. After forming a vacsivation film 54 thereon, the insulating film at the pad portion is removed and a hole for the pad is formed.

第３図（ｂ）は半導体集積回路装置の電気特性を測定し
た後のパッド部のＡＬバッドの測定端子によるエグレを
示している。測定端子の針圧が強かったりすると第３図
（ｂ）のようにパッド部のＡＬが大きくエグリ取られて
しま５゜その後、良品チップはダイシング及びクラッキ
ングされて、実装へまわされる。実装の時のワイヤボン
ディング時に、パッド部のＡＬのエグレが大きいと、ボ
ンディングのボールが付きにくいし、ボンディング強度
が弱い。FIG. 3(b) shows the erosion caused by the measurement terminal of the AL pad in the pad portion after measuring the electrical characteristics of the semiconductor integrated circuit device. If the stylus pressure of the measurement terminal is strong, the AL of the pad portion will be greatly eroded as shown in FIG. 3(b).After that, the good chip is diced, cracked, and sent for mounting. During wire bonding during mounting, if the AL of the pad part has a large erodibility, the bonding ball will be difficult to attach and the bonding strength will be weak.

［発明が解決しようとする課題］ 以上より明らかなごとく、ウェハー段階の電気特性測定
時に、測定端子の圧力が強がったり、−部の端子が突出
していた場合、パッド部のＡＬをキズつけてしまい、ボ
ンディング不良やボンディング強度が弱い現象がでて（
る。特に工Ｃチップが大型化したりして、入出力端子の
数が多（なって鳴ると、不良への確立が高（なり、大き
な問題となる。[Problems to be Solved by the Invention] As is clear from the above, when measuring electrical characteristics at the wafer stage, if the pressure on the measurement terminal is strong or if the negative terminal is protruding, the AL of the pad part may be damaged. , the phenomenon of poor bonding and weak bonding strength occurred (
Ru. In particular, as industrial C chips become larger and have a large number of input/output terminals, the probability of failure becomes high, which becomes a big problem.

本発明は、以上のような欠点を工Ｃザイドから改良する
事を目的としている。The purpose of the present invention is to improve the above-mentioned drawbacks from the engineering process.

［課題を解決するための手段］ 本発明は、上記の問題を解決するために、ＡＬパッドＭ
１極の下に、測定用の端子ではキズが付きに（い高融点
金属層を設けた事を特徴とする方法である。[Means for Solving the Problems] In order to solve the above problems, the present invention provides an AL pad M
This method is characterized by providing a high melting point metal layer under one pole, which is difficult to scratch on the measurement terminal.

［実施例］ 第１図（α）、（ｂ）及び第２図（ａ）、（ｌＩ）に本
発明の方法によるパッド部の断面構造の略図を示し、以
下に本発明の方法について説明する第１図（ｃＬ）に示
すように、単結晶ｓｉ基板１１上に絶縁膜１２をかいし
て金属ＭＯ層１５とＡ、Ｌ層１４を設け、ホトエツチン
グにより必要部分を残して他を除去する。その上にパシ
ベーション膜１５を形成した後、パッド部の絶縁膜を除
去して、パッドの穴あけを行な５゜ 第１図（ｂ）は工Ｏの電気特性を測定した後のパッド部
のＡＬ層測定端子によるエグレを示している。[Example] Fig. 1 (α), (b) and Fig. 2 (a), (lI) show schematic diagrams of the cross-sectional structure of a pad portion according to the method of the present invention, and the method of the present invention will be explained below. As shown in FIG. 1(cL), a metal MO layer 15 and A and L layers 14 are provided on a single-crystal Si substrate 11 through an insulating film 12, and the necessary portions are left and the others are removed by photo-etching. After forming a passivation film 15 on the passivation film 15, the insulating film on the pad part was removed and a hole was made for the pad. This shows the egress caused by the layer measurement terminal.

測定端子の針圧が強かりたすすると第１図（ｂ）のよう
にパッド部のＡＬ層１４が大きくエグレ取られてしまう
。しかし高融点金属であるＭＯ層１３は残りボンディン
グ時になんら支障をきたさない。If the stylus pressure of the measurement terminal is too strong, the AL layer 14 at the pad portion will be greatly eroded as shown in FIG. 1(b). However, the MO layer 13, which is a high melting point metal, remains and does not cause any trouble during bonding.

第２図（α）に示すように、単結晶８１基板２１上に絶
縁膜２２をがいして高融点金属Ｍ。As shown in FIG. 2(α), an insulating film 22 is peeled off on a single crystal 81 substrate 21 to form a high melting point metal M.

層２３を形成し、ホトエツチングにより必要部分を残し
て他を除去する。その上に層間絶縁膜２４を形成し、ホ
トエツチングによりスルホールの穴あげをおこなう。そ
の上にＡＴＪ層２５をもうけ、ホトエツチングにより必
要部分を残して他を除去する。その上に１パシベーシヨ
ン膜２６を形成した後、パッド部の絶縁膜を除去してパ
ッドの穴あけをおこなう。A layer 23 is formed and removed by photoetching, leaving only the necessary portions. An interlayer insulating film 24 is formed thereon, and through holes are formed by photoetching. An ATJ layer 25 is formed thereon, and the necessary portions are left and the remaining portions are removed by photo-etching. After forming a passivation film 26 thereon, the insulating film at the pad portion is removed and a hole for the pad is formed.

第２図（ｂ）には工Ｏの電気特性を測定した後のパッド
部のＡＬ層の測定端子によるエグレを示している。測定
端子の針圧が強かりたりすると第２図（邊）のようにパ
ッド部のＡＩｉが大きくエグリ取られてしまう。しかし
、下の高融点金属ＭＯ層２３は残り、ボンディング時に
なんら支障をきたさない。FIG. 2(b) shows the deviation due to the measurement terminal of the AL layer of the pad portion after measuring the electrical characteristics of the electrode. If the stylus pressure of the measurement terminal is strong, the AIi of the pad portion will be greatly eroded as shown in Figure 2 (side). However, the lower refractory metal MO layer 23 remains and does not cause any problem during bonding.

［発明の効果コ 上記の本発明の方法によれば、ウニ八段階の電気測定の
時に測定端子によってパッド部のＡＬＮをキズ付けてし
まりても、下に高融点金属層が残るためボンディング不
良や、ボンディング強度が弱いという現象がおこらず、
特に工Ｏチップが大形化したりして入出力端子の数が多
（なっても大丈夫である。[Effects of the Invention] According to the method of the present invention described above, even if the ALN of the pad part is scratched by the measurement terminal during the electrical measurement of the eight levels, the high melting point metal layer remains underneath, which prevents bonding defects. , the phenomenon of weak bonding strength does not occur,
In particular, as industrial chips become larger, the number of input/output terminals increases (it is okay.

又、本発明の例では高融点金属層としてＭＯ層を例に示
したが、Ｗ、Ｔｉ及びＮ１等、他の高融点金属やＯｕで
も同じ効果が出せるし、合金及び多層購造でも同様であ
る。In addition, in the example of the present invention, an MO layer is used as an example of a high melting point metal layer, but the same effect can be obtained with other high melting point metals such as W, Ti, N1, etc., and with alloys and multilayered materials. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ｃＬ）、（ｂ）及び第２図（α）、（ｂ）は本
発明の例としてのポンディングパッド部の断面略図であ
る。 第３図（α）　（ｂ）は従来の方法の例としてのポンデ
ィングパッド部の断面略図である。 以上FIGS. 1(cL) and (b) and FIGS. 2(α) and (b) are schematic cross-sectional views of a bonding pad portion as an example of the present invention. FIG. 3(α)(b) is a schematic cross-sectional view of a bonding pad portion as an example of a conventional method. that's all

Claims (1)

【特許請求の範囲】[Claims] 外部引き出し用パッド電極部にＡＬ層を用いる半導体集
積回路装置において、該パッド電極部の該ＡＬ層の下の
少なくとも一部に、少なくとも一層以上の高融点金属層
を設けた事を特徴とする半導体集積回路装置。A semiconductor integrated circuit device using an AL layer in a pad electrode section for external extraction, characterized in that at least a part of the pad electrode section under the AL layer is provided with at least one high melting point metal layer. Integrated circuit device.
JP5422389A 1988-08-25 1989-03-07 Semiconductor integrated circuit device Pending JPH02168639A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP5422389A JPH02168639A (en) 1988-08-25 1989-03-07 Semiconductor integrated circuit device
US08/143,677 US5719448A (en) 1989-03-07 1993-10-26 Bonding pad structures for semiconductor integrated circuits

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP21119488 1988-08-25
JP63-211194 1988-08-25
JP5422389A JPH02168639A (en) 1988-08-25 1989-03-07 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH02168639A true JPH02168639A (en) 1990-06-28

Family

ID=26394970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5422389A Pending JPH02168639A (en) 1988-08-25 1989-03-07 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH02168639A (en)

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