JPH02166766A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form two types of electronic circuits having different operating speeds on the same semiconductor substrates by forming a reference circuit cell section having a plurality of reference circuit cells and a matrix wiring section disposed between the individual cell sections and a reference circuit cell section for connecting a predetermined individual cell of them to the reference circuit cells to each other. CONSTITUTION:When high speed signals Sin 1, Sin 2 are supplied to electrode pads 14, the signals Sin 1, sin 2 are input to inverters 30-1, 30-2 in a reference circuit cell section 12, and the signals required for a process of a high speed signal is sent to a high speed circuit section 40 through output side nodes 33-1, 33-2. On the other hand, when a process of a low speed signal is executed, signals of output side nodes 33-1, 33-2 are sent to individual cell sections 11 through connecting points 52a, 52b, 52c, 52d preset in a matrix wiring section 13, and a NOR is taken by a 2-input NOR gate 20 in the individual cell section 11 to be processed. Thus, increases in power consumption and chip area are suppressed, and both high and low speed operation processes are performed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit having a gate array structure in which a plurality of individual cells, etc. for forming a logic circuit are arranged and formed on a semiconductor substrate. be.

(Conventional technology) Conventionally, as a technology in this field, for example, Suzuki-so
Edited and authored "Gate Array" first edition (Sho 6l-11-5) El
There was one described in Kankogyo Shinbunsha, P, 1.4-15.

As described in this document, a semiconductor integrated circuit with a gate array structure has basic cells (gates) for making logic arranged on a semiconductor substrate, and metal The wafer is wired to have a specific function.The first half, where the gates are lined up, is made in a standard manner and is called the master wafer, and the second half, which is made according to the customer's specifications, is called virtualization. FIG. 2 shows an example of a master wafer chip in a semiconductor integrated circuit having this gate array structure.

As shown in FIG. 2, an individual cell section 2 is formed on a semiconductor substrate 1 by arranging a large number of individual cells for making logic. The area between individual cells is a wiring area.

After the desired electrode wiring process is performed on the individual cells using the wiring area and an electronic circuit is formed, a plurality of electrode pads 3 for outputting signals to the electronic circuit are placed on the semiconductor substrate. 1 and constitutes a semiconductor integrated circuit.

In this type of semiconductor integrated circuit, a semiconductor substrate 1 having an individual cell portion 2 whose manufacturing operation has proceeded halfway through the semiconductor manufacturing process.
Moreover, by adding a manufacturing process for electrode wiring tailored to a desired electronic circuit, it has the advantage that semiconductor integrated circuits tailored to diversified electronic circuits can be easily realized in an extremely short time.

(Problems to be Solved by the Invention) However, the semiconductor integrated circuit having the above configuration has the following problems.

In the conventional Goo 1-Array Tsuzo semiconductor integrated circuit, electrode wiring is performed in accordance with the desired electronic circuit on a semiconductor substrate 1 having an individual cell section 2 that has been manufactured halfway through the semiconductor manufacturing process. Since it forms an integrated circuit, it is extremely useful in cases where the operating speed of the electronic circuit, that is, the operating speed of the individual cell section 2, only needs to satisfy a certain characteristic, and is not widely used in practical use. has been done.

However, in this type of semiconductor integrated circuit, when attempting to form an electronic circuit that handles signals at a higher speed at a certain operating speed, the operating speed of the individual cell section 2 reaches its limit at a certain operating speed. Therefore, it is necessary to provide a cell for high-speed operation within the individual cell section 2, but this is not possible because the manufacturing process becomes complicated. In order to solve this problem, it is possible to configure all of the individual cell section 2 with high-speed circuits, but if you try to make everything high-speed, the power consumption will increase and the area for forming the individual cell section 2 will increase. There were problems such as the size of the device, and it was not possible to create something that was technically satisfactory.

The present invention solves the problem of the prior art, which is that it is difficult to form two types of electronic circuits with different operating speeds on the same semiconductor substrate without increasing power consumption and element formation area. The company provides semiconductor integrated circuits and circuits.

(Means for Solving the Problems) In order to solve the above problems, the invention of claim 1 provides that an individual cell portion in which a plurality of individual cells for configuring a logic circuit are arranged is provided on a semiconductor substrate-F. In the formed semiconductor integrated circuit having a gate array structure, a standard circuit cell section having a plurality of standard circuit cells having a wiring standard matching the wiring standard for the individual cell section, and a connection between the individual cell section and the standard circuit cell section. A matrix wiring section located between and interconnecting predetermined individual cells and standard circuit cells therein,
It is formed on the semiconductor substrate.

In the second aspect of the present invention, the individual hill section is constructed of a low-speed, low-power circuit, and the standard circuit cell section is constructed of a circuit that can operate at a higher speed than the individual cell section.

According to the inventions of claims 1 and 2, since the semiconductor integrated circuit is configured as described above, the standard circuit cell section can perform, for example, high-speed operation, and the lower constant speed operation can be performed individually, for example. By providing a receiver in the cell section, and having the receiver in the 7-trix wiring section for signal exchange between the standard circuit cell section and the individual cell section, high-speed performance and performance at low speed and relatively low power consumption are achieved. It becomes possible to easily configure a semiconductor integrated circuit having both of the following. Therefore, the above problem can be solved.

(Example) Figure 1 (a>, (b) shows an example of the present invention,
Figure (a) is a block diagram of a semiconductor integrated circuit having a gate array structure, and figure (1) is a circuit diagram showing an example of the configuration of a main part thereof.

As shown in FIG. 1 (a), this semiconductor integrated circuit has a semiconductor substrate 11 made of, for example, semi-insulating GaAs,
On the semiconductor substrate ui11, an individual cell section 11 and a standard circuit cell section 12 are formed facing each other. The individual cell section 11 is constructed by arranging a large number of individual cells each having a constant operating speed. Each individual cell is, for example, a Schottky barrier gate field effect transistor (Metal).
semicondt+ctor field effe
ct transistor (hereinafter referred to as MESFET)
(hereinafter referred to as DCFL). The standard circuit cell section 12 is composed of a plurality of standard circuit cells capable of high-speed operation. Each standard circuit cell is composed of, for example, a DCFL using MESFET.

Further, on the semiconductor substrate 10, a mitric wiring part 13 is formed between the individual hill part 11 and the standard circuit cell part 1-2 to connect them both to each other, and further on the outer periphery thereof. A plurality of electrode pads 14 are formed for signal output.

In order to manufacture such a semiconductor integrated circuit, for example, an individual cell section 11 and a standard circuit cell section 12 are placed on a semiconductor substrate 10.
After forming the individual cell part 11 and standard circuit part 12
An electrode wiring process is performed on the substrate to form an electronic circuit, and a matrix wiring section 13 is also formed. Next, predetermined locations of the matrix wiring section 13 are connected to interconnect the individual cell section 11 and the standard circuit cell section 12, and then the electrode pads 3 and the like are formed to form a semiconductor integrated circuit with a group 1-array structure. A circuit is obtained.

Next, the circuit configuration of this semiconductor (41: integrated circuit) is shown in Figure 1 (
This will be explained with reference to b).

For example, a two-manpower NOR gate 20 is formed in a part of the individual cell section 11 . This two-man powered NOR gate 20 consists of two normally-off MESFETs (
21°22 (hereinafter referred to as EFET), and a normally-on type MESFET (hereinafter referred to as DFE) with one step for the load.
I') 23 connected in parallel]
, 22 and a DFET 23 are connected in series between the power supply potential DD and the ground potentials V and S. The standard circuit cell section 12 includes buffer inverters 30-1 and 30-2 made up of standard cells, and a high-speed circuit section 40 for high-speed signal processing made up of flip-flops and the like. The inverters 30-1 and 30-2 take in the high-speed signal 5inlSin2 supplied to each electrode pad section 14, and are connected to the switch EFET 31 and the load DFET connected in series between the power supply potential VDD and the ground potential 788.
Each of them consists of 32 pieces. Inverter 30-1.
The output side nodes 33-1, 33-2 of 30-2 are connected to the input side of the high-speed circuit section 110, and are also connected to the input side of the two-person NOR gate 20 via the matrix wiring section 13.

The matrix wiring section 13 is composed of, for example, a plurality of first layer wirings 50 arranged in parallel in the horizontal direction and a plurality of second layer wirings 51 arranged in parallel in the vertical direction. The intersection points are connected with through holes. Figure 1(b)
Here, 52a to 52c represent connection points, and the inverter 3
0-1 output side node 33-1 or connection points 52a, 52b
The output node 33-2 of the inverter 30-2 is further connected to the gate electrode of the EFET 22 via connection points 52c and 52d.

FIG. 3 is a pattern layout diagram of FIG. 1(b).

In this pattern layout diagram, for example, EFET31 is
It has a structure in which a long gate electrode 31G is disposed between a source electrode 31S and a drain electrode 31D. Pond E
FET and DFET have similar structures.

The operation of the semiconductor integrated circuit configured as described above will be explained.

In FIG. 1(b), when a high-speed signal 5inlSin2 is supplied to each type and pole pad 14, the signal 5inl
, 5in2 is the inverter 30- in the standard circuit cell section 12.
1.30-2, and those requiring high-speed signal processing are sent to the high-speed circuit unit 40 through the output node 33-1.33=2. On the other hand, when performing low-speed signal processing, the signals of the output side nodes 33-1, 33-2
, 52c and 52d to the individual cell section 11,
The two-man NOR gate 20 in the individual cell unit 11 performs processing such as performing a negative OR operation.

This embodiment has the following advantages.

A conventional semiconductor integrated circuit as shown in FIG. 2 is composed of individual cell parts 2 that have a certain operating speed, so it is easy to construct a semiconductor integrated circuit that has both high-speed operation and a certain lower operating speed. It was difficult to do so. On the other hand, in this embodiment, high-speed input signals 5inl, 5in2
On the other hand, high-speed signal reception and high-speed signal processing are performed in the standard circuit cell section 12, and lower-speed signal processing is performed in the individual cell section 11 through the matrix wiring section 13. Therefore, high-speed operation processing and low-speed operation processing are possible while suppressing increases in power consumption and chip area.

In addition, DCF by G aA s ME'S FET
When patterning was performed with L as shown in FIG. 3, it was extremely easy to operate at a high speed of IGH7 or higher in the standard circuit cell section 12, and to operate at about 200 MHz in the individual cell section 11.

Note that the present invention is not limited to the illustrated embodiment, and for example, as a semiconductor base, a compound semiconductor other than GaAs or S
Various modifications are possible, such as using a substrate such as I, and configuring the individual cell section 11 and the standard circuit cell section 12 with logic circuits other than those shown in FIG. 1(b).

(Effects of the Invention) As described above in detail, according to the invention of claims 1 and 2, the circuit allows the standard circuit cell section to perform, for example, high-speed signal processing, and the individual cell section to perform, for example, slower signal processing. The integrated circuits formed on the same semiconductor substrate can handle high-speed signal reception, high-speed signal processing, and lower-speed signal processing. Therefore, it can be easily achieved without increasing power consumption or chip area.

[Brief explanation of the drawing]

FIG. 1 (a>, (b) shows an embodiment of the present invention,
The same figure (a> is a block diagram of a semiconductor integrated circuit, the same figure (b)
2 is a block diagram of a conventional semiconductor integrated circuit, and FIG. 3 is a pattern layout diagram of FIG. 1(b). 10...Semiconductor substrate, 11...Individual cell section, 12...Standard circuit cell section, 13...
...Matrix wiring section, 14... Electrode pad.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit formed on a semiconductor substrate, an individual cell portion in which a plurality of individual cells for configuring a logic circuit are arranged meets wiring standards for the individual cell portion. a standard circuit cell section having a plurality of standard circuit cells having a wiring standard; and a standard circuit cell section located between the individual cell section and the standard circuit cell section, and interconnecting predetermined individual cells and standard circuit cells therein. A semiconductor integrated circuit, comprising: a matrix wiring section formed on the semiconductor substrate. 2. The semiconductor integrated circuit according to claim 1, wherein the individual cell section is composed of a low-speed, low-power circuit, and the standard circuit cell section is composed of a circuit that can operate at a higher speed than the individual section.