JPH0216616U - - Google Patents
Info
- Publication number
- JPH0216616U JPH0216616U JP9495988U JP9495988U JPH0216616U JP H0216616 U JPH0216616 U JP H0216616U JP 9495988 U JP9495988 U JP 9495988U JP 9495988 U JP9495988 U JP 9495988U JP H0216616 U JPH0216616 U JP H0216616U
- Authority
- JP
- Japan
- Prior art keywords
- output terminal
- input terminals
- circuits
- terminal
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 2
Description
第１図は本考案の多安定フリツプフロツプの基
本回路図、第２図は第１図に示す本考案の多安定
フリツプフロツプの動作説明図、第３図は本考案
の多安定フリツプフロツプの一実施例を示す回路
図、第４図は本考案の多安定フリツプフロツプの
他の基本回路図、第５図は第４図に示す本考案の
多安定フリツプフロツプの動作説明図、第６図は
本考案の多安定フリツプフロツプの他の実施例を
示す回路図、第７図は従来のＩＣ化された優先回
路、第８図は従来の優先回路の駆動方法を示す系
統図、第９図は従来の優先回路の駆動タイミング
線図である。
１，２，３はフリツプフロツプ回路、４は優先
回路、５，６，７，８，９はＮＡＮＤ、１０，１
１，１２，１３，１４はＮＯＲである。
Figure 1 is a basic circuit diagram of the multistable flip-flop of the present invention, Figure 2 is an explanatory diagram of the operation of the multistable flip-flop of the present invention shown in Figure 1, and Figure 3 is an embodiment of the multistable flip-flop of the present invention. 4 is another basic circuit diagram of the multistable flip-flop of the present invention, FIG. 5 is an explanatory diagram of the operation of the multistable flip-flop of the present invention shown in FIG. A circuit diagram showing another embodiment of the flip-flop, FIG. 7 is a conventional IC priority circuit, FIG. 8 is a system diagram showing a method of driving a conventional priority circuit, and FIG. 9 is a driving method of a conventional priority circuit. It is a timing diagram. 1, 2, 3 are flip-flop circuits, 4 is a priority circuit, 5, 6, 7, 8, 9 are NAND, 10, 1
1, 12, 13, and 14 are NOR.
Claims (1)
和否定回路からなる論理回路の夫々はＮ個の入力
端子と１つの出力端子を具備し、上記論理回路の
夫々のＮ個の入力端子のうち夫々の１入力端子を
外部入力端子とし、他のＮ―１個の夫々の入力端
子は自分自身の上記出力端子以外の他のＮ―１個
の論理回路の上記出力端子に１本づつ接続する様
にして成ることを特徴とする多安定フリツプフロ
ツプ回路。 Each of the logic circuits consisting of N (N≧3) AND/NOT circuits or ORD/NOT circuits has N input terminals and one output terminal, and each of the N input terminals of the logic circuit has N input terminals and one output terminal. One input terminal of each of them is used as an external input terminal, and each of the other N-1 input terminals is connected to the output terminal of the other N-1 logic circuits other than its own output terminal. A multistable flip-flop circuit characterized in that it is configured in such a way that it is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9495988U JPH0216616U (en) | 1988-07-18 | 1988-07-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9495988U JPH0216616U (en) | 1988-07-18 | 1988-07-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0216616U true JPH0216616U (en) | 1990-02-02 |
Family
ID=31319556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9495988U Pending JPH0216616U (en) | 1988-07-18 | 1988-07-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0216616U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS532547A (en) * | 1976-06-29 | 1978-01-11 | Daicel Chem Ind Ltd | Recovery of electrodeposition coating |
-
1988
- 1988-07-18 JP JP9495988U patent/JPH0216616U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS532547A (en) * | 1976-06-29 | 1978-01-11 | Daicel Chem Ind Ltd | Recovery of electrodeposition coating |
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