JPH02165668A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the size of a cell and the size of a chip by providing an insulating layer which is selectively formed at a position facing a one- conductivity type impurity region, and forming another impurity region having another conductivity type based on a step between the exposed surfaces of a substrate. CONSTITUTION:A B-implanted layer 4 is formed in a semiconductor substrate 1 or in an insulating layer 2 which is grown on the semiconductor substrate 1 with resist 3 as a mask. Thereafter, a silicon dioxide layer 5 is deposited only on the semiconductor substrate 1 or the insulating layer 2 covering the semiconductor layer 1. Then, the resist layer 3 is peeled away. With the insulating layer 5 as a mask, P ions are implanted, and both well regions 7 are formed. Si steps are formed by utilizing the difference in growing speeds of Si oxide films covering the P- and B-implanted layers. The level differences are utilized in the following steps. Thus the semiconductor substrate can be reduced.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device in which a P/N type diffusion layer is formed by the Self Align method.
In particular, the present invention relates to c/mos P/N wells (Twin Wells) used in peripheral devices of highly integrated semiconductor devices such as D-RA).

(Prior art) In the currently used P/N well method of c/mos structure, a P well region and an N well region are formed adjacent to each other in a silicon semiconductor substrate, and a highly doped source layer,
A gate is further provided in the drain region to obtain an FET structure. This P-well region and N-well region are subjected to PEP twice.
This was achieved through the (Photo Engraving process) process. That is, as shown in FIGS. 3(a) to 3(d), a thermal oxide film 21 of 1000 angstroms is first formed on an N(100) substrate 20 with a specific resistance ρ~2.5 Ωcm.
After forming (FIG. 3-a), the P-well resist 22 is patterned.

Next, using the resist pattern 22 as a mask, the first ion species B is heated at Vacc=100KeV, Q=1.5xlO'
A B ion-implanted P layer 23 is formed near the surface of the N (100) substrate 20 as shown in FIG. 3-a by implanting at a depth of 3 cm. Next, using the resist pattern 22 as a mask, N
After performing isotropic etching on the thermal oxide film 21 using 84 F, the resist pattern 22 is peeled off. Then 95
A step 24 of about 50 angstroms is formed between the B implanted region and the non-implanted region by oxidizing in a wet atmosphere (mainly composed of N containing several volume percent of M elements) at 0° C. (Fig. 3-b). Figure-b). This step is an alignment mark (Alignm) previously formed on the N-type semiconductor substrate 20 for mask alignment.
Also used for ent Mark).

By the way, the N well region 26 necessary for the twin well region
To form the resist layer 26, as shown in FIG.
Vacc=160KeV, Q=I×1
0130 "2 implantation to form the P ion implantation layer 23 with N(10
0) Formed near the ground surface of the substrate 20.

Thereafter, after the resist layer 26 was dissolved, a drive-in process was performed for 150 minutes in an oxidizing atmosphere (mainly N and containing 1% oxygen) at 1190° C., as shown in FIG.
P-well region 27.d as shown in cross-section. A twin well structure consisting of an N well region 28 is shown in 1q.

In this example, the drive-in process for the P and N well regions is performed all at once, but in order to adjust the surface concentration Ns and diffusion depth Xj of each well region, it is necessary to perform the drive-in process twice after each injection. There is also. As is clear from FIG. 4, impurities of opposite conductivity type are introduced into the vicinity of the surfaces of both well regions to form high concentration layers P and N layers.
A cell base consisting of a drain (0) and a gate (G) is created by a PEP process using the P well region having the step 24 as a reference.

(Problems to be Solved by the Invention) As clarified in the conventional technology, the PEP process for the N-well region and S, D, and G is performed using the P-well region as a reference pattern. and S,
Mask alignment in the PEP process for D and G is indirect. For example, 25 created using the 1.2 μm rule (Rule)
6. According to the current design standard for Full c/mos, the distances a and b between the boundaries of both well regions, the ends of the high concentration layer 29.30, and the ends of both well regions 27.28 shown in FIG. 4 are a+b=
A margin of 3 μm (a=b=1.5 μm) is provided for mask alignment.

On the other hand, electrically, the distances a and b are
h Through) withstand voltage and latch up (Latch
Up) From the viewpoint of resistance, a = b = 1 μm is sufficient, but since the PEP process for the N-well region is required as described above, the margin (+ar
gin) and design a = b = 1.5 μm.

By the way, the cell structure with a degree of integration of Full C/MOS in 256 has a vertical length of 21 μm, so the contribution of 1 μm of allowance for the PEP process is only a few percent at most, and it is expected that it will be implemented in the future and the vertical length will be 5 μm. 0,5
In the μm rule, the alignment margin for the PEP process has a large influence on the cell size.

In addition, PEP for semiconductor device manufacturing according to the 1.2 μm rule
In the process, direct bonding is 0.3 μm, and bonding is 0.5 μm between 5
This is the h'a') measurement standard, and the aligner performs actual work using this dimension.

The present invention has been developed in view of the above circumstances, and in particular, it reduces the alignment margin, leading to a reduction in cell size and chip size, and also contributes to improving productivity by omitting the IPEP process.

[Structure of the Invention] (Means for Solving the Problem) The present invention provides impurity regions of different conductivity types that are formed adjacent to each other in a semiconductor substrate, and a selective impurity region that faces the -5 conductivity type impurity region. The semiconductor device is characterized by an insulating layer formed and an impurity region of the other conductivity type formed based on a step between the insulating layer and the exposed surface portion of the semiconductor substrate.

(Function) In the semiconductor device according to the present invention, a resist for forming a well region is patterned on the semiconductor substrate used or an insulating layer grown on the semiconductor substrate, and B is ion-implanted using the resist as a mask. Forms a large layer.

After that, after performing surface treatment in plasma or neutral species atmosphere, for example, by LPO method or anodic oxidation method, the 2M silicon oxide layer does not grow on the resist layer, but only on the semiconductor substrate or the insulating layer covering the semiconductor substrate. deposit. Next, after peeling off the resist layer, P ions are implanted using this insulating layer as a mask, and both well regions are formed by the Self Align method.

This difference in the growth rate of the Si oxide film covering the P and B injection layers is used to form a Si step, and this step is used in subsequent steps, which has the great advantage of making it possible to reduce the size of the semiconductor substrate. .

(Embodiment) (1) An embodiment of the present invention will be described with reference to FIG. Since the manufacturing method is the same as that of the conventional example shown in FIGS. 3A and 3B until the 8 injection layers are formed on the semiconductor substrate 1, a detailed explanation is omitted, and the corresponding drawings are also omitted in FIG.

That is, a thermal oxide film 2 of 1000 angstroms is coated on the surface of an N(100) semiconductor substrate 1 having a specific resistance .rho.~2.5 ohm-cm, and then a pattern 3 is formed on the coated resist. Using this resist pattern layer 3 as a mask, a B injection layer 4 is formed on the semiconductor substrate 1.

Next, the surface of the resist pattern layer 3 is exposed to O plasma (P
After surface treatment by exposing the semiconductor substrate 1 to a thermal oxide film 2 for 30 seconds, a 6000 angstrom layer is deposited only on the thermal oxide film 2 covering the surface of the semiconductor substrate 1 using the LP method, in which a silicon dioxide layer is deposited from a silicon fluorine supersaturated solution using the following reaction formula. P
D (LiqLIid phase Depositio
A silicon dioxide layer 5 (hereinafter referred to as an insulating layer) is deposited by method n) as shown in FIG. 1-a.

This LPG silicon 21ide layer is deposited, for example, from a supersaturated silicon dioxide solution of silicofluoric acid, and its reaction formula is H2S!
F+H20=2S i 02 +HF.

In addition, pretreatment using oxygen plasma or neutral species generated by Freon gas discharge (Chemical DryEt
It has been confirmed that the LPo 2 M silicon oxide layer produced by the above reaction formula is difficult to precipitate on the resist subjected to the above reaction formula.

Next, the resist pattern layer 1 is peeled off, and using this insulating layer 5 as a mask, P ions are implanted at vacc=160K.
The P injection layer 6 is formed as shown in FIG. 1-b under the conditions of eV and Q=I.times.10.times.10.sup.13C.

Sarani, 1190°CN +Q (765B) (7)ff
Perform the ambient Tewel drive-in process, and add 8 injection layers 4 and P
An N well region 7 and a P well region 8 are formed by self-alignment using the injection layer 6 as shown in FIG. 1--. As a result, P well region 6 and N well region 4 are formed adjacent to each other in semiconductor substrate 1.

In this drive-in process using an atmosphere of 1190'CN202 (7% by volume), the difference in growth rate between the thermal oxide film 2 covering the P injection layer 6 and the insulating layer 5 covering the N well region 4 results in a growth of approximately 500 angstroms. A silicon step is formed as shown in FIG. 1C.

Since this step is used for alignment during the subsequent PEP process for the source, drain, and gate, the mask alignment process for both well layers is no longer necessary, leading to a reduction in the number of steps and a reduction in the size of the semiconductor substrate.

(2) In the above example, the process after the patterning step of the resist coated on the thermal oxide film grown on the semiconductor substrate was explained, but the above process was performed based on the resist directly deposited on the semiconductor substrate. It doesn't make any difference.

(3) An example using an anodic oxidation method instead of the LPo method will be explained.

That is, in the first step of forming the B injection layer in Example 1, the thermal oxide film 2 is removed using the resist pattern layer 3 as a mask, and then the N injection layer is formed.
A semiconductor substrate is anodized (plated) with a mixed solution consisting of methylacetamide, KNO3, and UR ionized water to form a silicon dioxide film, and after this, a semiconductor with twin well regions is formed by the same process as in Example 1. The description of the device is omitted to avoid overemphasizing it.

In the P/N twin well region formed by such a process, a high concentration layer is placed as shown in FIG. 4 to form a source and a drain necessary for the FET.

[Effects of the Invention] In Figure 2, the vertical axis shows the N+-N well breakdown voltage yield χ, and the horizontal axis shows the N+-N well spacing (dimensions on the mask), with the conventional example shown as a solid line and the present invention shown as a dotted line. However, in the conventional example, it is 1.45
While a 100% yield can be obtained with an N+-N well spacing of 1.15 μm or more, the present invention
A yield of 0% has been obtained.

Furthermore, in 256 and Full c/mos, a shown in Figure 4
+b, the cell size can be reduced by 0.6 μm, that is, the chip size can be reduced by 0.6 μm721 μm=3%.

In addition, the effect of the cell line twin well structure according to the present invention will be even greater in future miniaturization of cell dimensions.

Furthermore, since the number of well steps can be reduced from two to one, it is clear that there are advantages in terms of productivity and cost.

[Brief explanation of the drawing]

FIGS. 1A to 1C are cross-sectional views showing the steps of an embodiment of the present invention;
FIG. 2 is a curve diagram showing the characteristics of a semiconductor memory device manufactured by this process, FIGS. 3a to 3d are sectional views of a conventional manufacturing process, and FIG. 4 is a sectional view of a conventional twin well structure. 1: Semiconductor substrate 2; Insulator layer 7. 8: Well area agent Patent attorney Norio Ogo - N7 - Le Men Ichiya Fusai tX) -

Claims (1)

[Claims] impurity regions of different conductivity types formed adjacent to each other on a semiconductor substrate; an insulating layer selectively formed at a position opposite to the impurity region of one conductivity type; and the insulating layer and the exposed surface of the semiconductor substrate. A semiconductor device comprising another impurity region of the other conductivity type formed based on a step difference between parts.