JPH02160283A - Liquid crystal display driving device - Google Patents

Abstract

PURPOSE:To prevent the constitution from increasing in size, the operation speed from decreasing, and the driving signal from having variance by averaging the offset voltage of a picture element signal voltage with an adjusting signal which reduces the difference between a reference signal and the mean signal obtained by averaging sample-held signals obtained by sampling and holding the reference signal. CONSTITUTION:A mean offset calculating circuit 23 calculates the mean signal by averaging the reference signal and >=1 sample-held signals generated by sampling and holding the 1st reference signal A corresponding to respective picture elements. An adjusting signal generating circuit 27 compares the mean signal calculated by the mean offset calculating circuit 23 with the 1st reference signal A and generates the adjusting signal for reducing the difference between both signals. A driving adjusting circuit 21 adjusts the offset voltages of respective picture element signal voltages according to the adjusting signal generated by the adjusting signal generating circuit 27. Consequently, the increase in the size of the constitution, a decrease in the operation speed, and the variance of the driving signal are prevented.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a liquid crystal display driving device that drives a liquid crystal display using one or more IC-based The present invention relates to a liquid crystal display driving device including an X driving circuit that suppresses

(Prior Art) As an example of driving a liquid crystal display, for example, an active matrix display, there is one constructed as shown in FIG.

In FIG. 24, in an active matrix display, a pixel signal voltage is supplied to and held by a capacitor 3 corresponding to each liquid crystal (not shown) of the display panel 1 by opening/closing control of a switch 5, and the held pixel An image is displayed on the display panel 1 by applying a signal voltage to a corresponding liquid crystal. Each pixel signal voltage is supplied from an X drive circuit 7, and the opening/closing of the switch 5 is controlled by a Y drive circuit 9.

In such displays, as the screen size increases, the X drive circuit 7 that generates pixel signals corresponding to each liquid crystal in the line direction from input image signals such as TV signals and outputs them simultaneously is important. Become something. An example of such an X drive circuit 7 is one constructed as shown in FIG. 25.

In FIG. 25, the X drive circuit 7 includes a system register (switch pulse generation circuit) 11 that generates a switch pulse serving as a signal for sampling an input image signal, and a switch circuit 13 that samples and holds the input image signal. and a capacitor 15, and an output circuit 17 that outputs the sampled and held signal to the display panel 1 as a pixel signal.

In the input image signal, as shown in FIG. 26(A), image information corresponding to a unit screen consisting of a predetermined number of horizontal lines is continuously provided at intervals of a vertical synchronization period (α). In addition, each image information shown in FIG. 26 (△) is composed of image information for one horizontal line consecutively arranged at intervals of a horizontal synchronization period (β), as shown in FIG. 26 (B). ing.

Such an input image signal is input to the shift register 11 in synchronization with the horizontal shift clock, and is lean-pulled and held in accordance with the output switch pulse. That is, the input image signal is applied to and held in the capacitor 15 via the switch circuit 13 whose conduction is controlled by the switch pulse. The held input image signal is applied to the corresponding pixel of the display panel 1 via the output circuit 17.

When converting such an X drive circuit 7 into an IC to drive display on a large screen display panel 1, the X drive circuit 7
It is extremely difficult to configure the
As shown in FIG. 27, the X drive circuit 7 was composed of a plurality of ICs.

(Problems to be Solved by the Invention) As described above, when the X drive circuit 7 is composed of a plurality of ICs, variations occur in the respective ICs in terms of manufacturing, configuration, etc. For example, when the switch circuit 13 is configured with FETs, variations occur in the characteristics of the FETs. As a result, the parasitic capacitances formed between the gate electrode and source electrode of the FET are different. This is particularly noticeable in ICs with different lofts or C quadratures.

Therefore, the input image signal and switch pulse are FE
Since the pixel signal voltage is divided into the parasitic capacitance T and the hold capacitor 15, different offset voltages are generated in each pixel signal voltage. In this way, when variations occur between the respective pixel signal voltages, problems such as stepped or striped stripes occur on the display screen. This is particularly noticeable at the boundary between screens driven by different ICs.

Therefore, it is necessary to suppress the variations in the characteristics of each tC.
All ICs constituting one X drive circuit
All chips must be from the same lot or wafer. However, this countermeasure against J: causes a problem in that the yield deteriorates and the manufacturing efficiency deteriorates.

On the other hand, in order to reduce the offset voltage generated in the pixel signal voltage, it is necessary to increase the capacitance of the capacitor 15 relative to the parasitic capacitance of the FET forming the switch circuit 13. However, if the capacitance of the capacitor 15 is increased, the occupied area will increase and the operating speed will be limited.

Therefore, the present invention has been made in view of the above, and its purpose is to suppress variations in a large number of drive signals that drive a liquid crystal without causing an increase in the size of the structure or a decrease in operating speed. Therefore, it is an object of the present invention to provide a liquid crystal display driving device that makes it easy to view displayed images.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a liquid crystal display driving device having both paths for input image signals sampled and held corresponding to each pixel. is a calculation means for calculating an average signal obtained by averaging a first reference signal and at least one or more sample-and-hold signals obtained by sample-holding the first reference signal corresponding to each pixel; adjustment signal generation means for comparing the calculated average signal with a first reference signal and generating an adjustment signal for reducing the difference between the two signals; and adjusting each pixel according to the adjustment signal generated by the adjustment signal generation means. The unit X drive circuit includes an adjustment means for adjusting the offset voltage of the signal voltage.

Further, in order to achieve the above object, the present invention provides a liquid crystal display driving device including a circuit for applying sampled and held input image signals corresponding to each pixel as a pixel signal voltage to each corresponding pixel. Calculating means for calculating a difference signal between one reference signal and at least one or more sample-and-hold signals obtained by sample-holding the first reference signal corresponding to each pixel, and an average signal obtained by averaging them; A second signal obtained by averaging the plurality of average signals
and a reference signal generating means for generating a reference signal of , and comparing the difference signal or average signal calculated by the calculating means with a second reference signal generated by the reference signal generating means to reduce the difference between the two signals. a unit
It is configured with a drive circuit.

(Function) In one of the configurations described above, the present invention provides an adjustment signal that reduces the difference between the first reference signal and the average signal obtained by averaging the sample-and-hold signals obtained by sample-holding the first reference signal. The offset voltage is averaged out.

Further, in the other configuration described above, the present invention calculates a difference signal between the sample hold signal and the first reference signal and an average signal obtained by averaging them, and calculates a difference signal between the sample hold signal and the first reference signal, and calculates a difference signal between the difference signal or the average signal and the second reference signal. The offset voltage of the pixel signal voltage is averaged by an adjustment signal that reduces the difference.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the main part configuration of a liquid crystal display driving device according to a first embodiment of the present invention.
Figure 2 shows the configuration shown in Figure 1 as one IC.
FIG. 2 is a diagram illustrating how an X drive circuit is configured using a plurality of C and drives the display panel 1 for display. In addition, the first
In the figures and FIG. 2, the same reference numerals as in FIGS. 24 to 27 have the same functions, and the explanation thereof will be omitted.

The first embodiment of this invention and the embodiments described below are as follows:
The offset voltage of each IC was adjusted using the free time shown by the vertical synchronization period α and horizontal synchronization period β shown in FIG. 26 to reduce variations in the pixel signal voltage that drives the liquid crystal. It is something.

In FIG. 1, a drive adjustment circuit 21 that generates a pixel signal voltage from an input image signal and adjusts an offset voltage includes a shift register 11, a switch circuit 13, a capacitor 15, an output circuit 17, and an average offset calculation circuit 23. It is composed of The X drive circuit includes, in addition to the drive adjustment circuit 21, a reference signal change circuit 25 and an adjustment signal generation circuit 27.

The IL average offset calculation circuit 23 outputs a reference signal A having a constant value given to the input image signal, which is sampled and held in a sample hold (S/H) circuit consisting of a switch circuit 13 and a capacitor 15, and is outputted via an output circuit 17. It receives the given reference signal A and calculates the average of the differences between the two.

The reference signal A may be changed to the value of the input image signal that appears most frequently each time the offset is adjusted.

Further, the reference signal A is sequentially sampled and held by switch pulses shifted by the shift register 11. Alternatively, the reference signal A may be sampled and held at one time.

When the reference signal is sampled and held sequentially, the average offset calculation circuit 23 sequentially integrates the sampled and held reference signal A, and calculates the value obtained by dividing this integrated value by the total number of S/8 circuits and the reference signal @ Calculate the difference between On the other hand, if the reference signal A is sampled and held at once, -
At the same time, the sampled and held reference signal A is added together, and the difference between this added value divided by the total number of S/8 circuits and the reference signal A is calculated. In this way, the average offset calculation circuit 23 calculates the average value of the offset voltages of the drive adjustment circuit 21 (average offset voltage). The calculated average offset voltage is given to the reference signal change circuit 25.

The reference signal change circuit 25 calculates the average of the reference signal B and the average offset voltage calculated by the average offset calculation circuit 23. The calculated average value is given as a reference signal B' to the adjustment signal generation circuit 27 and the reference signal change circuit 25 of the next stage IC. Therefore, the reference signal @B is the average offset voltage of the preceding IC output from the reference signal changing circuit 25 of the preceding IC. Na J3! The single signal B may be weighted and the average value of the signal B and the average offset voltage may be calculated.

The adjustment signal generation circuit 27 is an average offset calculation circuit 23
After receiving the average offset voltage and the reference signal B- calculated in the above, an adjustment signal is generated using the reference signal @B- from the average offset voltage. This adjustment signal corresponds to a method of adjusting the offset voltage, which will be described later.

In such a configuration, the offset voltage is adjusted during the vertical synchronization period α and horizontal synchronization period β shown in FIG. 26(B). First, the reference signal A applied to the input image signal is sampled and held in the S/8 circuit sequentially or all at once, and is applied to the average offset calculation circuit 23 via the output circuit 17. The reference signal A sampled and held and given to the average offset calculation circuit 23 is the M simplex QA given directly to the average offset calculation circuit 23.
The average value of the difference between the two is calculated, and the average offset voltage is calculated. The average offset voltage is determined by the adjustment signal generation circuit 27.
and is adjusted according to the reference signal 8' provided from the reference signal changing circuit 25. As a result, the adjustment signal generation circuit 27 provides the drive adjustment circuit 21 with an adjustment signal that reduces the difference with the offset voltage of the preceding IC.

The offset voltage is adjusted by this adjustment signal.

In this embodiment, since adjustment is made to reduce the difference in offset voltage between each IC, there is no need to change the offset voltage significantly, and the adjustment method is extremely simple. Further, the ICra may be adjusted only around the boundary between each IC. In such a case, the adjustment will be even simpler.

Next, a specific method for adjusting the offset voltage will be explained using the drawings.

When adjusting the input image signal FIG. 4 shows an embodiment in which the input image signal is adjusted.

This simply applies an adjustment voltage to the input line of the input image signal for each IC to adjust the entire output of each IC. That is, the adjustment signal adjusted by the addition circuit 31 so that the difference between the average offset voltage and the reference signal B- becomes small is added to the input image signal. Therefore, the adjustment signal generation circuit 27 calculates the difference between the average offset voltage of the IC and the reference signal 8', inverts the sign, and outputs the difference as an adjustment signal.

The characteristics of this method are that each output within the IC is adjusted at the same time and does not increase the variation between outputs, so it is easy to design, and the adjustment can be made with one adder circuit 31 for each IC, so the circuit The configuration is extremely simple, the adjustment time is short, and the adjustment can be made reliably.

<When changing the ground potential of the hold capacitor> FIG. 4 is a diagram showing an example in which the ground potential of the hold capacitor 15 of the S/8 circuit is changed.

When the input image signal is sampled and held in the circuit, the output voltage of each S/8 circuit changes overall. Utilizing this, the entire output of each IC is adjusted by adding the adjustment signal 9 to the ground potential.Therefore, the adjustment signal is
The difference between the average offset voltage at and the reference signal B- is adjusted to be small. Therefore, the adjustment signal generation circuit 27 calculates the difference between the average offset voltage at the IC and the reference signal B', inverts the sign, and outputs the difference as an adjustment signal. Furthermore, timing for changing the ground potential is also generated. This timing is such that after the input image signal is sampled and held by the S/TO 1 circuit, the ground potential of the conching 15 for holding is changed.

This method provides the same effect as the embodiment shown in Figure 3)
I can do it.

When adjusting the dimension of a hold capacitor> FIG. 6 is a diagram showing an example of the configuration of an S/8 circuit.

The S/8 circuit is composed of a switch transistor 33 and a conching 15 for holding. The offset voltage of the S/8 circuit depends on the dimension of capacitor 15. That is, as the dimension becomes larger, the offset voltage becomes smaller, and as the dimension becomes smaller, the offset voltage becomes larger. In this embodiment, by adjusting the dimension of this capacitor 15, variations in the output of each IC are adjusted.

FIG. 6 is a diagram showing an embodiment in which the dimension of the hold capacitor 15 is adjusted.

This embodiment is constructed by connecting switch transistors 37 in series whose conduction is controlled by a conversion circuit 35, and connecting a microcapacitor 39 to the series connection point. The dimension of the capacitor 15 is finely adjusted by selecting one of the micro capacitors 39 closer to the capacitor 15 using the output signal from the conversion circuit 35. One conversion circuit 35 may be provided for each IC. The conversion circuit 35 converts the number of microcapacitors 39 to be used according to the adjustment signal. At this time, the conversion circuit 35 controls the conduction of the switch transistor 37 so as to select the microcapacitor 39 closer to the capacitor 35.

The adjustment signal is the average offset voltage and reference signal @
The offset voltage is compared with the reference signal B- and the offset voltage is increased or decreased so as to approach the reference signal B-.

This method involves adjusting each output within the IC, and can also be developed into a method for adjusting variations between outputs. Even in this case, each IC only needs to have one conversion circuit 35, and adjustment can be made one by one.

Further, the micro capacitor 39 may utilize the parasitic capacitance of the selection switch transistor 39, and in such a case, there is no need to add the micro capacitor 39, so the circuit scale and circuit configuration can be simplified.

Case in which the dimension of the switch transistor 33 is adjusted> FIG. 7 is a diagram showing an embodiment in which the dimension of the switch transistor 33 is adjusted.

The offset voltage of the 878 circuit is switch transistor 3
(The larger the dimension t, the larger the offset voltage becomes; the smaller the dimension, the smaller the offset voltage becomes.) In this embodiment, in addition to the main switch transistor 33, In addition, a microtransistor 41 which also serves as a selection switch transistor is connected in parallel. By selecting the microtransistor 41 using the output signal from the conversion circuit 35, the dimension of the switch transistor 33 is finely adjusted.

If the microtransistor 41 is not used (the transistor is in an off state), the dimension of the switch transistor 33 is not affected. When the microtransistor 41 is used (the transistor is in an on state), the dimension of the switch transistor 33 increases. In this way, by changing the dimension of the switch transistor 33 and changing the parasitic color, etc., the offset voltage is adjusted.

One conversion circuit 35 may be provided for each IC. Conversion circuit 35
converts the dimension of the switch transistor 33 into the number of micro transistors 41 to be adjusted according to the adjustment signal, and outputs the number of switch pulses. The adjustment signal compares the average offset voltage of the IC with the reference signal B' and increases or decreases the offset voltage so as to approach the reference signal @B-.

The feature of this embodiment is that each output within the IC is adjusted individually, and furthermore, it can be developed into a method for adjusting variations between outputs within the IC. Even in this case, it is sufficient to have one conversion circuit 35 for each 10,
Just adjust them one by one. In addition, the dimension of the switch transistor can be adjusted using the microtransistor 41.
Since this can be done by selectively using or not using as a switch transistor, it can be realized with a simple circuit configuration.

When adjusting the rise and fall times of the switch panel by minutely changing> FIG. 8 shows an example of the configuration of the shift register 11, which is a switch pulse generation circuit. The shift register 11 is composed of an open circuit inverter 43.

FIG. 9 shows a configuration example and operational functions of the clocked inverter 11. By adjusting the dimension of the output transistor 45 of the closed inverter 11 in this way (the parasitic capacitance and on-resistance of the transistor change), the rise and fall times of the switch pulse can be finely adjusted.

The offset voltage of the 878 circuit increases or decreases depending on the rise and fall times of the switch pulse. The offset voltage of the 878 circuit using 0MO8 becomes larger or smaller depending on the order in which the switches are turned off. offset voltage will be smaller). Also, the offset voltage of the S/T1 circuit using a single transistor is the rise of the switch pulse,
It becomes larger or smaller depending on the fall time. It is determined by the size ratio of the hold capacitor and the capacitor on the input image signal line side, but in this case,
Since the capacitor on the input signal line side is larger,
As the change time increases, the offset voltage decreases,
If there is a sudden change, the offset voltage will become thicker.

FIG. 10 is a diagram showing an embodiment in which the dimension of the output transistor is adjusted. In this embodiment, in addition to the main output transistor 45, a microtransistor 47 which also serves as a selection transistor is connected in parallel with each output transistor 45. By selecting the microtransistor 47 using the output signal from the conversion circuit 49, the dimension of the output transistor 45 is finely adjusted. If the microtransistor 47 is not used (the transistor is off), the dimension of the output transistor 45 is not affected. Microtransistor 47
When the output transistor 45 is used (input is applied to the transistor), the dimension of the output transistor 45 becomes large.

It is sufficient that each IC has one conversion circuit 49. Conversion circuit 49
converts the number of microtransistors 47 to be used according to the adjustment signal, and outputs a signal corresponding to the number of microtransistors 47 to be used. The adjustment signal compares the average offset voltage of the IC with the reference signal B-, and increases or decreases the offset voltage so as to approach the reference signal B-.

The feature of this method is that each output within the IC is adjusted individually, and it can also be developed into a method for adjusting variations among outputs within the IC. Even in this case, each IC only needs to have one conversion circuit 49, and adjustments can be made one by one. Since the dimension of the output transistor 45 can be adjusted depending on whether or not a microtransistor is used as the output transistor, it can be realized with a simple circuit configuration.

When adjusting the offset voltage of the output circuit> FIG. 11 shows an example of the configuration of the output circuit 17. This output circuit 17 is
It is assumed that the amplifier is composed of a differential amplifier with a gain of 1, and that there is normally no offset voltage between the input and the output. By adjusting the dimensions of the symmetrical transistor pair 51 and 53 of the output circuit 17, the offset voltage can be finely adjusted.

When the current 1 ds flowing through the transistor pair 51 is the same, if the dimension of the transistor 51 on the input signal side is larger, the offset voltage will be larger, and if the dimension of the transistor 53 on the output signal side is larger, the offset voltage will be becomes smaller.

Furthermore, when the dimensions of the input and output transistors 51 and 53 are equal, if the current 1ds flowing to the input signal side is large, the offset voltage will be large, and if the current 1ds flowing to the output signal side is large, the off-hit voltage will be small. .

FIG. 12 is a diagram showing an embodiment in which the dimension of the transistor 53 is adjusted. In this embodiment, in addition to the main transistor 53, a selection transistor 55
Microtransistors 57 connected to each other are connected in parallel. By selecting the microtransistor 57 using the output signal from the conversion circuit 59, the transistor 5
Fine-tune dimension 3. Microtransistor 5
7 is not used (the selection transistor 55 is off), the dimension of the transistor 53 is not affected. When using the microtransistor 57 (selection transistor 55 is on), the transistor 53
The dimension of becomes larger.

It is sufficient that each IC has one conversion circuit 59. Conversion circuit 59
outputs a selection signal for the number of microtransistors 57 to be used in accordance with the adjustment signal. The adjustment signal compares the average offset voltage of the IC with the reference signal B-, and increases or decreases the offset voltage so that it approaches the reference signal B-.

Also, l ds flowing through the symmetrical transistors 51 and 53
, l ds' may be adjusted by adjusting the dimension of the current mirror transistor 61, which is a current source, and the adjustment may be performed in the same manner.

The feature of this method is that each output within the IC is adjusted individually, and furthermore, it can be developed into a method for adjusting variations among outputs within the IC. Even in this case, each IC only needs to have one conversion circuit 59;
You just have to adjust it one by one.

FIG. 13 is a diagram showing the configuration of a second embodiment of the present invention. In the drawings shown below, the same reference numerals as in FIG. 1 have the same functions, and the explanation thereof will be omitted. The feature of this second embodiment is that, in contrast to the first embodiment, as shown in FIG. B, and the adjustment signal generation circuit 65 generates an adjustment signal according to the adjustment method from the reference signal B and the average offset voltage of each IC. The specific method for adjusting the offset voltage is as follows:
This is similar to the first embodiment. Therefore, even in this embodiment, the same effects as in the first embodiment can be obtained.

FIG. 15 is a diagram showing the configuration of a third embodiment of the present invention. The feature of this third embodiment is that the sampled and held input image signals are averaged by an average offset calculation circuit 67, and the input image signals are averaged by a reference signal generation circuit 69 to generate a reference signal A. Then, the adjustment signal generation circuit 71 generates an adjustment signal according to the adjustment method from this reference signal and the output of the average offset calculation circuit 67 to adjust the offset voltage.

The specific method for adjusting the offset voltage is the same as in the first embodiment. Therefore, the adjustment signal generation circuit 71 outputs adjustment signals according to each of the adjustment methods described above.

In this third embodiment, since the offset voltage is adjusted to be small for each IC, accuracy can be improved. Furthermore, since adjustment of each IC1ljffi can be performed for each IC, the number of wiring between the ICs 10 and 10 is reduced, and the circuit configuration can be simplified.

Next, a specific example of the configuration of the adjustment signal generation circuit 71 in the third embodiment will be explained using FIGS. 16 to 18.

FIG. 16 is a diagram showing an example of the configuration of the adjustment signal generation circuit 71. In FIG. 16, the difference between the average sample and hold output sampled and held by the S/H circuit and averaged by the average offset calculation circuit 67 and the reference signal Δ is calculated with the switch 73 in the closed state and the switch 75 in the open state. Accumulates in condenser 75. Then switch 73
With the capacitor 7 in an open state and the switch 75 in a closed state,
The charges accumulated in 7 are applied to an operational amplifier 79.

At this time, if the average sample hold output is larger than the reference signal Δ, the output of the operational amplifier, or the adjustment signal, changes to a negative value, and if it becomes smaller, it changes to a positive value. In this manner, the difference between the sample hold output and the reference signal A is extracted as an adjustment signal, and this adjustment signal is fed back to the drive adjustment circuit 21 to adjust the offset voltage according to the adjustment method described above.

When adjusting the offset voltage using such an adjustment signal, the adjustment of the offset voltage is performed gradually with feedback, so there is no possibility of over-adjustment, and the accuracy improves over time.

Note that, as shown in FIG. 17, the reference signal A may be directly applied to the operational amplifier 79. In such a case, the number of switches is reduced and the configuration becomes simple.

FIG. 18 is a diagram showing another example of the configuration of the adjustment signal generation circuit 71. In FIG. 18, the average sample and hold output and the reference signal A are provided to a comparator 81 for comparison, and the comparison result is provided to a 7-tube down counter 83. The up/down counter 83 counts down by one from the previous value if the average sample hold output is larger than the reference signal A as a comparison result, and counts up by one if it is smaller. The count value of the counter 83 is converted into an analog signal by the D/A conversion circuit 85 and fed back to the drive adjustment circuit 21 as an adjustment signal.

Even when the offset voltage is adjusted by generating the adjustment signal in this manner, the same effects as the embodiments shown in FIGS. 16 and 17 can be obtained.

FIG. 19 is a diagram showing the configuration of a fourth embodiment of the present invention. The feature of this fourth embodiment is that an adjustment signal generation circuit 87 is provided corresponding to each "S/1" circuit to adjust the offset voltage for each input image signal to be sampled and held. It's because I did it.

In this embodiment, the adjustment signal generation circuit 87 calculates an offset voltage from the sample-and-hold output sampled and held and given via the output circuit 17 and the reference signal A, and uses the reference signal B from this offset voltage. to generate an adjustment signal according to the adjustment method. In such an embodiment, the same effects as in the first embodiment can be obtained, and the offset voltage can be adjusted for each pixel.

The specific adjustment method is shown in FIGS. 3 to 12 in the first embodiment.
The method is similar to that shown in the figure. That is, when adjusting the input image signal, as shown in FIG. 20, an adder circuit 31 is provided corresponding to each S/8 circuit, and when the ground potential of the hold capacitor 15 is changed. As shown in FIG. 21, an adjustment signal is applied to each hold capacitor 15.

On the other hand, in the case of the embodiment using the conversion circuit shown in FIGS. 5 to 13, if each adjustment result is stored and adjustments are made sequentially, the conversion circuit can be applied to one IC. It becomes possible to use it as a walking stick, and the circuit size does not increase.

FIG. 22 is a diagram showing the configuration of a fifth embodiment of the present invention. The feature of this fifth embodiment is that, in contrast to the fourth embodiment, a reference signal B is generated by averaging the average offset voltage of each IC as shown in FIG. The adjustment signal generation circuit 89 generates an adjustment signal according to each adjustment method from B and each sample and hold output, and adjusts the offset voltage. Even in such an embodiment, the same effects as in the fourth embodiment can be obtained.

FIG. 23 is a diagram showing the configuration of a sixth embodiment of the present invention. The feature of this sixth embodiment is that, in contrast to the fourth embodiment, the reference signal A generated by the generation circuit 69 and the respective sample and hold outputs are converted to the reference signal used in the third embodiment. The purpose is to generate an adjustment signal from the adjustment signal generation circuit 91 to adjust the offset voltage. The specific configuration of the adjustment signal generation circuit 91 is similar to that shown in FIGS. 16 to 18. In such an embodiment, since the offset voltage can be adjusted to be small for each sample-and-hold output, the accuracy can be improved overall.

In this way, according to the embodiment described above, the variation in the average value of each offset voltage is adjusted, so that the accuracy of the X drive circuit is improved. Also,
Since the unique characteristics of each tC are also adjusted, it is no longer necessary to use chips with the same loft and wafer, improving yield.

Furthermore, even if the offset voltage changes over time, the offset voltage is successively adjusted, so it is effective even against offset voltages that fluctuate due to temperature changes and the like.

Further, since it is not necessary to reduce the off-cell I-ffi pressure itself, the holding capacitor can be made smaller. This makes it possible to realize fast driving without increasing the circuit scale. Furthermore, when the X drive circuits are arranged to face each other with the display panel 1 in between, it is possible to suppress vertical stripe noise caused by inversion of signal lines or the like.

Note that in the above embodiment, the input image signal is
Although the offset voltage has been described as a digital value, the variation in the average value of the offset voltage can be reduced in the same way as described above. In such a case, the reference signal may be adjusted or shifted when D/A converting the input image signal.

[Effects of the Invention] As explained above, according to the present invention, the adjustment signal that reduces the difference between the average signal obtained by averaging the signal pull hold signals and the first reference signal, or the adjustment signal that reduces the difference between the lean pull hold signal and the first reference signal. Since the offset voltage is adjusted by an adjustment signal that reduces the difference between the difference signal from the reference signal or the average signal obtained by averaging them and the second reference signal,
It is possible to suppress variations in drive signals without increasing the size of the configuration or reducing operating speed. Thereby, it is possible to provide a liquid crystal display driving device that provides easy-to-see display images.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a first embodiment of the present invention, and FIG.
The figure shows an example of driving the liquid crystal, FIGS. 3 to 12 show the configuration of an example of offset voltage adjustment, FIG. 13 shows the configuration of a second embodiment of the invention, and FIG. 14 15 is a diagram showing the configuration of a third embodiment of the present invention, and FIGS. 16 to 1
8 is a diagram showing the specific configuration of the main part shown in FIG. 15, FIG. 19 is a diagram showing the configuration of the fourth embodiment of the present invention, and FIG.
0 to 21 are diagrams showing the configuration of an example of offset voltage adjustment, FIG. 22 is a diagram showing the configuration of a fifth embodiment of the present invention, and FIG. 23 is a diagram showing the configuration of a sixth embodiment of the present invention. 24 to 27 are diagrams showing one conventional example of a liquid crystal display. 11...Shift register 13...Switch circuit 15...Hold capacitor 17...Output circuit 21...Drive adjustment circuit 23...Average offset calculation circuit 25...Reference signal change circuit 27 .65.71.91... Adjustment signal generation circuit 69.
・Reference signal change circuit

Claims (2)

[Claims] (1) A liquid crystal display drive equipped with one or more unit X drive circuits that drive a liquid crystal display by applying an input image signal sampled and held corresponding to each pixel as a pixel signal voltage to each corresponding pixel. In the apparatus, a calculation means for calculating an average signal obtained by averaging at least one sample-and-hold output signal obtained by sampling and holding a first reference signal corresponding to each pixel; and an average signal calculated by the calculation means; an adjustment signal generation means for comparing a first reference signal and generating an adjustment signal for reducing the difference between the two signals; and adjusting an offset voltage of each pixel signal voltage according to the adjustment signal generated by the adjustment signal generation means. 1. A liquid crystal display driving device comprising: an adjusting means for adjusting; and a unit X driving circuit comprising: (2) A liquid crystal display drive equipped with one or more unit X drive circuits that drive the liquid crystal display by applying sampled and held input image signals corresponding to each pixel as pixel signal voltages to the corresponding pixels. In the apparatus, calculating a difference signal between the first reference signal and at least one sample-and-hold output signal obtained by sampling and holding the first reference signal corresponding to each pixel, and an average signal obtained by averaging them. means, a reference signal generating means for generating a second reference signal by averaging a plurality of said average signals, and a difference signal or an average signal calculated by said calculating means and a second reference signal generated by said reference signal generating means. Adjustment signal generation means for comparing reference signals and generating an adjustment signal that reduces the difference between both signals; and adjusting the offset voltage of each pixel signal voltage in accordance with the adjustment signal generated by the adjustment signal generation means. 1. A liquid crystal display driving device comprising: a unit X driving circuit; and a unit X driving circuit.