JPH02158853A - Bus control system - Google Patents

Abstract

PURPOSE:To allow another unit to continuously use a bus without exerting influence upon the bus even when a part of units connected to the bus generates a fault by allowing only a permitted unit to send a response. CONSTITUTION:At the time of receiving a request BREQ from a transfer control circuit 1, a bus using right control circuit 3 generates a permission BRAM to a master and a unit 100-1 sends information to a data bus 200-1 and also sends a bus start BSTT to a bus control signal bus 200-2. At the time of receiving the BSTT, a bus monitoring circuit 10 generates a permission BFRS for a slave to the unit 100-2 so that a response can be sent from the unit 100-2 to the unit 100-1. When a fault is reported by the response during the sending of its own information, the unit 100-1 quickly generates a transfer end CMPT to release the line. Consequently, even when a fault is generated in a part of the units connected to the bus, the other unit can continuously use the bus without exerting its influence upon the bus.

Description

[Detailed description of the invention] 〔overview〕 As multiple units are linked together on a line.

Equipped with a bus arbiter that issues bus usage rights.

Regarding the bus control method that performs bus control under the so-called sprint method.

The purpose is to allow other units to continue using the bus without affecting the bus even if some units connected to the bus fail.

Create a response line within the above line.

The bus arbiter and slave side units mentioned above.

The system monitors the error state of the data being transferred, and in the event of a failure, it is configured to notify the above unit of this fact, and to abort the data transfer in which the failure occurs, and the bus arbiter and the unit A permission line was created between them, and the configuration was configured so that only units that received permission could send responses.

[Industrial application field]

The present invention relates to a bus control system, and more particularly to a bus control system in which a plurality of units are connected on a line, a bus arbiter is provided for issuing bus usage rights, and the bus is controlled under a so-called sprint system.

Regarding data transfer under the sprint method.

When the masked unit releases the line that issues commands to the slave side, and the slave unit completes the specified processing.

The slave side then acts as a mask and transfers the data to the other party. This improves bus usage efficiency.

[Conventional technology]

FIG. 4 shows a conventional configuration, and FIG. 5 shows a conventional time chart.

In FIG. 4, 100-1.100-2. . . . represents a unit, 200 represents a line, and 300 represents a bus arbiter. Furthermore, 1 is a transfer control circuit, 2 is a bus use right issue request receiving flip-flop, 3 is a bus use right control circuit, 4 is a bus use right permission receiving flip-flop, 5 is a transmitting/receiving register, and 6 is a gate.

7 is a transmission/reception register, and 8 is a response control circuit.

9 is a transfer end (bus complete) reception flip-flop, 10 is a bus monitoring circuit, and 200-1 is a data
Bus 200-2 represents a bus control signal bus. Needless to say, each unit is 100-1°100
-2. The configurations in... are the same configurations and perform the same processing in actual prizes.

Now assume that unit 100-1 requests data transfer from unit 100-2. In this case, as will become clearer with reference to the time chart shown in FIG.
The bus right control circuit 3 in the bus arbiter 300 receives the request (BREQ) and returns a permission (BGRNT) when granting the bus right. The permission (BGRNT) turns on the gate 6 and is taken into the transfer control circuit 1. Needless to say, the bus right control circuit 3 issues the above-mentioned permission (BGRNT) after processing conflicts with bus right requests from other units.

In unit 100-1, transfer control circuit 1 sends the information prepared on transmission/reception register 5 onto line 200. Information is sent to the data bus 200-1 in the order of command, address, and data, and in synchronization with the sending of the command, a bus indicating the start of the bus sequence is sent on the bus control signal bus 200-2 for 1τ.・Start (BSTT)
Output.

During the command, the unit that is currently masked) 10
0-1 and the unit 100-2 that should become a slave
Each unit 100-i connected to the 0 line 200 on which D is displayed monitors the contents of the bus 200-1 and the contents of the bus 200-2, and in this case, the unit 100-2 When detects its own ID, it operates as a slave.

The unit 100-1 serving as a mask issues a transfer end (BCPT) in synchronization with the last transfer data to be transferred. Based on this, the bus arbiter 300 drops the grant (BGRNT) and requests from other units (BGRNT).
REQ) is accepted. During this time, the bus monitoring circuit 10 monitors errors etc. on the bus, and the unit 100
For example, the bus monitoring circuit 10 sends a status S to the data bus 200-1 as shown in FIG. The unit 100-1, which has become a mask, receives the status S.

Know whether the previous data transfer was successful or not.

[Problem to be solved by the invention]

In the case of the above-mentioned conventional configuration, since the sprint method is adopted, when the unit 100-1 serving as a mask finishes transmitting the information to be transmitted by itself, the occupation of the line 200 is temporarily released. This prevents the three lines 200 from being occupied by one unit for an undesired long period of time.

However, problems still remain. That is, even if an error occurs in the data transfer indicated by the arrow 2 in the time chart shown in FIG.

The occurrence of a failure is notified at the timing of the status S shown in FIG. 5 after sending out all the data shown in FIG.

Therefore, all the data D is sent out in a so-called wasted manner.

Therefore, it is conceivable to adopt the configuration shown in FIG.

FIG. 6 shows a bus control system configuration based on the premise of the present invention, which is not yet known, and FIG. 7 shows a time chart in this case.

In the following description, for convenience, the structure shown in FIG. 6 will be considered as a conventional structure. Turn as shown in Figure 6! 2
During 00, the response line 200-3 is established and after the bus supervisory circuit 10 receives 9 bus start (BSTT), the slave unit 100-
2 can be sent on response line 200-3.

Then, from the unit 100-1 to the unit +00-
Response line 200-2 indicates whether an error occurred in the transferred data.
Responses RC, RA, RD via 3.

It will be returned as...

Although FIG. 7(A) shows a case where no error occurs, for example, if an error occurs during transmission of command C and the error is notified by response RC, the unit 100 serving as a mask -1 is 3τ
Afterwards, it issues a transfer end (BCPT) and bus arbiter 3
00 immediately drops the permission (BGRNT) and then notifies the details of the error with status S. Note that RC, RA, RD, . . . shown in FIG. 7(A) represent responses as a result of receiving information C, A, D, . . . on the data bus.

However, in this case, as shown in FIG. 7(B), if any unit 1 connected on the bus 200
00 causes a failure and operates abnormally, it drives the response line 200-3 completely unrelated to the normal bus sequence as shown in Figure 6, making the entire bus unusable. To.

Because all the units were connected to the response line, it was sometimes impossible to minimize failures. In other words, the slave unit 100-2 clearly has the right to use the bus 200 when the masked unit 100-2
The response will be transferred within the range of bus usage rights held by -1. Unisol l-100-2 as a slave
can transfer information without having to obtain the right to use the bus 200, so in the unlikely event that the slave unit 100-2 malfunctions due to a failure, the mask unit 100-2
There is an inconvenience that the entire bus is affected when an attempt is made to transfer outside the range of the bus usage right of unit 100-1, or when a completely unrelated unit 100 outputs a signal onto the bus 200 due to a failure.

An object of the present invention is to enable other units to continue using the bus without affecting the bus even if some units connected to the bus fail.

[Means to solve the problem]

Figure 1 shows the principle configuration diagram of the present invention with reference numeral 100 in Figure 0.
-1.100-2. . . . is a unit, and 200 is a line.

200-1 is a data bus, 200-2 is a bus control signal bus, and 200-3 is a response line (RLN).
, 200-4 is the transfer end (CMPT) line, 300 is the bus arbiter, 400 is the permission (BGR3, bus ground slave) line, ■ is the transfer control circuit, 3 is the bus right control circuit, 8 is the response control circuit.

10 represents a bus monitoring circuit, and 12 represents a gate.

The transfer control circuit 1 issues a bus usage right issuance request (BREQ) and a transfer end (CMPT), and after receiving bus usage permission for the mask (bus ground master BGRM), sends commands etc. on the 2nd line 200. Send information.

A response line 200-3 is provided in line 200, and bus supervisory circuit 10 performs a bus start (BST)
After receiving the bus (bus ground slave
GRS) and gate 1 in unit 100-2.
2 is turned on to enable the response from unit 100-2 to be sent onto response line 200-3.

[Effect]

Upon receiving the request (BREQ) from the transfer control circuit 1, the bus right control circuit 3 grants permission for masking (BGRM).
emits. Unit) 100-1 receives the permission (BGRM), and the transfer control circuit 1 sends out information onto the data bus 200-1.

At the same time, a bus start (BSTT) is sent onto the bus control signal bus 200-2.

As a result, the slave unit 100-2 receives the information on the bus 200-1. Bus monitoring circuit 10
When receiving the bus star (BSTT), it issues a slave permission (BGR3) to the slave unit too-2.

Response from unit 100-2 to unit 100-
1. That is, bus arbiter 30
Only the unit 100-2 that has received permission (BGR3) for the slave from the response line 200-
3. You can send a response on top.

While receiving the information from the unit 100-1, the unit 100-2 performs an error check on each piece of information received, and sends a response line 200.
-3, the response is sent back.

The unit 100-1 serving as a mask continues to send out information while checking from the above response whether or not each piece of information that it is sending out has been correctly received. When all the information has been sent, the bus right control circuit 3 and the slave unit 1
A transfer end (CMPT) is issued to 00-2 via the transfer end line 200-4.

When unit 100-1 is in the process of sending out its own information, a failure is reported by the response.

It is configured to issue a transfer termination (CMPT) early so to speak, and release one line. After unit 100-2 reports the failure with a response.

As well as knowing that the failure report was successfully forwarded by receiving a Transfer Termination (CMPT).

It is configured to prepare for the suspension of response transmission.

When the bus arbiter 300 receives the transfer end (CMPT), it drops the grant (BGRM) and the grant (BGR8).

Note that even though an error occurred while information was being transferred from UNIF 100-1, a response indicating that the slave unit 100-2 itself is in error due to a failure, etc. In such a case, the bus monitoring circuit 1O, which monitors the status and contents of one line 200, sends out a response indicating an error on behalf of the unit 100-2.

〔Example〕

FIG. 2 shows the configuration of an embodiment of the present invention, and FIG. 3 shows a time chart during normal operation.

It is shown in Fig. 2, the code 100.200.300. 1 to 10 correspond to FIG. 1 or FIG. 4, respectively.

4 is the bus usage permission for the master (BGRM) reception flop, 11 is the bus usage permission for the slave (BGR).
3) Represents the receive flop.

Hereinafter, with reference to FIG. 3, a description will be given assuming that information is transferred to the unit 100-1 and the crab unit 100-2.

When the transfer control circuit 1 issues a request (BREQ).

The bus right control circuit 3 issues permission (BGRM).

The unit 100-1 receives the permission (BGRM), turns on the gate 6, and transfers the information prepared in the transmission/reception register 5 to the line 20 by the transfer control circuit l.
Send on 0. Information is transmitted on the data bus 200-1 in the order of command, address, and data, and in synchronization with the transmission of the command, a bus start (BSTT) indicating the start of the bus sequence is issued for 1τ.

Some commands include unit 1, which is a bus mask.
00-1 and the ID of unit 100-2 to become a slave are displayed, and unit 100-2 takes in the information on data bus 2001, assuming that the information is addressed to itself.

Bus Control Signal Bus Start (BS) on bus 200-2
TT) is received by the bus monitoring circuit 10.

A permission (BGR5) is issued to the slave unit 100-2.

The slave unit 100-2 receives information on the data bus 200-1 every 1τ, and sends a response line 20 to report the status at the time of receiving the information.
Sends a response on 0-3. RC shown in Figure 3,
RA, RD, ... are information C, A, on the data bus.
It represents the response as a result of receiving D, .

The unit 100-1 serving as a mask performs the transfer while confirming that each piece of information has been normally received by the above response every lτ, and synchronizes with the last transfer to transmit the third information.
As shown in the figure, a transfer end (CMPT) is issued. In response, the bus arbiter 300 immediately grants (BG
RM), and after 1τ, permission (BGR3) is also dropped.

When unit too-1 receives a notification that an error has occurred in the response, for example, RA, while transferring information,
The unit 100-1 issues a transfer end (CMPT) after performing processing for 11 minutes. As a result, permission (BC; RM and BGR3) is dropped early. Bus monitoring circuit 1
0 also issues a response on behalf of unit 100-2.

〔Effect of the invention〕

As explained above, according to the present invention, while the unit serving as a mask is sending out individual information, the unit serving as a slave or the bus arbiter issues a response, and when a failure occurs, etc., the bus arbiter issues a response. The release can be carried out early, and it is possible to prevent any unit connected to the bus from causing a failure and issuing an inappropriate response, and to minimize the number of failure points.

300 is the bus arbiter, 400 is the grant line.

Reference numeral 1 represents a transfer control circuit, 3 represents a bus right control circuit, 5 and 7 represent transmission/reception registers, 8 represents a response control circuit, and 10 represents a bus monitoring circuit.

Claims (1)

[Claims] A plurality of units (100) are connected on a line (200) and are provided with a bus arbiter (300) that issues a bus usage right for occupying the line (200), When one of the units (100-1) requests the bus arbiter (300) to issue a bus usage right and obtains permission, it issues information on the line (200) and ), the bus control system is configured to temporarily release the occupation of the data bus (200).
00-1) and a bus control signal bus (200-2),
A response line (200-3) is provided, and the bus arbiter (300) and the plurality of units (100) are connected to each other.
a grant line (400) between the bus arbiter (300) and the data bus (200);
-1), the bus control signal bus (200-2), and the response line (200-3) to monitor the communication status between the units and to stop the communication when a failure occurs. and that only one of the units (100-2) that has received permission from the bus arbiter (300) is configured to send a response on the response line (200-3). Characteristic bus control method.