JPH02159658A - Bus control system - Google Patents

Abstract

PURPOSE:To inform the generation of a fault and the contents of the fault and to execute a bus release in an early stage by constituting the system so that while a master unit is sending out each information by using a response line, a slave unit or a bus arbiter generates a response. CONSTITUTION:The system is constituted so that a response line 200-3 is provided in a line 200, and a bus arbiter 300 and a unit 100-2 of a slave side monitor an error state, etc., of data which is being transferred and encode the contents of a fault together with a fault notice at the time of the fault so that they can be informed to a unit 100-1, and a data transfer in which the fault is generated can be suspended. In such a way, when a fault is generated in the course of a data transfer between each of the units 100-1, 2, a notice of the fault and the contents of the fault are encoded by using the response line 200-3, informed together as information, the data transfer is suspended in an early stage, and the bus use efficiency can be improved.

Description

[Detailed description of the invention] 〔overview〕 As multiple units are linked together on a line.

Equipped with a bus arbiter that issues bus usage rights.

Regarding the bus control method that performs bus control under the so-called sprint method.

When a failure occurs during data transfer between units,
The purpose is to improve bus usage efficiency by using the above response line to code a failure notification and the details of the failure, and notify them together as information so that the data transfer can be stopped at an early stage.

Create a response line within the above line.

The bus arbiter and slave side units mentioned above.

The error status of data being transferred is monitored, and in the event of a failure, the details of the failure are coded together with a failure notification, and the above unit is notified.

The system was configured to be able to abort data transfer when a failure occurs.

[Industrial application field]

The present invention relates to a bus control system, and more particularly to a bus control system in which a plurality of units are connected on a line, a bus arbiter is provided for issuing bus usage rights, and the bus is controlled under a so-called sprint system.

Regarding data transfer under the split method.

When the masked unit issues a command to the slave side, it temporarily releases the line, and when the slave unit completes the specified processing.

The slave side then acts as a mask and transfers the data to the other party. This improves bus usage efficiency.

[Conventional technology]

FIG. 5 shows a bus control system configuration based on the premise of the present invention, which was filed together with the present invention but has not yet become publicly known, and FIG. 6 shows a time chart for the conventional case. In the following description, for convenience, the configuration shown in FIG. 5 will be considered as a conventional configuration.

In FIG. 5, 100-1.100 to 2. . . . are units, 200 is a line, and 200-1 is a data unit.
The bus 2002 is a bus control signal bus, 200-3 is a response line, and 300 is a bus arbiter. Furthermore, 1 is a transfer control circuit, 2 is a bus usage right issue request reception frisive flop 7, and 3 is a bus usage right control circuit.

4 is a bus usage permission reception flip-flop, 5 is a transmission/reception register, 6 is a gate, 7 is a transmission/reception register, 8 is a response control circuit, and 9 is a transfer end (bus complete) reception flip-flop.

10 represents a bus monitoring circuit, 11 represents a bus use permission reception flip-flop, and 12 represents a gate.

Needless to say, each unit is 100-1,100-
2. . . . have substantially the same configuration and perform the same processing.

Now assume that unit 100-1 requests data transfer from unit 100-2. In this case, as will become clearer by referring to the illustrated time chart in FIG.
Transfer control circuit l of 100-1 requests (BRE
Q), the bus right control circuit 3 in the bus arbiter 300 receives the request (BREQ), and when granting the bus right, issues a bus permission (bus ground).
Mask BGRM) is returned. The permission (BGRM) turns on the gate 6 and is taken into the transfer control circuit l. Needless to say, the bus usage rights system 'a circuit 3 handles conflicts with bus usage rights requests from other units, and then
Issue the above permission (BGRM).

In the unit 100-1, the transfer control circuit 1 sends the information prepared on the transmitting/receiving register 5 onto the line 200. Information is sent to the data bus 200-1 in the order of command, address, and data, and in synchronization with the sending of the command, a bus control signal is sent to the bus 200-2 for a period of lτ.
Outputs bus start (BSTT) indicating the start of the sequence. The bus monitoring circuit 10 performs a bus start (BS)
TT) and 1τ later, it sends a bus use permission (bus ground slave BGRS) to the slave unit 100-2 and turns on the gate 12.

During the command, Unit 10, which is currently masked,
0-1 and the unit 100-2 that should become a slave
D is displayed. Each unit 100-i connected to the line 200 stores the contents of the bus 200-1 and the bus 2
00-2, and in this case, when unit 100-2 detects its own ID, it starts operating as a slave.

The unit 100-1 serving as a mask issues a transfer end (BCPT) in synchronization with the last transfer data to be transferred. Based on this, the bus arbiter 300 drops the grant (B G RM) and after lτ, the bus arbiter 300 drops the grant (B
R3) and accepts requests (BREQ) from other units. During this time, the slave side UNISO 100-2 and the bus monitoring circuit 10 monitor errors, etc. on the bus, and the unit 100-1 to the unit 100-2
Whether an error or the like has occurred in the data transferred during the transfer is returned as a response RC, RA, RD, . . . via the response line 200-3.

Figure 6 shows the case where no error has occurred, but as shown in Figure 7, for example, if an error occurs during transmission of command C and the error is notified by response RC, it becomes a mask. unit 10
0-1 issues a transfer end (BCPT) after 3τ, the bus arbiter 300 immediately drops the grant (BGRM), then drops the grant (BGR5), and after releasing the bus, the slave unit in turn Acts as a mask and notifies status S.

[Problem to be solved by the invention]

In the case of the above-mentioned conventional configuration, since the sprint method is adopted, when the unit 100-1 serving as a mask finishes transmitting the information to be transmitted by itself, the occupation of the line 200 is temporarily released. In addition, responses that are sent back sequentially are examined to release the occupation of the line 200 at an early stage. This prevents one line 200 from being occupied by one unit for an undesired long period of time.

However, problems still remain. That is, in the time chart shown in FIG. 7, for example, even if an error occurs in the transfer of command C, after the response RC indicating the error is sent, the status S will be notified in the new data transfer. However, detailed information about the failure is not known until the status S is notified.

In the present invention, when a failure occurs during data transfer between units, the failure notification and the details of the failure are coded as shown in Table 1 using the response line, and the information is sent as - The purpose of this system is to improve bus usage efficiency by notifying the client and stopping the data transfer at an early stage.

[Means to solve the problem]

FIG. 1 shows a basic configuration diagram of the present invention. Code 100 in the diagram
-1.100-2. . . . is a unit, and 200 is a line.

200-1 is a data bus, 200-2 is a bus control signal bus, and 200-3 is a response line (RLN).
, 1 is a transfer control circuit, 3 is a bus right control circuit, 8 is a response control circuit, 10 is a bus monitoring circuit, 12 is a gate, and 13 is an encoder, which has responses RA, RC, and R.
This indicates that information for notifying the content of the failure is inserted into D.

The transfer control circuit 1 issues a 9 bus usage right issue request (BREQ) and a transfer end (BCP T), and after receiving a bus usage permission (bus ground master BGRM), 2
Information such as commands is sent over the line 200.

A response line 200-3 is provided in line 200, and a bus supervisory circuit IO detects the bus start (BST)
Unit 1, which has become a slave, after receiving T)
Permitted for 00-2 (bus ground slave BG
R3) and gate 12 in unit 100-2.
is turned on, allowing the response from unit 100-2 to be sent on response line 200-3, including the details of the failure.

[Effect]

Upon receiving a request (BREQ) from the transfer control circuit 1, the bus right control circuit 3 issues a permission (BGRM). Upon receiving the permission (BGRM), the transfer control circuit 1 sends information onto the data bus 200-1, and also sends a bus start signal (BSTT) onto the bus control signal bus 200-2. ) is sent.

As a result, the slave unit 100-2 receives the information on the bus 200-1. Bus monitoring circuit 10
When receiving the bus start (BSTT), it issues permission (BGR) to the slave unit 100-2.
3) to enable unit 100-2 to send a response to unit too-1.

Unit 7) While receiving information from unit 100-1, unit 100-2 performs an error check on each piece of information received, and responds to response line 2.
A response is sent back via 00-3.

When a failure occurs, the encoder 13 encodes the failure occurrence notification as well as the detailed contents of the failure as shown in Table 1 in the response and adds 1 to the code.

[Explanation of terms 1 NOTIS: For physically unimplemented receiving UNIT.

I went to bus operation.

Alternatively, the transceiver of the bus group of the receiving side UNIT or the receiving side 11NIT is in a blocked state.

AfJl: Send (lI!1UNIT sent data';
'4r successfully received. Upon response transfer, the status is returned.

ACK2: The sending unit successfully received the data sent. No response forwarding occurs.

)1[1[! RR: An abnormality in the bus signal was detected in the bus arbiter/bus adapter (bus connection mechanism) or the receiving UNIT.

cMvc/5rsRJc: x If the pass transaction is an initiated transfer, an operation not supported by the receiving tlNIT was received. If the bus transaction is a response transfer, 2 an unexpected status was received.

To BSQC = In the pass transaction, the amount of data sent by the sending side tlNIT and Command/5t
If there is a discrepancy with the amount of data specified by atus, the receiving side UNI
It was detected in T.

PB[lSY: The physical buffer of the bus interface section of the receiving side UNIT is in the BUSY state, and the path transaction cannot be accepted.The sending side UNIT makes a try upon receiving this response status.

This pattern is not abnormal and occurs regularly.

^PER[I: A protocol error was detected on the 7-bit line of the sending UNIT by the bus arbiter or bus adapter (bus connection mechanism).

BAHAIJ: The receiving side UNIT is a logical unit in an expansion case, and the connection state with the expansion case is IIALT. The unit 100-1 that is in the process of confirming whether or not each piece of information that it is sending out has been correctly received, based on the response, continues sending out the information. When all the information has been sent, a transfer end (BCPT) signal is issued.

While the unit 100-1 is transmitting its own information, if a response reports the occurrence of a failure and the details of the failure, the unit 100-1 issues a transfer end (BCPT) early so to speak.
Configured to release the line.

Note that even though an error occurred while information was being transferred from the unit 100-1, the slave unit 100-2 itself did not receive an error message indicating that the error occurred due to a failure, for example. If a response cannot be sent, the bus monitoring circuit 10, which monitors the status and contents of the two lines 200, writes a message indicating the error and its details on behalf of the unit 100-2. Send a response.

〔Example〕

FIG. 2 shows the configuration of an embodiment of the present invention, FIG. 3 is a time chart during normal operation, and FIG. 4 is an exception (N).

T I S: Unit is in a non-mounted state. PBBS
Y: A time chart at the time of occurrence of physical buffer busy state, etc.) is shown.

In FIG. 2, the symbols 100.200.300. 1 to IO correspond to FIG. 1 or FIG. 5, respectively.

Below, with reference to FIGS. 3 and 4, the unit to
The following description assumes that o-1 transfers information to unit 100-2.

When the transfer control circuit 1 issues a request (BREQ).

The bus right control circuit 3 issues permission (BGRM).

The unit 100-1 receives the permission (BGRM), turns on the gate 6, and transmits the information prepared in the transmission/reception register 5 to the line 20 by the transfer control circuit lk.
Send on 0. Information is transmitted on the data bus 200-1 in the order of command, address, and data, and in synchronization with the transmission of the five commands, a bus start (BSTT) indicating the start of the bus sequence is issued for 1τ.

Among the commands, unit 1, which is the bus master,
I between 00-1 and the unit 1002 that should become a slave
D is displayed, and unit 100-2 takes in the information on data bus 2001, assuming that the information is addressed to itself.

Bus Control Signal Bus Start (BS) on bus 200-2
TT) is received by the bus monitoring circuit 10.

A permission (BGR3) is issued to the slave unit 100-2.

The slave unit 100-2 receives information on the data bus 200-1 every 1τ, and sends a response line 200-3 via the encoder 13 to report the state at the time of receiving the information. Sends the response above. RC, RA, RD shown in Figures 3 and 4,
. . . represents a response as a result of receiving information C, A, D, . . . on the data bus.

The unit 100-1 serving as a mask performs the transfer while confirming that each piece of information has been normally received by the above response every 1τ, and synchronizes with the last transfer to transmit the third information.
As shown in the figure, a transfer end (BCPT) is issued. The bus arbiter 300 accordingly grants (BGRM)
, and after ■τ, also drop permission (BGR3).

When the unit 100-1 receives a notification that an error has occurred in the response (RC) and the detailed content of the error as shown in FIG. 4 while transferring information, the unit 100-1
0-1 after performing predetermined processing.

Issue transfer end (BCPT). As a result, permission (B
GRM and BGR5) will be dropped. At this time, needless to say, there is no need to transmit the status S shown in FIG. The bus monitoring circuit 10 also issues a response on behalf of the unit 100-2 when a failure occurs in the unit 100-2 itself.

〔Effect of the invention〕

As explained above, according to the present invention, while the mask unit is sending out individual information, the slave unit or bus arbiter issues a response, and when a failure occurs, etc. By using the response to notify the occurrence of a failure and the details of the failure, the bus can be released at an early stage.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, FIGS. 3 and 4 are time charts for the present invention, and FIG. 5 is a conventional configuration. FIGS. 6 and 7 show time charts in the conventional case. In the figure, 100 is a unit, 200 is a line, 200-
1 is a data bus, 200-2 is a bus control signal bus,
200-3 is a response line, 1 is a transfer control circuit, 3 is a bus right control circuit, 5 and 7 are transmitting/receiving registers, 8 is a response control circuit, 10 is a bus monitoring circuit, 1
2 represents an encoder.

Claims (1)

[Claims] A plurality of units (100) are connected on a line (200) and are provided with a bus arbiter (300) that issues a bus usage right for occupying the line (200), When one of the units (100-1) requests the bus arbiter (300) to issue a bus usage right and obtains permission, it issues information on the line (200) and ), the bus control system is configured to temporarily release the occupation of the data bus (200).
00-1) and a bus control signal bus (200-2),
a response line (200-3), and the bus arbiter (300) is connected to the data bus (20-3).
0-1), the bus control signal bus (200-2), and the response line (200-3) to monitor the communication status between the units and stop the communication at least when a failure occurs. In addition, in the response transmitted on the response line (200-3), the notification about the failure and the details of the failure are encoded and transmitted together as information. bus control method.