JP2504548B2 - Data transfer control method - Google Patents

Description

DETAILED DESCRIPTION [Overview] In a system in which a plurality of units are connected on a line and a bus arbiter that issues a bus use right is provided, data is transferred under a bus control method called a split method. Thus, regarding a data transfer control method in which a request ID is added to each of a plurality of pieces of information that a certain unit transfers to the same partner unit, a plurality of commands that are sent and received with the same partner unit To send and receive information that sends and receives multiple statuses, so to speak, for the purpose of enabling multiple executions, one of the above units may send multiple commands to the same partner unit. A function to write the request ID in each command, and a function that the other unit receives and holds the request ID in each command. And the function of writing the request ID held in each status when the counterpart unit sends a plurality of statuses, and in one of the units, It is configured to have the function of receiving each request ID.

[Industrial applications]

The present invention relates to a data transfer control method, and more particularly to data transfer under a bus control method called a split method in a system having a bus arbiter that issues a bus use right while a plurality of units are linked on a line. The present invention relates to a data transfer control method in which a request ID is added to each of a plurality of pieces of information transferred by a certain unit to the same partner unit.

In the data transfer under the split method, when the master unit issues a command to the slave side, the occupation of the line is temporarily released, and when the slave side unit completes the predetermined processing, the slave side This time it becomes the master and transfers data to the other party. As a result, bus usage efficiency is improved.

For this reason, the above-mentioned split method is adopted in an information processing device in which units such as a processor, a memory, an I / O control device, etc., which constitute the information processing device are linked on a line.

[Prior Art] FIG. 7 shows a conventional configuration, and FIG. 8 shows a time chart of the conventional case.

In FIG. 7, reference numerals 100-1, 100-2, ... Represent units such as a processor, a memory and an I / O controller, 200 is a line, and 300 is a bus arbiter. Further, 1 is a transfer control circuit, 2 is a bus usage right issuance request reception flip-flop, 3 is a bus usage right control circuit, and 4 is a bus usage right permission reception flip-flop.
Flop, 5 is transmission / reception register, 6 is gate, 7 is transmission / reception register, 8 is response control circuit, 9 is transfer end (bus complete) reception flip-flop, 10 is bus monitoring circuit,
Reference numeral 200-1 represents a data bus, and 200-2 represents a bus control signal bus. Needless to say, each unit 100-1,100-
The configurations in 2, ... Are substantially the same configurations and perform the same processing.

It is now assumed that the unit 100-1 requests the unit 100-2 to transfer data. In this case, referring to the time chart shown in FIG.
The transfer control circuit 1 of 100-1 issues a request (BREQ),
In the arbiter 300, the bus use right control circuit 3 receives the request (BREQ) and returns a permit (BGRNT) when giving the bus use right. The permission (BGRNT) is taken into the transfer control circuit 1 when the gate 6 is turned on. Needless to say, the bus use right control circuit 3 processes the contention with the bus use right request from another unit and then performs the above-mentioned permission (BG
RNT) is issued.

In the unit 100-1, the transfer control circuit 1 sends out the information prepared in the transmission / reception register 5 onto the line 200. Information is transmitted to the data bus 200-1 in the order of command, address, and data. In synchronization with the transmission of the command, a bus start (BS
TT) is output.

During the command, the unit 100- which is now the master
The IDs of 1 and the unit 100-2 that should be the slave are displayed. Each unit 100-i connected to the line 200 is
It monitors the contents of bus 200-1 and the contents of bus 200-2,
In this case, when the unit 100-2 detects its own ID,
Start operation as a slave.

The master unit 100-1 issues a transfer end (BCPT) in synchronization with the last transfer data to be transferred. The bus arbiter 300 is authorized based on this (BGRN
T) is dropped and the request (BREQ) from another unit is accepted. During this time, the bus monitoring circuit 10 monitors the bus for errors and the like.

When the unit 100-2 operating as the slave performs the process corresponding to the command, the unit 100-2 which is the master becomes the status corresponding to the command.
Return to 1. The operation in this case is exactly the same as the case shown in FIG. 8 above, with the unit 100-2 acting as a master and the unit 100-1 acting as a slave.

FIG. 9 shows a conventional time chart for explaining the transmission / reception relationship between command and status, in which the master requests the slave to transfer the data from the specified address by the number indicated by the byte count. This is an example. Reference numeral 110 in the drawing represents a command, and 120 represents a status. Various control codes are given to the portions marked with * in the figure.

In FIG. 9, unit 110 sends a command 110- with unit B as the other party.
1 is issued, unit B issues status 120-1 to unit A, and after sending and receiving corresponding to command 110-1, unit A issues command 110-2 with unit B as the other party, Unit B issues status 120-2 to unit A, and after sending and receiving corresponding to command 110-2, unit A issues command 110-3 with unit B as the other party, and so on. It is shown.

[Problems to be Solved by the Invention]

In the case of the above-mentioned conventional configuration, since the split system is adopted, the occupation of the line 200 is once released when the master unit 100-1 finishes transmitting the information to be transmitted by itself. For this reason, the line 200 is undesirably
No longer occupied by one unit.

However, there are still problems. Even if the split method is adopted as described above, in the unit A that issued the command, another command can be issued until the status is returned from the partner unit B in response to the command issued by itself. could not.

An object of the present invention is to enable a plurality of commands to be transmitted / received to / from the same partner unit and a plurality of statuses to be transmitted / received continuously, so to speak, for a plurality of times.

[Means for solving the problem]

FIG. 1 shows the principle configuration of the present invention. Reference numeral 100- in the figure
1, 100-2, ... are units such as a processor, a memory and an I / O control device, 200 is a line, 200-1 is a data bus, 200-2 is a bus control signal bus, and 200-3 is the present invention. Response line (RLN), 1 is a transfer control circuit, 3 is a bus right control circuit, 8 is a response control circuit, 10 is a bus monitoring circuit,
Reference numeral 21 denotes a request ID management unit on the master unit side, and 22 denotes a request ID management unit on the slave unit side.

The transfer control circuit 1 issues a command such as a command on the line 200 after issuing a bus use right issue request (BREQ) and a transfer end (BCPT) and receiving a bus use permission (bus grant master BGRM). Send out.

A response line 200-3 is provided in the line 200, and after the bus monitoring circuit 10 receives a bus start (BSTT), the unit 100-2 that is a slave is permitted (bus Grant slave BGRS)
Turn on the gate in unit 100-2 to turn unit 100-2 on.
Allow the response from to be sent on the response line 200-3.

Request ID management unit 2 in master unit 100-1
In the case of sending a plurality of commands to the same partner unit, 1 is the request ID written in each command and written in each status from the slave side unit 100-2. Corresponds to each request ID in each command issued earlier based on the request ID of.

Request ID in slave unit 100-2
The management unit 22 holds each request ID in each command, and when issuing each of the above statuses, writes each previously held request ID in each status.

[Action]

When the request (BREQ) from the transfer control circuit 1 is received, the bus use right control circuit 3 issues a grant (BGRM). Unit 10
In 0-1, the permission (BGRM) is received, and the transfer control circuit 1 sends information to the data bus 200-1 and also bus start (BSTT) to the bus control signal bus 200-2.
Is sent.

As a result, the slave unit 100-2 receives the information on the bus 200-1. When the bus monitoring circuit 10 receives a bus start (BSTT), it issues a permission (BGRS) to the slave unit 100-2, and the unit 100-2 can send a response to the unit 100-1. To do so.

The unit 100-2, while receiving the information from the unit 100-1, performs an error check or the like on each received information, and returns a response via the response line 200-3.

The unit 100-1, which is the master, continues to send information while confirming whether or not the individual information being sent by itself has been correctly received by the response. When all the information has been sent, the transfer end (BCPT) is issued.

The unit 100-1 is configured to issue a transfer end (BCPT) as soon as possible and release the line when a failure is reported by the response while sending its own information.

It should be noted that, even though an error or the like occurred while the information from the unit 100-1 was being transferred, a response indicating that the slave unit 100-2 itself is in error due to, for example, a failure is sent. If it cannot be sent, the bus monitoring line 1 that monitors the status and contents of the line 200
Instead of the unit 100-2, 0 sends a response indicating an error.

When the unit 100-1 issues a plurality of commands to the same partner unit 100-2, request IDs are assigned to the respective units. The request ID management unit 21 shown in the figure gives the request ID to each command. Then, the slave unit 10 that is the other unit
When the status is returned from 0-2, each request ID described in the individual status is received and associated with each request ID previously assigned.

In the slave side unit 100-2, each request described in each sent command
ID is held. Then, the request ID management unit 22
In returning the above-mentioned individual statuses, each request ID held therein is written in the status.

In the case of the present invention, since the request ID is given, each unit sends one command to the slave unit after issuing one command. It becomes possible to issue other commands one after another without waiting for the corresponding status from the unit to be received.

〔Example〕

FIG. 2 shows the configuration of an embodiment of the present invention, FIG. 3 is a time chart when normal, and FIG. 4 is a time chart when an exception occurs.
The chart is shown.

In FIG. 2, reference numerals 100, 200, 300, 1 to 10 respectively correspond to FIG. 1 or FIG. 7, 11 is a bus use permission (GBRS) reception flip-flop, 12 is a gate, and 13 is 8 inputs and 3 outputs. Represents a concoder.

The unit 10 will be described below with reference to FIGS. 3 and 4.
It is assumed that 0-1 transfers information to the unit 100-2.

When the transfer control circuit 1 issues a request (BREQ), the bus usage right control circuit 3 issues a permission (BGRM). Unit 100-
1 receives the permission (BGRM), turns on the gate 6, and causes the transfer control circuit 1 to transmit / receive the register 5
The information prepared in (1) is transmitted to the line 200. Information is sent to the data bus 200-1 in the order of command, address, and data, and a bus start (BSTT) indicating the start of the bus sequence for 1τ is synchronized with the sending of the command.
Is emitted.

In the command, the unit that is the bus master
The IDs of 100-1 and the unit 100-2 to be the slave are displayed, and the unit 100-2 takes in information on the data bus 200-1 as the information for itself.

Bus control signal Bus start on bus 200-2 (BSTT)
When the bus monitoring circuit 10 receives this, the permission (BRGS) is issued to the slave unit 100-2.

The slave unit 100-2 receives the information on the data bus 200-1 every 1τ, and sends a response line 200-3 via the encoder 13 to report the state when the information is received. Send the response above. RC, RA, RD, ... Shown in FIGS. 3 and 4 represent the response as a result of receiving the information C, A, D ,.

The unit 100-1 which is the master performs the transfer while confirming that each information has been normally received by every 1τ by the above response, and finally, in synchronization, completes the transfer as shown in FIG. BCPT) is issued. Bus arbiter 300
Correspondingly drops the permit (BGRM), and after 1τ, also drops the permit (BGRS).

When the unit 100-1 receives a notification that an error has occurred in the response (RA) shown by the arrow as shown in FIG. 4 while the unit 100-1 is transferring the information, the unit 100-1 performs processing for 1τ. Then, the transfer end (BCPT) is issued. As a result,
As you can see by comparing Figures 3 and 4, the permits (BRM and BGRS) are dropped early. Bus monitoring circuit 10 is also unit 1
Issue a response instead of 00-2.

FIG. 5 shows a time chart for explaining the situation of transmission and reception of commands and statuses in the case of the present invention. Reference numeral 110 in the drawing represents a command, and 120 represents a status. Various control codes are given to the portions marked with * in the figure.

In FIG. 5, unit A issues a plurality of commands 110-1 to 110-4 collectively with unit B as the other party, unit B issues status 120-1 to unit A, and unit B issues It is shown that status 120-2 is issued to unit A, unit B is issuing status 120-3 to unit A, and so on.

FIG. 6 (A) shows the configuration of the main part of one embodiment of the master side, and FIG. 6 (B) shows the configuration of the main part of the one embodiment of the slave side.

Reference numeral 30 in FIG. 6 (A) is a chip bus control unit, which controls a bus (not shown) in the chip. Also, 31
Is a register, 32 is a switch, 33 is a command generator, 34 is a transmission data buffer, 35 is a buffer memory, and 36 is a self ID.
A holding unit, 37 is a transmission control unit, 38 is a multiplexer, 39 is a reception control unit, 40 is a status management unit, 41 is a reception data buffer, 42 is a multiplexer, and 43 is a register.

Further, in FIG. 6 (B), reference numeral 44 is a register, 45 is a multiplexer, 46 is a status creating unit, 47 is a transmission control unit, and 48.
Is a self ID holding unit, 49 is a transmission data buffer, 50 is a switch, 51 is a register, 52 is a chip bus control unit, 53 is a register, 54 is a multiplexer, 55 is a stack area, 56 is a reception data buffer, 57 Is a reception control unit, and 58 is a register.

In FIG. 6A, if I / O command issuance is requested, the chip bus control unit 30 controls the switch 32 to lead the data to the command creation unit 33. In the command creating unit 33, the self ID and the request from the self ID holding unit 36
The command format is adjusted by the request ID from the ID management unit 21 and stored in the buffer memory 35.

In the case of data transfer, the command and address are stored as one set. The request ID is given as a serial number to the same partner unit, and operates as a so-called DMA pipeline. When the serial number reaches the maximum that can be given by the allocated bits, the status becomes a waiting state until the request ID previously allocated is canceled as a result of receiving the status. The timing of adding the request ID depends on the instruction from the transmission control unit 37.
As for the status sent from the slave unit, when the reception control unit 39 determines that the status is the status, the status management unit 40 checks the status and sends the corresponding request to the request ID management unit 21. Instruct to cancel the ID.

The transmission control unit 37 receives the data in the buffer, and the I / O-BU
To get S. When the bus can be acquired, as many commands as exist in the buffer are sent as commands 110-1 to 110-4 shown in FIG.

In the slave unit that has received the command from the master unit, if the reception control unit 57 shown in FIG. 6 (B) determines that it is a command, it is stacked in the stack area 55. The stack consists of FIFO buffers. When the software on the slave side learns that data has been input to the receive data buffer 56, the software in the stack area
Commands are fetched one by one from 55 and the instructions are executed. At this time, the request ID management unit 22 reads and holds the request ID.

When the software finishes the process, it requests data transmission. The transmission control unit 47 attaches data after the status to be transmitted and transmits it. The status creating unit 46 creates and sends a status format using the request ID and the self ID that are held in advance.

〔The invention's effect〕

As described above, according to the present invention, it is possible to successively send a plurality of commands to the same partner unit.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a time chart when normal, FIG. 4 is a time chart when an exception occurs, and FIG. In the case of the present invention, a time chart for explaining the situation of transmission and reception of commands and status, FIG. 6 (A) is a main part configuration of one embodiment on the master side, and FIG. 6 (B) is a slave. FIG. 7 is a conventional configuration, FIG. 8 is a time chart in the conventional case, and FIG. 9 is a time in the conventional case for explaining the transmission / reception relationship between command and status.・ Show a chart. In the figure, reference numeral 100 is a unit, 200 is a line, 1 is a transfer control circuit,
3 is a bus use right control circuit, 8 is a response control circuit, 21, 22
Represents the request ID management unit, respectively.

Claims (1)

(57) [Claims] 1. A plurality of units (100) are connected on a line (200), and a bus arbiter (300) for issuing a bus use right for occupying the line (200) is provided. When one of the above (100-1) requests the bus arbiter (300) to issue the bus usage right and obtains permission, the other unit (100-2) is designated on the line (200). It is configured to issue a command that describes the operation requested for the unit and then release the occupancy of the line (200) once, and the status of the result of the counterpart unit (100-2) handling the command is displayed. When the bus arbiter (300) is requested to issue the bus use right for transmission and the permission is obtained, one of the units (100-1) is designated on the line (200) and the command is issued to the unit. After issuing a status that is the result of dealing with In the bus control system configured to release the occupation of the line (200), one of the units (100-1) is plural for the same one of the counterpart units (100-2). When sending the command of, the request ID management unit (21) that writes the request ID in each command and the request ID written in the status from the partner unit (100-2) A status management section (40) for reading and notifying the request ID management section (21) is provided, and the counterpart unit (100-2) holds a stack area (55) for holding each of the received commands.
And when sending out the above status and fetching and executing the command from the stack area, the request ID management part (21) reads the request ID of the command to be processed and writes the read request ID in each status A data transfer control method characterized in that it has a request ID management section (22) and that each of the above units issues multiple commands in succession to the same partner unit.