JPH02158839A - Data transferring method - Google Patents

Abstract

PURPOSE:To speed up data transferring processing by forming FIFO (First in First out) structure on a memory area when the data transferring processing is performed by interruption. CONSTITUTION:The capacity information 31 of a first data memory area 12, a transferring address 32, a read-out position information 33 and a write-in position information 34 are provided on a second data memory area 13 to control the first data memory area 12. Then, in the case of the rise of an interruption request during data processing, processing operation is executed prior to interruption processing according to the decision of an interruption control part. Namely, the data transferring processing of the FIFO structure can be executed on the memory area 11 by starting by the interruption. Accordingly, internal data is never saved in a stack by the interruption request, and data transferring processing time can be shortened. Thus, data transferring processing efficiency is improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a data transfer method, particularly a method of interrupting the normal flow of a program and performing a data transfer process using an interrupt, internal data generated when the data transfer process is executed using an interrupt is provided. The first in first o
The purpose of this data transfer method is to speed up data transfer processing by forming a 1st to write the transfer data
a data memory area and a second data memory area for managing writing and reading of the first data memory area, and at least the data transfer process is activated by a microinstruction by an interrupt and the first data The method includes writing transfer data into a memory area, and sequentially reading data from the first data memory area starting from the transfer data written first.

[Industrial application field]

The present invention relates to a data transfer method, and more specifically to a method of interrupting the normal flow of a program and performing data transfer processing using an interrupt.

Recent single-chip microcontrollers have a function that interrupts the normal flow of the program and forcibly executes an exception handling program due to internal interrupts caused by internal causes in the microprocessor or main memory, or external interrupts from peripheral input/output devices. There is.

Here, data transfer processing refers to storing external data from the outside into an external memory or outputting external data stored in the external memory to the outside in interrupt processing. Therefore, this differs from internal data transfer processing in which internal data within the CPU is temporarily saved on the stack.

By the way, in data transfer processing using an interrupt, it takes a lot of time to save internal data.

This poses a problem in that it is not possible to speed up data processing.

Therefore, a method is desired in which data is transferred without saving internal data to the stack using hardware.

[Conventional technology]

FIG. 5.6 is an explanatory diagram of a conventional example.

FIGS. 5(a) and 5(b) are explanatory diagrams of a conventional data transfer method.

FIG. 2A is a diagram schematically illustrating a communication data processing system according to a conventional example.

In the figure, 8 is a CPU (Central Processing Unit), which includes an instruction execution section 1, an instruction control section 2, an interrupt control section 3, and a data control section 4. The data control unit 4 includes a program counter 4a, a stack pointer 4b, and other registers 4.
C, an accumulator 4d, etc. Further, 5 indicates an internal bus.

6 is a communication chip, and communication chip A is a received data DI.
It inputs N and outputs external data D21.

The communication chip B inputs external data D22 and outputs transmission data DOT.

7 is an external memory that stores external data 021 and outputs stored external data D22. Due to these, internal data DI and external data D21
．． A communication microprocessor and the like that process data of D22 are configured.

FIG. 2B is a flowchart relating to a conventional data transfer method for a communication microprocessor, etc.

In the figure, the normal flow of a user program is interrupted by an interrupt and is forcibly changed to an exception handling program. In this case, first step P.

An interrupt request is generated from communication chip 8 or B. At this time, the instruction execution unit 1 and the instruction control unit 2 execute step P to save the state of the user program.

The interrupt sequence is activated.

Then, according to the interrupt sequence in step P,
The internal data D1 of the program counter 4a, accumulator 4d, etc. is saved to the address pointed to by the stack pointer 4b.

Next, in step P4, the process moves to the interrupt program, and in step P, the received data DIN of the communication chip A is
is set as external data DI2 and transferred to the external memory 7, and external data D22 in the external memory 7 is set as transmission data DOT of the communication chip B and processed for data transfer.

Then, in step P, start an interrupt sequence,
The internal data DI saved in the stack pointer 4b in step P7 is transferred to the program counter 4a and the achievable emulator 4.
d, thereby restoring the state to the user program.

FIGS. 6(a) and 6(b) are diagrams illustrating problems associated with the conventional data transfer method.

3A shows a counter mode in which external data D21 is transferred to the memory area 7a of the external memory 7 in response to a request from the communication chip A, giving priority to interrupt processing.

This is because, if priority is given to interrupt processing, it will take time to save the internal data D1 to the stack pointer, as in the processing content of step P in FIG.

Therefore, the external data D21 is processed without executing interrupt processing.
is executed with priority to speed up data transfer processing.

In the figure, 7b is a pointer, external memo +J 7
Data transfer area 7C allocated to memory area 7a of
It shows the position of

In counter mode, first receive data D of communication chip A.
IN is set as external data D21 and is transferred to the data transfer area 7c of the external memory 7 one after another via the CPU 8.

Here, when the pointer 7b moves from "start" to "end" and the data transfer area 7C reserved in the memory area 7a becomes full, an interrupt sequence is activated, and the processing from step P in FIG. Moving on to the content.

FIG. 4B shows a counter mode in which external data D22 stored in the external memory 7 is transferred to the outside in response to a request from the communication chip B, giving priority to interrupt processing.

In the figure, when the pointer 7b moves from "start" to "end" and the data transfer area 7C becomes empty, an interrupt sequence is activated and the process moves to step P in FIG. 5 and subsequent processing contents.

In this way, the data transfer area 7C is transferred to the external data D2.
1 and every time the seats become full, an interrupt sequence is activated and it is necessary to set the transfer mode of counters, addresses, etc. At this time, the program counter in CPUB and the internal data DI of the accumulator are temporarily saved to the stack.

[Problem to be solved by the invention]

Therefore, when it becomes necessary to transfer the external data D21 directly from the communication chip A to the communication chip B, according to the conventional example, the first step is to transfer the external data D21 from the communication chip A to the external memory 7. A second counter mode in which the external data D22 is transferred from the external memory 7 to the communication chip B are executed.

Furthermore, an interrupt sequence process is executed between the first and second counter modes.

Therefore, as shown in FIG. 6(a), there is a part that transfers the external data D21 from the communication chip A to the external memory 7, and a part that transfers the data from the external memory 7 to the communication chip B, giving priority to the interrupt handling process. Although it is possible to speed up the data transfer, it takes time for the internal data DI of the accumulator and program counter of the CPU 8 related to interrupt sequence processing to be temporarily saved to the stack, and the data transfer as a whole is slowed down. There is a problem in that it is not possible to increase the speed of the process.

The present invention was created in view of the problems of the conventional example, and eliminates the internal data saving operation that occurs when data transfer processing is executed in counter mode, and performs FIFO (First 1nFirst) operation on the memory area. o
The purpose of the present invention is to provide a data transfer method that makes it possible to speed up data transfer processing.

[Means to solve the problem]

FIG. 1 shows a principle diagram of the data transfer method of the present invention.

This method includes a first data memory area 12 that writes transfer data to a memory area 11 in a data transfer method that performs data transfer processing with priority over interrupt processing when an interrupt request is received during data processing. , said first
a second data memory area 13 for managing writing and reading of the data memory area 12;
The data transfer process is activated by a microinstruction caused by an interrupt, writes transfer data to the first data memory area 12, and writes the transfer data to the first data memory area 1.
The second data memory area is characterized in that the read processing is performed in order from the transfer data that was written first, and the second data memory area has a small amount of data (including the capacity of the first memory area 12, information 31, and transfer address). 32 read position information 33 and write position information 34, the above object is achieved.

[Effect]

According to the present invention, capacity information 31. of the first data memory area 12 is stored in the second data memory area 13 that manages the first data memory area 12. Forwarding address 32. Read position information 33 and write position information 34 are provided.

Therefore, if an interrupt request is made to the CPU or the like during data processing, the next processing operation can be performed in priority to the interrupt processing based on the judgment of the interrupt control unit 14 or the like.

That is, first, the transfer address 32 of the first data memory area 12 is read out, and then it is determined whether to write or read the transfer data.

With this determination, for example, in the case of a write operation, the first data memory area 1 is
The transfer data is stored in the write position No. 2. At this time, the transferred data is sequentially stored in the first data memory area 12, and the contents of the write position information 34 are updated.

On the other hand, in the case of a read operation, based on the read position information 33, the read process is performed starting from the transfer data that was written into the first data memory area 12 first. At this time, the transferred data is sequentially read out to other data memory areas and the contents of the read position information 33 are updated.

Next, it is determined based on the write position information 34 and the read position information 33 that the data transfer process is complete, and other processes are continued.

As a result, PIFo (F
irst! It becomes possible to perform data transfer processing with a structure (n First out).

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

2nd-. FIG. 4 is a diagram illustrating a data transfer method according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating a memory area according to an embodiment of the present invention.

In the figure, 10 is a microprocessor such as a 1-chip microcontroller, and an interrupt control register 14
．． Instruction execution unit 16. Command control unit 17, data control unit 18
and an internal bus 19.

11 is a memory area such as main memory and control registers. 1
2 is a first data memory area, which is a memory data area forming a FIFO8II area.

Transfer data is stored in the FIFOfiJI area. 13
is the second data memory area, and FIFO6Jt area 1
This is a memory data area for managing 2.

The second data memory area 13 has a Panor size 31
．． Buffer address pointer 32. Load pointer 33
．． Store pointer 34. Various modes 35. A buffer disk flipper 36 and a memory address 37 are registered. Here, the transfer data is the data indicated by the memory address 37 that is transferred, and the data loaded from the first data memory area 12 is transferred to the area indicated by the memory address 37. 15 is another data memory area.

Batza size 31 is the size (capacity N) of FIFO area 12, and load pointer 33 is FIF, 0fil.
The store pointer 34 specifies the position from which to read the transfer data stored in the FIFO area 12.
2 specifies the write position where the transfer data is to be stored. In the various modes 35, transfer modes can be set, such as whether priority is given to interrupt processing or data processing. Mode selection is performed by activating an interrupt using the interrupt control register 14.

The buffer disk libter address 36 is, for example, the address of the buffer disk libter of the second data memory area 12 registered. The reason why the second data memory area 12 is divided into two is because the counter mode and F
This is to eliminate unnecessary data areas, which change to 2 or 4 bytes depending on the transfer mode such as IFO mode.

The memory address 37 is a write or read address for another data memory area 15.

FIG. 3 is a flowchart relating to a data transfer method according to an embodiment of the present invention.

In the figure, first, in step P1, normal CPU operation is performed. This is a data processing operation related to the normal flow of a user program, ie, the state before an interrupt request.

Next, in step P2, it is determined whether or not an interrupt request has occurred. Here, if there is no interrupt request (NO), the process returns to step P1 and repeats the processing contents of step P1.

If there is an interrupt request (YES), step P;
to move to.

In step P, it is determined whether or not to transfer. If not transferred, the process moves to step P1□ and a normal interrupt sequence is executed. To transfer, move to P.

In step P4, transfer processing is started. At this time,
A transfer process is activated by a microinstruction such as a microprogram stored in the data control unit 18 via the instruction execution unit 16 and the instruction control unit 17.

Next, in step P, is it FIFO mode?

Determine whether it is in counter mode. Here, in the case of F[FO (ring mode) (YES or A), data transfer processing related to FEFO mode is performed. Note that the data transfer process related to the FIFO mode will be explained in detail in FIG. 4. In case of counter mode (NO), step P
, move to.

In step P&, data transfer processing is performed in a counter mode as in the conventional example.

Furthermore, in step P, various pointers and the like are controlled, and the process moves to step P8, where it is determined whether or not the data transfer process in the counter mode is normal. At this time,
In the case of normal termination (YES), the process moves to step P, where the interrupt is cleared, and in step 15, the CPU operation is returned to. If the termination is not normal (No), the process moves to step pH and processes for abnormal termination are performed.

Next, the process moves to step P1□ to execute an interrupt sequence, followed by step pu3 to process the user's interrupt program, and step P14 to perform interrupt recovery processing.

Next, the process moves to step PIS, and the CPU operation returns to normal program processing before the interrupt request.

FIG. 4 is a flowchart relating to data transfer processing in the FIFO mode according to the embodiment of the present invention.

This is step P5 in the flowchart of FIG.
When using FIFO mode (YES or A
) is the processing content of step P1°. In the figure, first, step P. 1 performs read processing of the buffer disk libter. Here, the buffer disk libter address 36 of the second data memory area 12 is referenced, and the buffer address pointer 32 is set to f! recognized.

Next, in step ptoi, the transfer bit is determined. Here, for example, if the load processing is performed when the transfer bit DIR-1 is set (YES), step P4. ．． to move to. The load process is performed at the read position of PIFO6+l area 12 (
This is the process of reading transfer data from a load point). If the transfer bit is DIR-0 (NO), step P, to perform a store process. , move to. The store process is a process of writing transfer data to a write position (store point) in the FIFOpi area 12.

Here, the store process will be explained first with reference to steps below.

Therefore, in step P1゜, the contents of the memory register are converted to address pointer (BAP) 32 + store pointer 3.
Transfer to the memory area indicated by 4.

Here, the transfer data from the other data memory area 15 is written into the FIFOjl area 12.

Next, in step P1114, the store pointer 34 is set to 1.
Add (increment) by one.

Next, step P. , it is determined whether the store pointer 34 and the buffer size 31 are the same value. If the store pointer 34 and the buffer size 31 become equal (YES), the process moves to step P1°, where "00" is written to the store pointer 34, and step P,
. transition to f. If they are not equal (NO), the process moves to step PLO, and it is determined whether the store pointer 34 and load pointer 33 have the same value.9 If they are equal (YES), an interrupt is executed in step ptes. Status register S■ of the requested resource.

Set SO to “10” and write capacity is “Full”.
” (full). In this case, it is an abnormal termination. In this case, the process moves to step P++ (point CB) in the flowchart of FIG. Execution of the sequence, processing of the user's interrupt program in step P+z, and return processing of the interrupt sequence in step P14 are performed.Then, in step P+s, the CPU operation is returned to.

If the store pointer 34 and the load pointer 33 are not equal (No), it is a normal termination and the process moves to step P in the flowchart of FIG.
This is data transfer processing during store processing related to O mode.

Next, the data transfer process during the load process related to the FIFO mode will be explained.

That is, if the transfer bit DIR=1 in step ploz (YES), the process moves to step P1°, and it is determined whether the load pointer 33 and store pointer 34 have the same value. If the load pointer 33 and store pointer 34 are equal (YES), step PI1
4, sets '01'' in the status register of the resource that requested the interrupt, and informs that the write capacity of FIFO 6J area 12 is "Elf) ty" (vacant). The process moves to step pH (point B) k, performs processing at the time of abnormal termination, then executes the interrupt sequence in step P1□, processes the user's interrupt program in step pts, and performs return processing for the interrupt sequence in step PI4. After that, step PU returns to CPU operation.

If the load pointer 33 and store pointer 34 are not equal in step P109 (No), the step pH
. The contents of the address pointer (BAP) 32+load pointer 33 are transferred to a memory register or the like.

At this time, the transfer data stored in the FIFO8JI area 12 is read out to another data memory area 15 and processed.

Next, in step P Il+, the load pointer 33 is added (incremented) by one.

Next, in step P1□, it is determined whether the load pointer 33 and the buffer size 31 are the same value. If the load pointer 33 and the buffer size 31 are equal (YES), "00" is written to the load pointer 33 in step P1.2. If they are not equal, step PI of the flowchart in FIG. Shift to clear interrupts, shift to step pus, and clear CPU
Return to operation.

As a result, FIFO (First
in First out) is formed.

In this way, the second
The buffer size of the PIFOf+Jj area 12 is stored in the data memory area 13 of 31. Buffer address pointer 32.
A load pointer 33 and a store pointer 34 are provided.

Therefore, if an interrupt request is made to the CPU or the like during data processing, the following data processing operation can be performed with priority over the interrupt processing based on the judgment of the interrupt register 14 or the like.

That is, first, the buffer address pointer 32 of the FIFO area 12 is read out, and then it is determined whether to write or read the transfer data.

Based on this determination, for example, in the case of a write operation, the transfer data is stored in the store point of the F(FOel area 12) based on the store pointer 34.

At this time, the transferred data is sequentially stored in the FIFO area 12 and the contents of the store pointer 34 are updated.

On the other hand, in the case of a read operation, based on the load pointer 33, the read process is performed starting from the transfer data written to the FIFO area 12 first. At this time, the transferred data is sequentially read out to another data memory area 15 and the contents of the load pointer 33 are updated.

Next, it is determined based on the store pointer 34 and load pointer 33 that the data transfer process is complete, and other processes are continued.

As a result, FIFO (Fi
rst in first out) structure can be performed.

In the embodiment of the present invention, the second data memory area 13 for managing the FIFO area 12 is divided into two parts, a buffer disk libter and a service disk libter, but it may be divided into one. Also, load pointer 33 and store pointer 3
A dedicated counter may be provided for the 4th grade. This reduces the burden of microinstructions and further speeds up data transfer processing.

〔Effect of the invention〕

As explained above, according to the present invention, data transfer processing in a FIFO structure can be performed on the memory 6N area by activation by an interrupt.

Therefore, when external data from the outside is directly transferred to the outside as external data by an interrupt request as in the past, internal data such as an accumulator or a program counter is not saved in the storage tank. Therefore, it becomes possible to significantly shorten the data transfer processing time.

This improves the data transfer processing efficiency and makes it possible to speed up the data processing operation of a one-chip microcontroller or the like.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram related to the data transfer method of the present invention, FIG. 2 is a diagram explaining the memory area of the embodiment of the present invention, and FIG. 3 is a diagram related to the data transfer method of the embodiment of the present invention. Flowchart, FIG. 4 is a flowchart related to the transfer process related to the F[FO mode of the embodiment of the present invention, FIGS. 5(a) and (b) are explanatory diagrams related to the conventional data transfer method, Figures (a) and (b) are diagrams illustrating problems associated with the conventional data transfer method. (Explanation of symbols) IO...Microprocessor, 7a, 11...Memory area, 12...First data memory area (FIFO9Jl area), 13...Second data memory area, 31...・Capacity information, 32... Transfer address, 33... Read position information, 34... Write position information, 3.14... Interrupt register (interrupt control unit),
15...Other data memory areas, 1.16...Instruction execution unit, 2.17...Instruction control unit, 4, Engineering 8...Data control unit, 5.19...Internal bus, 4a...Program counter, 4b...Stack pointer, 4c...Other registers, 4d...Accumulator, 6...Communication chip A or B, 7...External memory, 7b...Pointer , 7c...Data transfer area, 8...CPU (central processing unit), DIN...
Reception data, DOT...Transmission data, D2゜D21゜D22...External data, DI...Internal data.

Claims (2)

[Claims] (1) When an interrupt request is received during data processing, the data transfer process takes precedence over the interrupt process.
a data memory area (12), and a second data memory area (13) that manages writing and reading of the first data memory area (12), and at least the data transfer process is performed using an interrupt-based microinstruction. , the first data memory area (12) is activated by writing transfer data, and the first data memory area (12) is sequentially read from transfer data written first. A data transfer method characterized by: (2) Second data memory area (13) according to claim 1
A data transfer method comprising at least capacity information (31), transfer address (32), read position information (33), and write position information (34) of the first memory area (12).