JPH02158133A - Formation of aluminum electrode wiring - Google Patents
Formation of aluminum electrode wiringInfo
- Publication number
- JPH02158133A JPH02158133A JP31208788A JP31208788A JPH02158133A JP H02158133 A JPH02158133 A JP H02158133A JP 31208788 A JP31208788 A JP 31208788A JP 31208788 A JP31208788 A JP 31208788A JP H02158133 A JPH02158133 A JP H02158133A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- electrode wiring
- laser beams
- aluminum electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052782 aluminium Inorganic materials 0.000 title claims abstract description 24
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 title claims abstract description 24
- 230000015572 biosynthetic process Effects 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 6
- 239000011701 zinc Substances 0.000 claims description 5
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims 1
- 229910052725 zinc Inorganic materials 0.000 claims 1
- 238000004544 sputter deposition Methods 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 238000010521 absorption reaction Methods 0.000 abstract description 5
- 239000003990 capacitor Substances 0.000 abstract description 4
- 230000003449 preventive effect Effects 0.000 abstract 2
- 238000002161 passivation Methods 0.000 abstract 1
- 230000008569 process Effects 0.000 description 11
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 2
- 101100327917 Caenorhabditis elegans chup-1 gene Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はＬＳＩにおけるアルミニウム（ＡＩ）電極配線
の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming aluminum (AI) electrode wiring in an LSI.
（従来の技術）
従来、このような分野の技術としては、以下にに示され
るものがあつた。(Prior Art) Conventionally, there have been technologies in this field as shown below.
近年、ＬＳＩの高集積化に伴い、コンタクトサイズも微
細化されてきているため、従来のスパッタ堆積法では、
金属膜を段差被覆性（ステップカバレッジ）が良好にな
るように被覆することは困難になってきた。そのために
、段差被覆性が良い成膜技術や金属埋め込み技術の開発
が課題になってきている。In recent years, with the increasing integration of LSIs, the contact size has also become smaller, so conventional sputter deposition methods
It has become difficult to coat metal films with good step coverage. Therefore, the development of film formation technology and metal embedding technology that provide good step coverage has become an issue.
その中の一つに、レーザ照射によりＡＩ膜を流動させる
Ａル−ザフロー技術がある。One of them is the A-user-flow technique, in which an AI film is made to flow by laser irradiation.
第２図はこの技術を用いた従来のアルミニウムの電極配
線の形成工程断面図である。FIG. 2 is a cross-sectional view of a conventional aluminum electrode wiring formation process using this technique.
まず、Ｓｌ基板１上にトランジスタ、キャパシタ等を形
成した後（図示なし）、電極取出口として絶縁膜２の所
定箇所にコンタクトホール３を開孔する。First, after transistors, capacitors, etc. are formed on the Sl substrate 1 (not shown), a contact hole 3 is opened at a predetermined location in the insulating film 2 as an electrode outlet.
次に、スパッタ法で、／Ｍ！−１，５％Ｓ １ｌｌＱ４
を１．０μｍの厚さに、続いて、アモルファスＳ１膜５
を５００人の厚さに堆積させる。Next, by sputtering, /M! -1,5%S 1llQ4
to a thickness of 1.0 μm, and then an amorphous S1 film 5
Deposit to a thickness of 500 people.
そして、この半導体ウェハにＸｅＣ１のエキシマレーザ
ビーム６を照射する（第２図（ａ）参照〕。Then, this semiconductor wafer is irradiated with an excimer laser beam 6 of XeC1 (see FIG. 2(a)).
この場合の照射条件としては、半導体ウェハをスキャン
させなからレーザエネルギー密度２．４〜３．３Ｊ／−
で行う、このレーザ照射により局部的にＡＪ−１，５％
３１１１４が加熱され、それが段差の低いコンタクトホ
ール３に流れ込んで、Ａｌ−１，５％ｓｉ膜４′は平坦
な形状となる（第２図（ｂ）参照）。In this case, the irradiation conditions are such that the semiconductor wafer is not scanned and the laser energy density is 2.4 to 3.3 J/-.
This laser irradiation locally causes AJ-1.5%
31114 is heated and flows into the contact hole 3 with a low step, so that the Al-1,5% Si film 4' becomes flat (see FIG. 2(b)).
次いで、Ａｌフォトリソ及びエツチング工程によりＡｊ
−１，５冗Ｓｌ膜４′をパターニングし、Ａｊパターン
ｌ！４”を得た後、反射防止膜のアモルファスＳ ｉ膜
５ ’を除去する。その後、ＡＩシンタを行い、最後に
、バンシベーシロン膜７を堆積させてデバイスを完成さ
せる〔第２図（ｃ）参照〕。Then, Aj is formed by Al photolithography and etching process.
- Pattern the 1,5-layer Sl film 4' to form an Aj pattern l! 4", the amorphous Si film 5' of the anti-reflection film is removed. Then, AI sintering is performed, and finally, the Vansibasilon film 7 is deposited to complete the device [see FIG. 2(c)] ].
（発明が解決しようとする１Ｉａ）
しかしながら、以上述べた方法では、反射防止膜として
のアモルファスＳｔのレーザ光に対する吸収効果が小さ
いため、Ａｊ！、１４９への照射効率も低くなり、Ａｊ
ｌｉを流動させるのに必要なレーザエネルギー密度が高
くなってしまう、このように、照射するレーザのエネル
ギー密度が高いと、ビーム重なり領域でのＡｊｌｉのダ
メージが大きくなり、亀裂が入ったり、溶融・蒸発して
穴があいたりする致命的な欠陥を生じる。更に、アモル
ファスＳｌがＡｊ＋と反応し、以後の工程で完全に除去
できなくなり、Ａｌ配線のマイグレーション寿命を低下
させるという問題もあった。(1Ia to be Solved by the Invention) However, in the method described above, since the absorption effect of amorphous St as an antireflection film for laser light is small, Aj! , 149 is also lowered, and Aj
The laser energy density required to flow the li becomes high.If the energy density of the irradiated laser is high, the damage to the li in the beam overlap region will increase, causing cracks, melting, and Evaporation causes holes and other fatal defects. Furthermore, there is also the problem that the amorphous Sl reacts with Aj+ and cannot be completely removed in subsequent steps, reducing the migration life of the Al wiring.
本発明は、以上述べた反射防止膜のレーザ光に対する吸
収効果が小さいという問題点と、照射後に反射防止膜が
除去できなくなるという問題点を除去するために、レー
ザ光に対する吸収効果が大きく、かつ、除去工程が不要
な反射防止膜を用いたアルミニウム電極配線の形成方法
を提供することを目的とする。In order to solve the above-mentioned problems that the anti-reflection film has a small absorption effect on laser light and the problem that the anti-reflection film cannot be removed after irradiation, the present invention has been developed to have a large absorption effect on laser light and An object of the present invention is to provide a method for forming an aluminum electrode wiring using an antireflection film that does not require a removal process.
（Ｌｌ！題を解決するための手段）
本発明は、上記問題点を解決するために、アルミニウム
電極配線の形成方法において、真空チャンバ内で基板を
加熱しながら、該基板上の反射防止膜で覆われたアルミ
ニウム膜に紫外光レーザを照射するようにしたものであ
る。(Means for Solving Problem Ll!) In order to solve the above-mentioned problems, the present invention provides a method for forming aluminum electrode wiring, in which an anti-reflection film on the substrate is heated while the substrate is heated in a vacuum chamber. The covered aluminum film is irradiated with an ultraviolet laser.
（作用）
本発明によれば、基板上に形成されるＡＪＭを反射防止
膜として亜鉛（Ｚｎ）膜で覆い、チャンバ内にセットす
る。゛そこで、レーザフローｖ装置として、従来のもの
より短波長のＡｒＦエキシマレーザ光源（波長λ： １
９３０人）を用い、チャンバを１０−’Ｔｏｒｒ以下に
真空排気しておき、基板の加熱を３００〜３５０℃に保
持しながらアルミニウム電極配線の形成を行う。(Function) According to the present invention, the AJM formed on the substrate is covered with a zinc (Zn) film as an antireflection film and set in a chamber.゛Therefore, as a laser flow v device, we used an ArF excimer laser light source with a shorter wavelength than the conventional one (wavelength λ: 1
930 people), the chamber was evacuated to 10-' Torr or less, and aluminum electrode wiring was formed while heating the substrate at 300 to 350°C.
（実施例）
以下、本発明の実施例について図面を参照しながら詳細
に説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の実施例を示すアルミニウム電極配線の
形成工程断面図である。FIG. 1 is a cross-sectional view of an aluminum electrode wiring forming process showing an embodiment of the present invention.
まず、Ｓｌ基板１上にトランジスタ、キャパシタなどを
形成した後（図示なし） 、ｔｔｆｌ取出口として絶縁
膜２の所定箇所にコンタクトホール３を開孔する。First, after transistors, capacitors, etc. are formed on the Sl substrate 1 (not shown), a contact hole 3 is opened at a predetermined location in the insulating film 2 as a ttfl extraction port.
次に、スパッタ法で、７１７−１．５％ｓｉ膜４を１．
０μｍの厚さに堆積し、続いて、スパッタ法で反射防止
膜としてＺｎ膜１１を７００人の厚さに堆積する。Next, a 717-1.5% Si film 4 was deposited using a sputtering method.
The Zn film 11 is deposited to a thickness of 0 μm, and then a Zn film 11 is deposited to a thickness of 700 μm as an antireflection film by sputtering.
そして、基板を５ Ｘ １０−”Ｔｏｒｒの真空チｔン
バに入れ、それを３００℃に加熱した状態で、ＡｒＦエ
キシマレーザビーム１２を２Ｊ／ｃｄのエネルギー密度
で照射する〔第１図（ａ）参照〕。Then, the substrate was placed in a vacuum chamber of 5 x 10-'' Torr, heated to 300°C, and irradiated with an ArF excimer laser beam 12 at an energy density of 2 J/cd [Figure 1 (a)] reference〕.
ここで、ｚｎのレーザ光に対する反射率は、波長２５７
３人の光に対して２０％と十分低い、一方、従来のアモ
ルファスＳｔの反射率は、波長２０６６人の光に対して
６８％と高い。Here, the reflectance of zn for laser light is at wavelength 257
The reflectance of conventional amorphous St is sufficiently low at 20% for the light of 3 people, while the reflectance of conventional amorphous St is as high as 68% for the light of 2066 people at a wavelength.
従って、Ｚｎ１ｌｌの場合、波長１９３０人のＡｒＦエ
キシマレーザビーム１２のＡｌ−１，５％Ｓ１膜４への
照射効率がアモルファスＳ １ｌｉ５に比ベテハるかに
高くなる。Therefore, in the case of Zn1ll, the irradiation efficiency of the ArF excimer laser beam 12 with a wavelength of 1930 on the Al-1,5% S1 film 4 is much higher than that of amorphous S1li5.
よって、従来のアモルファスＳｌより小さいエネルギー
密度でもってｊｌ膜４がフローし、平坦化されたＡＪ−
１，５％Ｓｔ膜４′を得ることができる〔第１図（ｂ）
参照〕。Therefore, the JL film 4 flows with a lower energy density than the conventional amorphous Sl, and the flattened AJ-
A 1.5% St film 4' can be obtained [Fig. 1(b)]
reference〕.
また、°この場合、基板１の加熱を行っているので、レ
ーザビーム１２ニよ！、１−１．５Ｍ５ｌａ４のフロー
への低エネルギー化を図ることができる。Also, in this case, since the substrate 1 is being heated, the laser beam 12! , 1-1.5M5la4 can be reduced in energy.
更に、Ｚｎは融点が４１９℃、沸点が９０７℃であり、
ＡＩより低いのでレーザ照射後にはＺｎ膜１１は蒸発し
て排気され、除去のための工数を要しないという利点が
ある。Furthermore, Zn has a melting point of 419°C and a boiling point of 907°C,
Since it is lower than AI, the Zn film 11 is evaporated and exhausted after laser irradiation, which has the advantage that no man-hours are required for removal.
その後、グイ （染料）入りレジストを用いて、従来と
同様にＡＩパターン８４’を形成し、その上にパンシベ
ーシッンＩ！１３を堆積させる〔第１図（ｃ）参照）。Thereafter, an AI pattern 84' is formed using a dye-containing resist in the same manner as before, and Pancibasin I! is applied thereon. 13 (see FIG. 1(c)).
第３図は本発明の他の実施例を示すアルミニウム電極配
線の形成工程断面図である。FIG. 3 is a sectional view showing a process for forming aluminum electrode wiring according to another embodiment of the present invention.
まず、Ｓｉｉ仮１仮定上ランジスタ、キャパシタなどを
形成した後（図示なし）、電極取出口として絶縁膜２の
所定箇所にコンタクトホール３を開孔する。First, after forming transistors, capacitors, etc. (not shown) on a Sii hypothetical basis, a contact hole 3 is opened at a predetermined location in the insulating film 2 as an electrode outlet.
次いで、スパッタ法で、オーミンクメタルとしてＴｉ
ｆｌ！１１４を５００人形成し、その上に反応性スパッ
タ法で、バリアメタルとしてＴＩ ＮＢ！１５を１００
（１人形成し、更にその上にＡＪ−１，５％３１膜１６
を１．０μｍの厚さに堆積し、続いて、スパッタ法で反
射防止膜としてＺｎ１ｉ１７を７００人の厚さに堆積す
る。Next, using a sputtering method, Ti was added as an ohmink metal.
Fl! 114 was formed, and TI NB! was applied as a barrier metal on top of it by reactive sputtering. 15 to 100
(One person formed, and then AJ-1,5%31 film 16
was deposited to a thickness of 1.0 μm, and then Zn1i17 was deposited to a thickness of 700 μm as an antireflection film by sputtering.
そして、基板を５ Ｘ １０− ”Ｔｏｒｒの真空チャ
ンバに入れ、基板を３００℃に加熱した状態で、ＡｒＦ
エキシマレーザビーム１２を２Ｊ／ｃｄのエネルギー密
度で照射する〔第３図（ａ）参照】。Then, the substrate was placed in a 5 x 10-” Torr vacuum chamber, and while the substrate was heated to 300°C, ArF
The excimer laser beam 12 is irradiated with an energy density of 2 J/cd [see FIG. 3(a)].
そこで、Ａｌ膜１６がフローし、前記実施例と同様に平
坦化されたＡｊ！−１，５％５ｉｌｌ１６’を得ること
ができる〔第３図（ｂ）参照〕。Therefore, the Al film 16 flows, and Aj! is flattened as in the previous embodiment. -1.5% 5ill16' can be obtained [see Figure 3(b)].
その後、ダイ（染料）入りレジストを用いて、従来と同
様にＡＩパターン膜１６′を形成し、その上にパンシベ
ーシコン膜１８を堆積させる〔第３図（ｃ）参照〕。Thereafter, using a dye-containing resist, an AI pattern film 16' is formed as in the conventional method, and a pansibasicon film 18 is deposited thereon (see FIG. 3(c)).
このように、Ａｊｔｌｉの下にバリアメタルを敷いた配
線構造にすると、ＡＪ膜のフロー温度が高い場合でも、
そのバリアメタルの存在により基板のダメージをより低
減できるという利点がある。In this way, by creating a wiring structure in which a barrier metal is placed under Ajtli, even when the flow temperature of the AJ film is high,
The presence of the barrier metal has the advantage that damage to the substrate can be further reduced.
なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
（発明の効果）
以上、詳細に説明したように、本発明によれば、反射防
止膜として、レーザ光の吸収効果の大きいＺｎ１ｉを用
い、かつ基板の加熱も併用したので、低エネルギー密度
のレーザ照射でＡＪ膜がフローできる。従って、ビーム
重なり領域に対しても、過度のエネルギーによるＡｊｌ
膜のダメージの発生が回避できるだけでな（、レーザ出
力がそれ程大きくないレーザ光源でもビームサイズを大
きくできるので、ビームスキャン時間が短縮され、スル
ープントが向上するという利点がある。更に、反射防止
膜はレーザ照射後、特別な除去処理を施さなくても蒸発
してなくなるので、工程が簡略化され、Ａｌ電極配線の
信頼性の向上を図ることができる。(Effects of the Invention) As described in detail above, according to the present invention, Zn1i, which has a large laser light absorption effect, is used as the antireflection film, and the substrate is also heated, so that the laser beam with low energy density can be used. Irradiation allows the AJ film to flow. Therefore, even for the beam overlap region, Ajl due to excessive energy
Not only can damage to the film be avoided (but also the beam size can be increased even with a laser light source whose laser output is not so high, the beam scanning time is shortened and throughput is improved. After laser irradiation, it evaporates and disappears without any special removal treatment, which simplifies the process and improves the reliability of the Al electrode wiring.
また、Ａｊｌｌｌの下にバリアメタルを敷いた配線構造
にすると、ＡＪ膜のフロー温度が高い場合でも、そのバ
リアメタルの存在により基板のダメージをより低減させ
ることができる。Furthermore, if a wiring structure is adopted in which a barrier metal is laid under the AJll, even if the flow temperature of the AJ film is high, damage to the substrate can be further reduced due to the presence of the barrier metal.
第１図は本発明の実施例を示すアルミニウム電極配線の
形成工程断面図、第２図は従来のアルミニウム電極配線
の形成工程断面図、第３図は本発明の他の実施例を示す
アルミニウム電極配線の形成工程断面図である。
１・・・８１基板、２・・・絶縁膜、３・・・コンタク
トホール、４．１６・・・Ａ ｊ −１，５％Ｓ ｉ膜
、１１．１７・・・亜鉛（Ｚ ｎ）膜、１２・・・Ａｒ
Ｆエキシマレーザビーム、１３、１８・・・バッジベー
ジリン膜、１４・・・Ｔｉ１５１．１５・・・Ｔｉ Ｎ
膜。
特許出願人 沖電気工業株式会社
代理人 弁理士 清 水 守（外１名）第
図
従来のＡｉ２電躬電盃１項の形成工ｆ１幻１ｉｆｆｉ閏
第
２図FIG. 1 is a sectional view of the process of forming an aluminum electrode wiring according to an embodiment of the present invention, FIG. 2 is a sectional view of the process of forming a conventional aluminum electrode wiring, and FIG. 3 is a sectional view of the process of forming an aluminum electrode wiring according to another embodiment of the present invention. FIG. 3 is a cross-sectional view of the wiring formation process. 1... 81 substrate, 2... insulating film, 3... contact hole, 4.16... A j -1,5% Si film, 11.17... zinc (Zn) film , 12...Ar
F excimer laser beam, 13, 18...Budgebage phosphorus film, 14...Ti151.15...TiN
film. Patent applicant Oki Electric Industry Co., Ltd. Agent Patent attorney Mamoru Shimizu (1 other person) Fig. 1 Forming process of conventional Ai2 electric cup 1 f1 phantom 1 iffi leap Fig. 2
Claims (3)
の反射防止膜で覆われたアルミニウム膜に紫外光レーザ
を照射し、基板平面部分を平坦化することを特徴とする
アルミニウム電極配線の形成方法。(1) While heating the substrate in a vacuum chamber, an ultraviolet laser is irradiated onto an aluminum film covered with an anti-reflection film on the substrate to flatten the flat surface of the substrate. Formation method.
請求項１記載のアルミニウム電極配線の形成方法。(2) The method for forming an aluminum electrode wiring according to claim 1, wherein the antireflection film is a zinc film.
成してなる請求項１記載のアルミニウム電極配線の形成
方法。(3) The method for forming an aluminum electrode wiring according to claim 1, wherein a barrier metal layer is formed below the aluminum film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31208788A JPH02158133A (en) | 1988-12-12 | 1988-12-12 | Formation of aluminum electrode wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31208788A JPH02158133A (en) | 1988-12-12 | 1988-12-12 | Formation of aluminum electrode wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02158133A true JPH02158133A (en) | 1990-06-18 |
Family
ID=18025080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31208788A Pending JPH02158133A (en) | 1988-12-12 | 1988-12-12 | Formation of aluminum electrode wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02158133A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04245457A (en) * | 1990-09-05 | 1992-09-02 | Micron Technol Inc | Method of improving step coverage of metallic coated layer on integrated circuit by usage of high melting-point metal as antireflection film at time of laser flattening |
| JP2006201745A (en) * | 2005-01-20 | 2006-08-03 | Samsung Sdi Co Ltd | Plasma display apparatus and method of manufacturing the same |
| US7163854B2 (en) | 1996-11-07 | 2007-01-16 | Semiconductor Energy Laboratory Co., Ltd. | Fabrication method of a semiconductor device |
-
1988
- 1988-12-12 JP JP31208788A patent/JPH02158133A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04245457A (en) * | 1990-09-05 | 1992-09-02 | Micron Technol Inc | Method of improving step coverage of metallic coated layer on integrated circuit by usage of high melting-point metal as antireflection film at time of laser flattening |
| US7163854B2 (en) | 1996-11-07 | 2007-01-16 | Semiconductor Energy Laboratory Co., Ltd. | Fabrication method of a semiconductor device |
| US7470580B2 (en) | 1996-11-07 | 2008-12-30 | Semiconductor Energy Laboratory Co., Ltd. | Fabrication method of a semiconductor device |
| JP2006201745A (en) * | 2005-01-20 | 2006-08-03 | Samsung Sdi Co Ltd | Plasma display apparatus and method of manufacturing the same |
| US7492080B2 (en) | 2005-01-20 | 2009-02-17 | Samsung Sdi Co., Ltd. | Plasma display apparatus and method of manufacturing same |
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