JPH02157959A - Information transfer system for information processor - Google Patents

Abstract

PURPOSE:To shorten waiting time to a data bus using request and to improve data transfer ability by providing a shared data bus in a loop shape, electrically executing the interruption and connection of the data bus in correspondence to the data bus using request when the request is received, dividing the data bus and simultaneously executing data transfer to plural places. CONSTITUTION:When the data bus using requests are outputted from central processing units 1 and 2, main storage devices 3 and 4 and input / output devices 5 and 6, a gate control part 8 recognizes a data bus using condition from a gate operating state at a present time. Then, in correspondence to the data bus using condition, respective gates 9-14 are opened / closed and the connection and interruption of the data bus are executed. After that, plural data buses 7 are constituted and the data transfer is simultaneously executed to the plural places. Thus, the waiting time is shortened to the data bus using request and the data transfer ability can be improved.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an information transfer method for an information processing device.

In particular, it relates to data bus transfer control.

〔overview〕

The present invention provides an information transfer system for an information processing device in which at least one central processing unit, main storage device, and input/output device are connected by a shared data bus that transfers information between each other, in which the shared data bus is looped. When a data bus use request is received, the data bus is electrically connected/disconnected and divided, making it possible to perform multiple data transfers at the same time. It is designed to reduce time and improve data transfer ability.

[Conventional technology]

Conventionally, in the data transfer method of this type of information processing device, the shared data bus that transfers data between the central processing unit, main storage device, and input/output device is only used to transfer data in response to one data bus usage request. If there are multiple data bus usage requests at the same time, data transfer will be performed only in response to one of them, and data transfer in response to other data bus usage requests will not be performed at the same time. It was decided that this would not be done.

[Problem that the invention seeks to solve]

In the conventional data transfer method described above, even if there are multiple data bus use requests at the same time, data transfer is performed only in response to one of the data bus use requests, and other data bus use requests are not permitted. Therefore, the data bus use request source had to wait until the request was granted.

SUMMARY OF THE INVENTION The present invention aims to eliminate these drawbacks, and aims to provide a transfer method that can reduce waiting time for requests to use a data bus and improve data transfer performance.

[Means for solving problems]

The present invention provides an information transfer method for an information processing device in which at least one central processing unit, main storage device, and input/output device are connected by a data bus, in which the data bus is connected in a loop, and the data bus is connected to the data bus. A plurality of gates are provided to electrically open and close all paths existing between the central processing unit, the main storage device, and the input/output device, and the plurality of gates are opened and closed according to information obtained from the central processing unit. The present invention is characterized in that it includes a gate control section for controlling the data bus, and the gate control section includes control means for simultaneously dividing the data bus into a plurality of data buses for use.

[Effect]

When a data bus use request is output from the central processing unit, main memory device, and input/output device, the gate control unit O recognizes the data bus usage status from the current gate operating state and opens and closes each gate accordingly. It connects and disconnects buses, configures multiple data buses, and performs multiple data transfers simultaneously.

This makes it possible to reduce waiting time for data bus use requests and improve data transfer capability.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

The figure is a block diagram showing the configuration of an embodiment of the present invention.

Embodiments of the present invention include at least one central processing unit 1
．． 2. The main storage device 3.4 and the input/output device 5.6 are connected by a data bus 7, and the data bus 7 is provided in a loop, and the central processing device 1.2, the main storage device 3.4, and the input/output device A plurality of gates 9.10.5.6 electrically open and close all the data buses 7 present between each of the gates 9.10.
11.12.13.14 and these multiple gates 9.10
, and a gate control section 8 that controls the gates 1, 12, 13, and 14.

The gate control unit 8 includes means for storing the physical positional relationship of the central processing unit 1.2, the main storage device 3.4, and the input/output device 5.6, and means for storing the current operating state of the gate 7. , accepts and stores data bus usage requests and data transfer partners from the central processing unit 12 and input/output devices 5.6;
It is determined whether the data bus use request source can use the data bus 7 based on the physical positional relationship with the data bus use request source, the physical positional relationship with the data transfer partner, and the current gate operating state, and the data bus use request source is sent to the data bus 7. When the data bus use request source can use the data bus 7, the gate 9 of the data transfer route between the data bus use request source and the data transfer destination
．． 12.13.14 connection control means.

That is, the central processing unit 1.2, the main storage device 3.4, and the input/output device 5.6 are connected by a loop-shaped shared data bus 7 in the arrangement shown in the figure, and this physical positional relationship is determined by the gate control unit 8. Gates 9.10.11.12 are connected between each device on this loop-shaped shared data bus 7.
．． 13.14 are provided.

Each gate) 9.10.11.12.13.14 electrically connects or disconnects the loop data bus 7, and each gate 9.
．． The states of 10, 11, 12, 13, and 14 are determined by the gate controller 8 and stored.

The operation of the embodiment of the present invention configured as described above will be explained. FIG. 2 is a flowchart showing the flow of operation of the embodiment of the present invention. When there is no request to use the loop-shaped shared data bus 7, the gate control unit 8 controls each gate 9.10.11.
12.13.14 are all electrically disconnected. In this state, when the central processing unit 1 transfers data to the main storage device 3, it first notifies the gate control unit 8 using the data bus use request permission control signal 15. The gate control unit 8 instructs the gate 9 to connect and notifies the central processing unit 1 of permission to use the data bus.

When the input/output device 6 further transfers data to the main storage device 4 in this state, it notifies the gate control section 8 by the data bus use request permission control signal 18. The gate control unit 8 instructs the gate 11 to connect and notifies the input/output device 6 of permission to use the data bus. This enables two types of data transfer between the central processing unit 1 and the main storage device 3 and between the input/output device 6 and the main storage device 4.

In this embodiment, data can also be transferred between the central processing unit 2 and the input/output device 50 at the same time by further performing similar control and connecting the gate 13.

Further, in response to data bus use requests from each device, the gate control unit 8 changes the connection and disconnection states of each gate 9, 10, 11, 12, 13, and 14, and controls data transfer between each device.

〔Effect of the invention〕

As explained above, according to the present invention, a common data bus for transferring data between the central processing unit, the main storage device, and the input/output device is configured in a loop shape, and the data bus is electrically connected. Gates to be disconnected and data bus usage requests accepted are used to electrically connect and disconnect the looped data bus at several points using gates as necessary to enable multiple data transfers. According to
This has the effect of reducing waiting time for requests to use the data bus and improving data transfer capability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a flowchart showing the operation flow of the embodiment of the present invention. 1.2...Central processing unit, 3.4...Main storage device,
5.6...I/O device, 7...Loop-shaped shared data bus,...Gate control unit, 9.10.11.12.1
3.14...Gate, 15.16.17.18...
Data bus use request permission control signal.

Claims (1)

[Claims] 1. An information transfer method for an information processing device in which at least one central processing unit, main storage device, and input/output device are connected by a data bus, the data bus being connected in a loop, A plurality of gates are provided to electrically open and close all the paths existing between the central processing unit, the main storage device, and the input/output device on this data bus, and the plurality of gates are obtained from the central processing unit. An information transfer system for an information processing device, comprising: a gate control unit that controls opening and closing according to information; and the gate control unit includes control means for simultaneously dividing the data bus into a plurality of data buses for use. .