JPH0215790A - Muse signal digital recording and reproducing device - Google Patents

Abstract

PURPOSE:To shorten the data length of MUSE signals so that the MUSE signals can be recorded efficiently by using a smaller area by partially deleting horizontal synchronizing signals at every horizontal line at the time of recording and shifting the data by the deleted quantities. CONSTITUTION:MUSE signals fed to an input terminal 11 are supplied to a data length reduction circuit 12. The circuit 12 reduces the data length of the MUSE signals at every horizontal line by partially deleting horizontal synchronizing signals HD contained in the MUSE signals at every horizontal line and shifting the data by the deleted quantities. The MUSE signals, the data length of which is reduced, are supplied to a rotary head 19 and recorded on a magnetic tape 20 after the signals are subjected to various processes. On the other hand, the MUSE signals reproduced from the magnetic tape 20 by means of the rotary head 19 are supplied to a data length restoration circuit 26 after the signals are subjected to various processes. Then the MUSE signals are restored to the original data length by performing the opposite data shifting process on the MUSE signals and adding previously prepared deleted data of the horizontal synchronizing signals to the shifted parts.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a MUSE signal digital recording and reproducing apparatus that records and reproduces MUSE television signals in the form of digital signals.

(Prior Art) Conventionally, in a video tape recorder (hereinafter referred to as VTR), a television signal of the MUSE system (hereinafter referred to as MUSE) is used.
When recording a signal (hereinafter referred to as a USE signal) on a magnetic tape, it was converted to an analog signal before being recorded.

However, in recent years, digital recording technology for VTR signals has progressed rapidly, and even in home VTRs, MU
Digital recording of SE signals has become possible.

By the way, the MUSE signal has many redundant parts, and recording it digitally as it is would be wasteful.

Therefore, a VTR is desired that can effectively record MUSE signals using a small area.

(Problem 8 to be solved by the invention) As mentioned above, digital recording of signals in home VTRs has progressed, and with this, the MUSE signal, which has many redundant parts, can be recorded using a small area. The problem was how to record efficiently.

Therefore, this invention provides a home VTR with a MUSE
MU that can efficiently record signals in a small area
An object of the present invention is to provide an SE signal digital recording and reproducing device.

[Structure of the Invention (Means for Solving the Problems)] In order to achieve the above object, the present invention focuses on the fact that the horizontal synchronization signal of the MUSE signal has a fixed pattern, and when recording, this horizontal synchronization signal is By partially deleting each horizontal line and shifting the data by only the deleted bone, the data length of the MUSE signal is shortened and recorded, and during playback, data shift processing is performed in the opposite manner to that during recording, By adding the horizontal synchronization signal deletion data to this part,
The data length of the MUSE signal is restored.

(Operation) According to the above configuration, the horizontal synchronization signal is deleted by
Since the data length of the MUSE signal is shortened, the redundancy of the MUSE signal is reduced, and this MUSE signal can be efficiently recorded using a small area.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, first, the configuration at the time of recording will be explained.

In the figure, 11 is an input terminal to which the MUSE signal is supplied. - The MUSE signal supplied to this input terminal 11 is supplied to a data length reduction circuit 12. This data length reduction circuit 12 deletes a part of the horizontal synchronizing signal HD included in the MUSE signal for each horizontal line, and shifts the data by the deleted amount, thereby reducing the MUS of each horizontal line.
Shorten the data length of the E signal.

The MUSE signal whose data length has been shortened is the time axis conversion circuit 1.
3, and is time-compressed to enable addition of a synchronization signal, etc., which will be described later. This time-compressed MUSE signal is divided into blocks of predetermined data length by a VTR synchronization signal addition circuit 14, and a synchronization signal is added to each block. The MUSE signal to which the synchronization signal has been added has a parity check code added thereto by an error correction parity generation circuit 15, and then interleaved by an interleave circuit 16. This interleaved MU
After the SE signal is modulated into a signal suitable for recording by the modulation circuit 17, it is supplied to the rotary disk 19 via the switch 18 and recorded on the magnetic tape 20.

Next, the configuration of the reproduction system will be explained.

M reproduced from the magnetic tape 20 by the rotating head 19
The USE signal is supplied to the demodulation circuit 21 via the switch 18 and demodulated. This demodulated MUSE signal is
After being deinterleaved in the deinterleaving circuit 22, the signal is subjected to error correction processing in the error correction circuit 23.

The MUSE signal that has undergone this error correction process has a synchronization signal for block synchronization removed by a VTR synchronization signal deletion circuit 24, and then time-expanded by a time axis conversion circuit 25. As a result, the time length is returned to the time length before time compression by the time conversion circuit 13.

The time-expanded MUSE signal is sent to the data length restoration circuit 26
supplied to This data length restoration circuit 26
MUS
Restore the data length of the E signal to its original length. The restored MUSE signal having this data length is supplied to the output terminal 27.

The overall configuration of one embodiment has been described above. Next, the data length reduction circuit 12 and the data length restoration circuit 26, which are the characteristics of the present invention, will be explained in more detail.

FIG. 2 is a circuit diagram showing an example of a specific configuration of the data length reduction circuit 12.

In this FIG. 2, the MUS supplied to the input terminal 11
The E signal is stored in the field memory 31. for each field.
32 and read in the next field.

This read MUSE signal is transmitted to the time base conversion circuit 13.
supplied to

Write address designation data specifying the write address of the memory 31, 32 is output from the active low type write counter 33, and read address designation data specifying the read address is output from the active low type read counter 34. These addressing data are alternately supplied to the memory 31 via the selector 35 for each field. Similarly, the above two addressing data are alternately supplied to the memory 32 for each field via the selector 36. In this case, the memory 31
If write addressing data is supplied to
Memory 32 is provided with read addressing data, and conversely, if memory 31 is provided with read addressing data, memory 32 is provided with write addressing data. As a result, writing and reading are performed separately in the memories 31 and 32.

The counters 3B and 34 are reset for each field by a reset signal R output from the timing generation circuit 37. Furthermore, the selectors 35 and 36 alternately select two pieces of addressing data for each field in response to the control signal C output from the timing generation circuit 37.

Note that the timing generation circuit 37 generates various timing signals such as the above-mentioned reset signal R in synchronization with the MUSE signal supplied to the input terminal 11.

To shorten the data length of the MUSE signal, the enable signal EN supplied from the timing generation circuit 37 to the write counter 33 is set to a high level to stop the counting operation of this counter 33, and the timing generation circuit 37 also outputs data from the memory 31 or the memory. This is done by stopping the generation of the write pulse WP supplied to the memory 32 and stopping data writing to the memory 31 or the memory 32.

As a result, updating of the write address of the memory 31 or the memory 32 is stopped, and data writing to the memory 31 or the memory 32 is also stopped, so that data is deleted and data is shifted.

Here, the horizontal synchronization signal) (for the deleted part of D, the third
This will be explained with reference to the figures and FIG.

FIG. 4 is a diagram showing the data structure of the MUSE signal per horizontal line.

As shown in the figure, the MUSE signal has a horizontal synchronization signal HD at the beginning.
exists, followed by a color signal C and a luminance signal Y in sequence. Also, the number of samples per horizontal line is 480, of which the horizontal synchronizing signal H
The number of samples of D is set to 11.

FIG. 3 shows an analog waveform of the horizontal synchronizing signal HD.

In the figure, HDI is, for example, a horizontal synchronizing signal for odd lines, and HD2 is a horizontal synchronizing signal for even lines. In this way, in the MUSE system, there are two types of fixed pattern signals as horizontal synchronizing signals HD, and these are sent alternately for each horizontal line.

For such a horizontal synchronization signal HD, the data length reduction circuit 12 deletes, for example, 8 bytes of data from the beginning, shifts the data by this amount, and outputs only the remaining 3 bytes of data. It has become.

Note that data is read from the memory 31 or the memory 32 at a faster speed than the writing speed. That is, the clock rate of the read counter 34 is set to a higher value than the clock rate of the write counter 33. This is to secure the time necessary for data processing, since the data read from memory 31 or memory 32 is subjected to various data processing as explained in FIG. 1 above. In other words, at the time of writing data to the memory 31 or the memory 32, the memory 32
Alternatively, it is for reading data from the memory 31 and executing the various data processing described above.

In order to perform data read processing faster than data write processing in this way, when the data read processing is completed, the enable signal supplied from the timing generation circuit 37 to the read counter 34 is set to high level, and the timing generation circuit The generation of the read pulse RP supplied from the circuit 37 to the memory 31 or the memory 32 is stopped, and the data read operation is stopped until the data of the next field is read.

FIG. 5 is a circuit diagram showing an example of a specific configuration of the synchronizing signal adding circuit 26. As shown in FIG.

In FIG. 5, the MUSE signal output from the time axis conversion circuit 25 is alternately written into the field memories 41 and 42 for each field, and then read out in the next field. The read MUSE signal is sent to the switch 43
is supplied to the output terminal 27 via.

Write address designation data specifying a write address of the memory 41, 42 is output from an active low type write counter 44, and read address designation data specifying a read address is output from an active low type read counter 45. These addressing data are alternately supplied to the memory 41 for each field via the selector 46. Similarly, the above two addressing data are alternately supplied to the memory 42 for each field via the selector 47. In this case, the memory 41
If write addressing data is supplied to
If memory 42 is supplied with read addressing data and memory 41 is supplied with read addressing data, memory 42 is supplied with write addressing data.

As a result, the -memories 41 and 42 are written and read separately.

The counters 44 and 45 are reset for each field by a reset signal R output from the timing generation circuit 48. Further, the selectors 46 and 47 alternately select two pieces of address designation data for each field in response to the control signal C1 outputted from the timing generation circuit 48. The timing generation circuit 48 generates the reset signal R in synchronization with the MUSE signal output from the time axis conversion circuit 25.
Generates various timing signals such as

Of the data length restoration processing of the MUSE signal, the data shift processing is performed by setting the enable signal EN supplied from the timing generation circuit 48 to the read counter 45 to a high level to stop the counting operation of the read counter 45, and at the same time This is done by stopping the generation of the read pulse RP supplied from the generation circuit 48 to the memory 41 or the memory 42 and stopping reading data from the memories 41 and 42. As a result, updating of the read address of the memory 41 or the memory 42 is stopped, and
Since data reading from memory 41 or memory 42 is stopped, data is shifted.

On the other hand, data addition processing is performed by switching the switch 43 to the ROM 49 side and guiding the deleted data of the horizontal synchronizing signal HD stored in the ROM 49 to the output terminal 27.

The ROM 49 stores data of the portions of the two types of horizontal synchronizing signals HDL and HD2 described above in FIG. 4 that were deleted during recording. In this case, the deletion data of the horizontal synchronization signal HDI and the deletion data of the horizontal synchronization signal HD2 are stored at different addresses. Addressing data for reading out the stored data is provided by the timing generation circuit 48 and counter 50. In this case, the addressing data output from the timing generation circuit 48 specifies the address in units of 8 bytes, and the addressing data output from the counter 50 specifies the read address in units of bytes. . That is, the timing generation circuit 48 detects the reproduction output (3 bytes worth of data) of the horizontal synchronization signal HD from the MUSE signal output from the time axis generation circuit 25,
Determine whether the horizontal line is an odd or even line. Then, according to the result of this determination, address designation data that designates the data storage address in units of 8 bytes is output. The counter 50 performs a counting operation in synchronization with the detection output of the horizontal synchronization signal HD of the timing generation circuit 48, and outputs address designation data that designates a storage address in units of bytes. Addressing is then performed using the former as addressing data for the upper bits and the latter for the lower bits.

The switch 43 selects the read output of the memory 41 or the memory 42 during the period when the read counter 45 is performing counting operation, and selects the read output from the memory 41 or the memory 42 during the period when the read counter 45 is stopping the counting operation due to the enable signal EN.
Select read data of OM49. This selection operation is controlled by a control signal C2 output from the timing generation circuit 48.

Note that the clock rate of the write counter 44 is set to the same rate as the clock rate of the write counter 34 in FIG. On the other hand, the clock rate of the read counter 45 is set to the same rate as the clock rate of the write counter 33.

As a result, a MUSE signal having the same time length as the MUSE signal supplied to the input terminal 11 is output to the output terminal 28 .

In order to perform the data write process faster than the data read process, when the data write process is completed, the enable signal EN supplied from the timing generation circuit 48 to the write counter 34 is set to high level, and the memory 41 or Write pulse WP to memory 42
The data writing operation is stopped until the reproduction data of the next field arrives.

As detailed above, in this embodiment, the horizontal synchronization signal is a fixed pattern signal, and when recording the MUSE signal, the first 8 bytes of data of the horizontal synchronization signal HD are deleted. There is a system in which data is shifted by that amount, data shift processing is performed in the opposite direction to that during reproduction and recording, and deletion data of the horizontal synchronizing signal HD is added to this shifted portion.

According to such FI4 configuration, the data length of the MUSE signal can be shortened by partially deleting the horizontal synchronization signal HD, so the MUSE signal, which has many redundant parts, can be efficiently recorded in a small area. can do.

Furthermore, according to the 1111S configuration, in a digital recording/playback device using a so-called multi-track recording method in which a track is divided into a plurality of areas and a MUSE signal is divided and recorded in each area, the number of bytes to be deleted from the horizontal synchronization signal HD can be adjusted. MUSE is recorded separately in each area by setting appropriately.
There is an advantage that the number of signal bytes can be made equal.

Note that this invention is not limited to the above embodiments.

For example, in the previous embodiment, the first 8
Although a case has been described in which byte worth of data is deleted, it is of course possible to delete other parts or other number of bytes.

In addition, in the previous embodiment, in order to shorten the data length of the MUSE signal, it is necessary to update the write address and write the write pulse W.
Although a case has been described in which the generation of P is stopped, it is also possible to delete and shift data by stopping only updating of the write address and overwriting data at the same address. This also applies to data length restoration processing.

Further, in the previous embodiment, the MUE signal output from the time axis conversion circuit 25 is used to determine whether the horizontal line is odd or even, and R
Although the case has been described in which the addressing data of the upper bits of the OM 49 is output, it goes without saying that the line determination may be performed using the MUSE signal read from the memory 41 or the memory 42.

It goes without saying that this invention can be modified in many other ways without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, the data length of the MUSE signal, which has many redundant parts, can be shortened.
MUSE signals can be efficiently recorded in a small area.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the overall configuration of the present invention, FIG. 2 is a circuit diagram showing an example of a specific configuration of the data length reduction circuit shown in FIG. 1, and FIG. FIG. 4 is a diagram showing the analog waveform of the horizontal synchronization signal; FIG. 5 is a diagram showing the tl configuration of an example of a specific configuration of the data length restoration circuit in FIG. 1. It is a circuit diagram. 11...Input terminal, 12...Data length reduction circuit, 1
3... Time axis conversion circuit, 14... VTR synchronization signal addition circuit, 15... Parity generation circuit for error correction,
16... Interleave circuit, 17... Modulation circuit,
18.43...Switch, 19...Head, 20.
... Magnetic tape, 21 ... Demodulation circuit, 22 ... Deinterleave circuit, 23 ... Error correction circuit, 24.
...VTR synchronization signal deletion circuit, 25...Time axis conversion circuit, 26...Time axis restoration circuit, 27...Output terminal, 31゜32.41.42...Field memory, 3
3.44...Write counter, 34.45...Read counter, 35, 36, 46.47...Selector,
37゜4: Timing generation circuit, 49: ROM
. 50...Counter.

Claims (1)

[Scope of Claims] Data length reduction means for reducing the data length of the MUSE signal by partially deleting the horizontal synchronization signal of the MUSE signal for each horizontal line and shifting the data by the deleted amount; a recording means for recording the output of the data length reduction means on a recording medium; a reproduction means for reproducing the MUSE signal recorded on the recording medium; and a data shift process of the data length reduction means for the reproduction output of the reproduction means. A MUSE signal digital recording/reproducing device comprising data length restoring means for restoring the data length of a MUSE signal by performing a data shift process opposite to the above and adding deleted data of a horizontal synchronizing signal to the shifted portion.