JPH02156672A - Semiconductor device - Google Patents

Abstract

PURPOSE:To keep on-resistance of a transistor constant irrespective of the size of the capacitance of a MOS transistor by making the plane shape of the gate of the MOS transistor a composite shape rather than a rectangle. CONSTITUTION:On an Si diffusion area 11 forming the bottom electrode of a gate structure, the top electrode 12 of the gate structure is formed. SiO2 exists between the area 11 and the electrode 12, and a parallel-plate capacitor is formed, which constitutes an essential portion of a MOS transistor. The area 11 as a bottom electrode and a gate area 15 oppositely facing the top electrode 12 are formed in a composite shape of length l1 and which w1, and length l2 and width w2. By forming the plane shape of a gate like this, the on-resistance of the transistor can be kept constant irrespective of the size of the capacitance of the MOS transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor integrated circuit (LSI) in which complementary transistors mounted on a semiconductor substrate are interconnected to mainly perform logic functions. The present invention relates to a semiconductor device devised to facilitate design regarding the delay time of passing signals.

2. Description of the Related Art Semiconductor integrated circuits (hereinafter referred to as LSI) generally consist of a huge number of circuit elements such as transistors, resistors, and capacitors, and in order to perform various functions, these circuit elements are interconnected using aluminum wiring. is connected with. Various elemental circuits can be created depending on the wiring method, but the most basic circuit that occupies most of the circuit in terms of quantity is a CMOS inverter dependent coupling circuit, and FIG. 3 shows a two-stage coupling CMOS inverter circuit. In practice, many such circuits or modified circuits are used, but basically they are two stages.

When a signal passes through this circuit, a delay time occurs and the signal is delayed. Estimating this delay time or designing it to a predetermined value is an essential design element for the LSI to function normally. This will be explained using FIGS. 3 and 4.

In FIG. 3, 32 and 33 are power supply terminals, and normally a voltage of +5V is supplied between these two terminals. 34 and 36
is a P-channel MOS type transistor, and 35 and 37 are N-channel MOS type transistors. 30 is an input terminal, and 31 is an output terminal. 38 is the total stray capacitance existing in the signal line 40 and the ground terminal 33, and the transistor 34
．． This is the total capacitance of the drain capacitance of No. 35, the wiring capacitance of the signal line 40, the gate capacitance of the transistors 36 and 37, etc. Similarly, 39 is the total capacitance present in the signal line 31.

A signal is applied to terminal 30 and output to terminal 31. At this time, the signal is delayed. To further explain this, consider inputting a square wave like 41 in FIG. 4 to the input terminal 30. (As is known, the waveform of the signal line 40 is like the waveform 42 in FIG. 4. Also, the waveform of the signal output terminal 31 is like the waveform 43. When compared with the waveform 4 in Figure 4,
The signal is delayed by the time td shown in 4. These delay times t and i are the time TOH of the signal line waveform 42 in FIG.
It is clear that they are directly involved. Here, the voltage 42 on the signal line 40 is falling with a finite slope over time TON (this is because the charge accumulated in the capacitor 38 must pass through the on-resistance RON of the transistor 35 and be discharged). Therefore, the on-time TON is determined by the capacitance value CS of the stray capacitance 38 and the on-resistance R of the transistor 35.
It has a value related to the product R3S"CS of OM. On the other hand, the time T OFF of the voltage rising portion of waveform 42- is the capacitance value CL
This is generated by charging the capacitance 39 of the output terminal with a charge through the on-resistance R3G of the transistor 36, and its value is directly related to the time constant R3g·CL. In this way, the input signal 41 in FIG. 4 becomes the output signal 43 by a delay time roughly related to TON and TOFF.The exact value of this delay time is Although it is complicated due to other factors, if the average time delay is td, it can be conceptually expressed by the following formula: 'ro,, = γasRsscs
(2) TOFF”γ0FFR36CL
(3) Here, α, β, γON
e γopp is a constant.

As mentioned above, the value of the average delay time td is an important factor in determining whether the entire LSI functions normally. Therefore, it is necessary to understand this value as accurately as possible and to design a circuit (mainly related to the size of the transistor) to a certain required value. Further, this delay time may be actively utilized to combine the circuit shown in FIG. 3 in multiple stages and apply it as a delay element. Therefore, let us consider a case where this average delay time is designed to a predetermined value. Now, if we consider the case where we want to design thicker td, various methods can be considered, but for example, let us consider the case where we increase the value of capacitor 38 to increase td. occupies most of the gate capacitance.This gate capacitance is proportional to the area of the gate of the transistor.

FIG. 5 shows the structure of transistors 36 and 37 on a semiconductor substrate. 51.54 are transistors 36.37 respectively
The source electrode of 52.55 is also the gate electrode of 53.
56 is a drain electrode.

Now, if we focus only on the gate area of the transistor 37 in question, the area is determined by its width W and length. In the conventional technology, the shape of the gate of the transistor is rectangular, and in order to increase the size of the capacitance value C5 for the current purpose, W or L of the gate must be increased (to increase the size of the capacitance C5). Usually, measures are taken to increase the area.

Problems to be Solved by the Invention Let us now consider a case where the capacitance value CS is increased to bring the average delay time td to a predetermined value. Therefore, specifically, measures are taken to increase the gate capacitance by mainly increasing the gate area of the transistor. In this case, if the gate width W and gate length are increased by the same ratio (that is, increased by scaling), the on-resistance of this transistor remains unchanged. Of course, it is theoretically possible to change W and L by the same ratio, but from the standpoint of actual LSI mask design, it is usually not possible to change the gate width due to the geometric arrangement with other transistors. . Under these circumstances, measures are taken to increase the gate capacity by increasing only the gate length.

Then, the on-resistance R37 of this transistor increases. This means that the time constant when discharging the capacitor 39 becomes large, and this occurs during the TON period previously explained with the on-resistance R3S of the transistor 35 and Cs of the capacitor 38.
(Similarly, this occurs at the transistor 37 and the capacitor 39, and the TON time in the transistor 37 also increases.) What can be learned from the above explanation is that in order to adjust the delay time, the capacitance can be changed by adjusting the gate length. This means that its own on-resistance also changes.As a result, the delay time when discharging the charge of the next-stage stray capacitor (capacitor 39 in FIG. 3) also changes.

What should be noted here is that the TON during this discharge is different from the TON period explained in FIGS. 3 and 4, and is the next TON period. However, as can be easily understood, changing the capacitance Cs also changes the delay times at other times, which is extremely complicated and inconvenient from the standpoint of setting the delay time td in design. Like this 1
When the constants of a location are changed, the characteristics of a large number of locations change, which is very inconvenient because it takes time to design and the design accuracy is poor.

An object of the present invention is to provide a MOS transistor that solves these problems.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a transistor having a non-rectangular polygonal gate structure such that the on-resistance of the transistor remains constant even if the gate area is changed. This problem is solved by a transistor whose capacitance can be changed independently without changing the on-resistance.

Function The present invention uses a transistor with a gate structure (shape) in which the on-resistance does not change even if the gate capacitance changes, thereby making it extremely easy to design the delay time of the circuit and reducing the variation in delay time. It also has the effect of becoming smaller, making it possible to improve design efficiency and performance.

Embodiment FIG. 1 shows a plan view of a gate structure of a MOS type transistor in an embodiment of the present invention. 11 is silicon P which will form the lower electrode of the gate structure.
or N-shaped diffusion region. Reference numeral 12 denotes an electrode made of polysilicon or aluminum vapor deposited layer forming the upper electrode of the gate structure. Silicon oxide 5iOx (insulator) is present between the diffusion region 11 and the electrode 12, forming a parallel plate capacitor, which is the main part of the operation of the MOS type transistor. 13 and 14 are contact windows for taking out the drain or source electrodes of the MOS transistors, respectively, and are wired to other elements using polysilicon or aluminum layers. 15 is a diffusion region 11 as a lower electrode
The portion facing the upper electrode 12 is essentially a portion of the gate structure, and has a composite shape of a length elo radiation ω1, a length e22 and a width ω2. Note that if a portion corresponding to the area 15.16 of the 11 silicon diffusion layers is P-type, the other portion (forming the drain and source) is N-type and becomes an N-channel MOS transistor, and conversely, the lower diffusion layer If the gate portion of the layer is of N type, the rest of the layer is of P type to form a P channel MOS transistor.

Now, problems with a MOS transistor having the above gate structure are gate capacitance and on-resistance. As mentioned above, the main objective is to provide an electrode structure in which the on-resistance does not change even when the gate capacitance is changed. In this case, the width of the diffusion region 11 must not be changed in terms of practical mask design arrangement efficiency.

As is well known, the gate capacitance is proportional to the gate area, and the proportionality constant is a constant related to the thickness of the gate oxide film, the dielectric constant, etc. On-resistance foil gate length/
gate width).

K2 is a constant that is not related to gate length and gate width.

In Fig. 1, the purpose of the present invention is expressed by an equation. First, for the capacitance, (Co)a = + (ω+ e 1 +ω2 Q
2) holds true. At this time, from the intention of the present invention, the on-resistance of both, ie, the conductance of the reciprocal thereof, is where W and L are equivalent gate width 2 equivalent gate length when the gate surface is regarded as equivalent to a rectangle.

Furthermore, due to the requirements on the mask, ω1+ω2=W (constant). ω+e+ωze so as to satisfy each of these formulas
It is only necessary to design t. Since there are three conditional expressions that must be satisfied and four variables that must be determined, there is a degree of freedom in determining unknowns, and there are an infinite number of solutions. Therefore,
The following ratio ρ is determined as a design parameter, and the shape is designed using this as a parameter.

In this way, the shape of the gate as shown in Fig. 1(a) is obtained, and its shape is (1), (2), (3),
The object of the present invention can be achieved by designing to satisfy equation (4).

Here, we have a solution for ω■ (and Similarly, ω21! Ie2 becomes as follows.

*ρ=50 k=2 However, with N channel enhancement, VT=1 (V),
Vos=5 (v), Cox=0.5 (f F/μm
This is the numerical value for case 2).

[Other Embodiments J Hereinafter, other embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows the gate structure of a MOS type transistor in another embodiment of the present invention. In Figure 2,
21 is a P-type or N-type diffusion region, 22 is a polysilicon or aluminum layer, 23 and 24 are drain and source contact windows, respectively, and 25 is a gate electrode. The structure of the gate electrode is as shown in Figure 2, and its shape is (1
), (2).

The object of the present invention can be achieved by setting so that equations (3) and (4) are satisfied.

Effects of the Invention According to the present invention, by making the planar shape of the gate of an MO3 type transistor into a composite shape other than a rectangular shape, the on-resistance of the MO3 type transistor can be kept constant regardless of the size of the gate capacitance of the MO3 type transistor. This makes it possible to realize an excellent MOS type transistor that can obtain the desired effects.

[Brief explanation of the drawing]

FIG. 1 is a plan view of the gate structure of a device according to one embodiment of the present invention, FIG. 2 is a plan view of the gate structure of another embodiment of the device of the present invention, and FIG. 3 is a circuit diagram of a conventional two-stage coupled CMOS inverter. ,
FIG. 4 is a waveform timing diagram of input signals and output signals to the inverter, and FIG. 5 is a structural plan view of the transistor CMOS inverter on a semiconductor substrate. 11.21 P-type or N-type diffusion region, 1
2.22... Gate polysilicon or gate aluminum electrode, 13.23... Contact window (drain), 14.24... Contact window (source), 15, 16 .25...Gate region, 30...Input terminal, 31...Output terminal, 32.33...Power terminal, 34.36...
...P-channel MOS transistor, 35.3
7...N-channel MOS transistor, 3
8.39...Capacity, 40...Signal line,
41...Input signal, 42...Signal line 4
Waveform of 0, 43...Output signal, 51.54...
...Source electrode, 52.55...Gate electrode, 53.56...Drain electrode. 1l---E Fraud Tank 12--・Z-Toto Electric Shoulder 1 13.14--Co''/9W 1/

Claims (1)

[Claims] A semiconductor device characterized in that the on-resistance of the MOS transistor is kept constant regardless of the size of the gate capacitance of the MOS transistor by making the planar shape of the gate of the MOS transistor a non-rectangular polygon.