JPH02154594A - Digital convergence device - Google Patents

Abstract

PURPOSE:To immediately start up a digital convergence device by adding an initialized period discrimination circuit and a CPU operation period switching circuit to a control part. CONSTITUTION:An initialized period discrimination circuit 2 discriminates whether or not a digital convergence device is in an initialized period and outputs an initialized period discrimination signal 4 to a CPU operation period switching circuit 1. The CPU operation period switching circuit 1 outputs a CPU operation instruction signal 5A in accordance with the inputted initialized period discrimination signal 4. The CPU operation instruction signal 5A, when it is in the initialized period, constantly operates the CPU, and when it is in an ordinary operation period, operates the CPU only in a vertical blanking period. Thus, the digital convergence device can be immediately started up.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital convergence device that can quickly and accurately adjust convergence correction in a color television receiver.

2. Description of the Related Art As is well known, a shadow mask type color cathode ray tube (hereinafter abbreviated as CRT) used in general color television receivers has three electron guns: red, green, and blue. However, since it is structurally impossible to arrange all of these multiple electron guns on the central axis of the CRT, they are mounted a little apart from the central axis and slightly tilted inward with respect to the central axis. Therefore, on the screen on this central axis, each electron beam converges at the shadow mask, and at the same time emit red, green, and blue fluorescent dots through the same hole, resulting in a convergence state.

However, since the radius of curvature of the shadow mask is larger than the distance from the center of deflection to the center of the shadow mask,
At locations other than the central axis of the CRT, the three electron beams converge in front of the shadow mask. Therefore, three electron beams cannot pass through the same hole at the same time, and the color shift, that is, the convergence shift, of the reproduced image increases as it moves away from the center of the screen. To prevent this kind of inconvenience, set the shadow mask to 3 over the entire screen.
It is necessary to perform convergence correction so that the book's electron beam converges.

Furthermore, in a projection type color television receiver that uses three CRTs that emit light in three primary colors to project enlarged images onto a screen, the angle of incidence of the CRT onto the screen differs for each CRT, resulting in color shift on the screen.

The superposition of these three primary colors, the so-called convergence, is achieved by - For boat fishing, a method is used to obtain a convergence correction waveform in an analog manner using passive elements such as L, C, and R, rather than a horizontal flyback pulse and a vertical deflection waveform. However, there is a problem with convergence accuracy.

In contrast, a method of digitally performing convergence correction has been proposed as a method of performing convergence with higher precision. The concept is to project a convergence correction pattern such as a crosshatch on the screen, digitally write the convergence correction amount data for each intersection in one frame memory, and read out this information in synchronization with horizontal and vertical scanning. Then, D/A conversion and amplification processing are performed to perform convergence correction.

An example of the digital convergence correction described in item 1 will be described below with reference to the drawings.

FIG. 3 is a diagram showing a conventional CPU operation period, and FIG. 4 is a block diagram of a digital convergence device.
FIG. 5 is a diagram showing a state in which a crosshatch, which is a signal for convergence adjustment, is displayed.

As shown in FIG. 5, the control unit 13 displays crosshatches 30 on the screen that indicate adjustment points in, for example, 9 columns in the horizontal direction and 7 rows in the vertical direction.
The image is displayed from the convergence adjustment signal output terminal 23. The intersection of these crosshatches 30 becomes the adjustment point. The control unit 13 receives signals input from the horizontal synchronization signal input terminal 24, vertical synchronization signal input terminal 25, and clock input terminal 26, and digital convergence control data from the data buffer random access memory 17 to the CPU 14 and the nonvolatile 1-frame memory. 16. Generates a control signal 27 for controlling the one-frame random access memory 15, data buffer random access memory 17, etc., controls the digital convergence device, outputs a pattern signal for convergence correction, and interfaces the control panel 18 and CPU 14 It is carried out.

First, when an adjustment point is selected on the control panel 18 of FIG. 4, the CPU 14 obtains the cursor address of the adjustment point. At this time, the addresses of the nonvolatile one-frame memory 16 and data buffer random access memory 17 are also obtained. In addition to an area for storing digital convergence control data and correction amounts for all adjustment points of the crosshatch 30, a stack area and a working area used by the CPU 14 are allocated to the data buffer random access memory 17. After the above operation, the control unit 14 displays the cursor 31 at the corresponding adjustment point on the screen. Next, select the color you want to correct on the control panel 18.
Cursor 3 on the screen indicates the selected adjustment point.
1, perform convergence adjustment using the adjustment key on the control panel 8, and write the desired correction amount to the previously specified address of the data buffer random access memory 17. When a certain period of time has elapsed after the adjustment key operation is completed, the above-mentioned correction amount is written into the non-volatile one frame memory 16. The same procedure is then performed for all adjustment points sequentially.

Hereinafter, the same process is performed for other colors.

Next, reading out the convergence correction amount written in the data buffer random access memory 17 will be explained. Since the correction amounts written in the data buffer random access memory 17 are only for the positions corresponding to the adjustment points shown in FIG. 4, it is necessary to perform interpolation for each scanning line between adjustment points in the vertical direction. . Therefore, for example, the data buffer random access memory 17
The CPU 14 interpolates the correction amount for each scanning line included between the adjustment points in the first and second rows using the correction amounts in the first and second rows read out. and writes it into the one-frame random access memory 15. Thereafter, the correction amount for each scanning line written in the 1-frame random access memory 15 is read out, converted into an analog signal by the D/A converter 9, and filtered by a low-pass filter (LPF).
) 20, amplified by an amplifier 21, and then supplied to a convergence coil (not shown) from a convergence correction signal output terminal 22.

Incidentally, during the convergence adjustment operation, the correction amount for each adjustment point is written into the nonvolatile one-frame memory 16, and this is for backing up the correction amount for each adjustment point. When the power of the digital convergence device is turned off, the correction amount written in the data buffer random access memory 17.1 frame random access memory 15 disappears. However, non-volatile 1
The frame memory 16 stores the written correction amounts for each adjustment point as they are. Therefore, when the power is turned on, the correction amount for each adjustment point stored in the non-volatile one frame memory 16 is written to the data buffer random access memory 17, and each adjustment written in the data buffer random access memory 17 is Point correction amount by CPU
By performing an interpolation calculation in step 14 and writing the correction amount for each scanning line into the one-frame random access memory 15, it is possible to eliminate the trouble of re-adjusting each time the power is turned on. (Hereinafter, the time from when the power is turned on to the digital convergence device to when the correction amount for each scanning line is written to the random access memory 15 for one frame is abbreviated as the initialization period.) Next, the operation of the interpolation calculation method is as follows. will be explained in detail.

Correction amounts for adjustment points in nine columns in the horizontal direction and seven rows in the vertical direction are stored in a non-volatile one-frame memory 16.

When the television receiver is turned on, the correction amount for each adjustment point in the nonvolatile one-frame memory 16 is written to a designated address in the data buffer random access memory 17. At this point, the position corresponding to the adjustment point shown in Figure 4 (
There is only a correction amount for the intersection point of the crosshatch 30). Therefore, the amount of correction for each scanning line between adjustment points is obtained by approximate calculation in the CPU 14 using the amount of correction for each adjustment point written in the data buffer random access memory 17, and the calculation result is stored in the one frame random access memory 15. By writing to the designated address, the correction amount for all scanning lines will be written to the random access memory 15 for one frame.

The above approximate calculation is obtained as follows. As shown in Fig. 4, for example, the change amount for each scanning line between the adjustment points is calculated from the correction amount a of the first line and the correction amount a of the second line, and this change amount and the correction amount of the second line are calculated. The correction amount for each scanning line is determined by adding up the amounts. In other words, in the basesense device, the CPU 14
is key scanning of the control panel 8, changing the correction amount at each adjustment point, interpolation calculation to obtain the correction amount for each scanning line from the correction amount at each adjustment point, and scanning line to the 1-frame random access memory 15. Processes such as writing the correction amount for each time and detecting the horizontal frequency are performed. However, the above CP
If the process U14 is performed during the vertical scanning period 8 shown in FIG. 3, the screen will be affected and the image will be distorted. Therefore, the CPU 14
is operated only during vertical blanking period 7 (as for the horizontal blanking period during the vertical scanning period, the time is short, so the CPU 14 is stopped), and vertical scanning period 8 is operated.
During this period, the operation of the CPU 14 is stopped, and the random access memory 15 for one frame is controlled by a control signal output from the control unit 13.
The convergence correction is performed by outputting the correction amount for each scanning line stored in the D/A converter.

In the digital convergence device described above, the adjustment points can be arbitrarily corrected independently, so that convergence correction can be performed with high accuracy. In FIG. 4, 28 represents an address bus, and 29 represents a data bus.

Problems to be Solved by the Invention The amount of correction for each scanning line is obtained by interpolating the amount of correction at adjustment points above and below the scanning line using the CPU, but it is difficult to calculate the amount of correction for all scanning lines on the screen. It takes a lot of time to find out.

In conventional systems, the operating period of the CPU is set within the vertical blanking period in any state.

For example, even if the convergence adjustment has already been completed, once the power is turned off, the convergence correction amounts for all adjustment points stored in the data buffer random access memory and all scanning lines stored in the 1-frame random access memory will be adjusted. The convergence correction amount disappears. Therefore, when the power is turned on, the correction amounts for all adjustment points backed up in the non-volatile 1 frame memory are written to the data buffer random access memory.
Based on the correction amount, the CPU interpolates the correction amount for each scanning line between the vertical adjustment points, and writes the correction amount for all scanning lines into one frame random access memory. Normal convergence will not occur unless the initialization period ends. Cannot be corrected.

In conventional digital convergence devices, the operating period of the CPU that performs the above processing is always set within the vertical blanking period, so the initialization period is quite long, and even when the power is turned on, convergence correction of the entire screen cannot be performed normally. The drawback was that it took a considerable amount of time before it was implemented.

In view of the above problems of the present invention, the CPU is always operated during the initialization period regardless of the vertical blanking period, and when the normal operation period begins, the CPU operation period is set to the vertical blanking period. To provide a device which greatly shortens the initialization period and allows a user to enjoy a convergence-corrected image on the entire screen immediately after turning on a color television receiver.

Means for Solving the Problems In order to solve the above problems, the digital convergence device of the present invention is provided with means for determining whether or not the initialization period is in progress, and if the initialization period is in progress, C
The PU is always operated, and during the normal operation period, the CPU operation period is set to a vertical blanking period.

Effects According to the present invention, the initialization period after turning on the power can be made much shorter than in the past, and the digital convergence device can be started up quickly.

EXAMPLE Hereinafter, a digital convergence device according to an example of the present invention will be described with reference to the drawings.

First, an explanation of the operation of the digital convergence device in this embodiment will be omitted since it is the same as that of the conventional system shown in FIG. 3.

FIG. 1 is a functional block diagram showing a CPU operation period switching section in the control section of a digital convergence device according to an embodiment of the present invention, and FIG. 2 is a functional block diagram showing the operation of the CPU of the digital convergence device according to an embodiment of the present invention. It is a figure showing a period.

The operation will be explained below.

In FIG. 1, the initialization period determination circuit 2 determines whether the digital convergence device is currently in the initialization period, and the CPU operation period switching circuit 1 determines whether the digital convergence device is currently in the initialization period.
The initialization period determination signal 4 is outputted to. The CPU operation period switching circuit 1 outputs a CPU operation instruction signal 5A as shown in FIG. 2 in accordance with the input initialization period determination signal 4. The CPU operation instruction signal 5A always operates the CPU 14 during the initialization period.
During normal operation, C only during the vertical blanking period.
Operate PU14.

As described above, in this configuration, by adding the CPU operation period switching circuit 1 and the initialization period determination circuit 2 to the control section 13, it becomes possible to switch the operation period of the CPU 14, so that the initialization period after turning on the power can be changed. This allows the digital convergence device to be started up quickly, and after the initialization period ends, the convergence correction amount at each adjustment point can be adjusted without affecting the screen, just like with conventional digital convergence devices. or perform convergence correction operations.

Effects of the Invention As described above, the present invention adds an initialization period determination circuit and a CPU operation period switching circuit to the control section, thereby making the initialization period after power-on longer than the conventional one without affecting normal operation. It is also possible to shorten the length considerably, allowing the digital convergence device to be started up quickly.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing a CPU operation period switching section in the control section of a digital convergence device according to an embodiment of the present invention, and FIG. FIG. 3 is an explanatory diagram showing the operating period of the CPU of a conventional digital convergence device, FIG. 4 is a block diagram of the digital convergence device, and FIG. FIG. 1...CPU operation period switching circuit, 2...
. . . Initialization period discrimination circuit, 3 . . . Vertical blanking signal input section, 4 . . . Initialization period discrimination signal, 5 . . . CPU operation instruction signal output section, 6 ... Vertical blanking signal, 7
・・・・・・Vertical blanking period, 8・・・・・・
Vertical scanning period, 9... Initialization period, 1
0...Normal operation period, 11...Microcomputer operation period, 12...Microcomputer stop period, 13
...Control unit, 14...CPU, 15.
...1 frame random access memory, 16.
...Non-volatile 1 frame memory, 17...
・Data buffer memory, 18...Control panel, 19...D/A! [,20...
...LPF, 21...Amplifier, 22...
...Convergence correction signal output terminal, 23...
- Convergence adjustment signal terminal, 24...Horizontal synchronization signal input terminal, 25...Vertical synchronization signal input terminal, 26...Clock input terminal.

Claims (1)

[Claims] Means for generating a convergence correction pattern so that the screen of a color television receiver has a plurality of convergence adjustment points in the horizontal and vertical directions; and inputting position information of the convergence adjustment points into a data buffer random access memory. means for writing a correction amount for a specified adjustment point into a corresponding address of a data buffer random access memory and a non-volatile one frame memory; and a means for writing a correction amount corresponding to all scanning lines from the data buffer random access memory. Means for calculating one frame by approximate calculation using the read adjustment point correction data and writing it to the address corresponding to the scanning line of the random access memory, and a non-volatile one frame for backup from when the power is turned on again after the power is turned off. Means for calculating the correction amount for all scanning lines by approximate calculation from the correction amount for each adjustment point transferred from the memory to the data buffer random access memory, determining the initialization period until writing one frame to the random access memory, and outputting a determination signal. and a means for switching the operating period of the CPU according to the above-mentioned discrimination signal, and during the initialization period, the CPU
1. A digital convergence device characterized in that U is always moved and the CPU operation period is set within a vertical blanking period during a normal operation period.