JPS62245790A - Digital convergence device - Google Patents

Abstract

PURPOSE:To reduce the number of memories by providing a channel memory storing correction data for a designated color only at the adjustment of convergence correction and a correction pattern selection circuit. CONSTITUTION:A channel memory 24, a correction pattern selection circuit 22 and a switching circuit 25 are provided, and only a green color being a reference and a color desired to be adjusted are displayed at the convergence adjustment, only the correction data of the colors is transferred to the channel memory 24 to rewrite the correction data and to apply the convergence correction. After the end of adjustment, the correction data are read from the 1st frame memory 14. Thus, the number of the channel memories 24 as buffer memories of the 1st frame memory 14 si reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital convergence device that can accurately adjust up to the periphery of the screen in a device for correcting the convergence of a color television receiver.

Conventional technology A general color television receiver has three electron guns for red, blue, and green, but these multiple electron guns are used for color CR.
Since it is structurally impossible to arrange it on the central axis of the T, it is installed slightly away from the central axis and slightly tilted inward with respect to the central axis. Therefore, on the screen on this central axis, each electron beam converges at the shadow mask, and simultaneously passes through the same hole to emit red, blue, and green fluorescent dots, creating a convergence state. However, at locations other than the central axis of the CRT, the radius of curvature of the shadow mask is larger than the distance from the deflection center to the center of the shadow mask, so three electron beams cannot pass through the same hole at the same time. In the reproduced image, the color shift, that is, the convergence shift, increases as the distance from the center of the screen increases. In order to prevent such problems, it is necessary to perform convergence correction over the entire screen so that the three electron beams converge at the shadow mask.

Generally, there is a method of obtaining an analog convergence correction waveform by using a horizontal flyback pulse, a vertical deflection waveform, and passive elements such as υL, C, and R, but this method has a problem in terms of accuracy. As a method of performing convergence correction with high precision over the entire screen and with easy adjustment, there is a digital convergence device such as that disclosed in Japanese Patent Publication No. 59-8114.

In the conventional example described above, the concept is to project a pattern for convergence correction such as a cross hatch on the screen, digitally write data on the amount of convergence correction for each cross point in the frame memory, and read out this information. It performs D/A conversion to obtain a convergence correction signal. A conventional digital convergence device will be explained below with reference to FIGS. 2 and 3.

In FIG. 2, the screen on which convergence is to be corrected is shown, where 1 is the screen of the receiver, 2 is a convergence correction pattern, and 3 is an adjustment point.

FIG. 3 shows a configuration diagram of a conventional digital convergence device, and 4 shows selection of adjustment points.

A control panel for specifying colors and instructing to increase/decrease correction data, 6 a cursor counter that generates addresses for adjustment points specified on the control panel 4, 6 vertical and horizontal synchronization signal input terminals, and 7 a horizontal synchronization signal input terminal. a clock generation circuit that generates a synchronized clock using a PLL circuit (not shown); 8 a correction pattern generation circuit that outputs a correction pattern for correcting convergence;
9 is a cursor generation circuit that displays the point to be adjusted on the screen; 10 is a mixing circuit that mixes the outputs of the cursor generation circuit 9 and the correction pattern generation circuit a and displays it on the screen; 11 is a circuit in the first frame memory; The first one controls writing and reading.
a frame memory control circuit; 12 is a coincidence detection circuit that supplies a signal to the cursor generation circuit 9 when the address of the first frame memory control circuit 11 and the cursor counter 5 match;
13 is a first address multiplexer for switching the write/read address of the first frame memory; 14 is a first address multiplexer;
The frame memory is an electrically erasable and writable memory that can store information even when the power is turned off, and stores correction data for all adjustment points. 16 is a reversible counter that increases or decreases the correction amount of the adjustment point to be corrected; 16 is a second frame memory control circuit that controls writing and reading of the second frame memory; and 17 is a control circuit that controls writing and reading addresses of the second frame memory. A second address multiplexer 18 stores the same correction data as the contents of the first frame memory 14, but a second frame memory 19 stores adjustment data in synchronization with the scanning of the television receiver. 20 is a D/A converter that converts a digital signal into an analog signal, and 21 is an LPF that performs correction amount processing in the horizontal direction.

The operation of the digital convergence device configured as described above will be described below. Here, a digital convergence device that performs convergence correction of red and blue using green as a reference will be explained.

First, after turning on the power (not shown), the hummersence device connects the first frame memory control circuit 11, the second frame memory control circuit 16, and the first address multiplexer 13.
Then, the second address multiplexer 17 controls to transfer all the correction data in the first frame memory 14 to the second frame memory 18. This transfer is performed during a period unrelated to the display screen of the display, for example, a vertical blanking period, when the power is turned on or when correction data is rewritten. The correction data transferred to the second frame memo 1J18 is read out in synchronization with the scanning of the display, and is supplied to the interpolation calculation circuit 19. The interpolation calculation circuit 19 obtains the correction data of the scanning line for which there is no correction data between the adjustment points from the upper and lower two points by interpolation calculation, supplies it to the D/A converter 2o, converts it into an analog signal, and supplies it to the LPF 21. A horizontal smoothing process is performed and a convergence correction signal is supplied to a convergence coil (not shown).

Next, convergence correction will be explained. This is processed by increasing/decreasing and rewriting the correction data in the frame memory 18. First, the convergence correction pattern is generated from the synchronization signal 6, the clock generation circuit 7, and the correction pattern generation circuit 8 as shown in FIG. The pattern is projected and the color and adjustment points to be adjusted are indicated on the control panel 4. The adjustment point specified on the control panel 4 generates its address information from the cursor counter 6, and the match detection circuit 12 outputs the address information from the cursor counter 6 to the first . Multiplexer 13 for second address
, 17. The coincidence detection circuit 12 supplies a coincidence signal to the cursor generation circuit 9 only when there is a coincidence with the address information of the first frame memory control circuit 11. Based on the coincidence signal, the cursor generation circuit 9 generates a signal such that the cross point of the adjustment point blinks, for example, and supplies it to the mixing circuit 1o, where it is mixed with the crosshatch signal of the correction pattern generation circuit 8.
displayed on the screen. The correction data for the adjustment point selected on the control panel 4 is sent to the address specified by the cursor counter 6 via the second address multiplexer 17 i2.
It is read by supplying it to the frame memory 18 and taken into the reversible counter 16. Next, the contents of the reversible counter 16 are increased or decreased using an increase/decrease key (not shown) on the control panel 4, written into the first frame memory 14, and further transferred to the second frame memory 1B. The increased/decreased correction data is sequentially read out from the second frame memory 18 in synchronization with the scanning of the screen display, and is sent out as a convergence correction signal. As mentioned above, the first. By rewriting the contents of the second frame memories 14 and 181, highly accurate convergence correction signals can be obtained.

Problems to be Solved by the Invention However, in the above configuration, the first frame memory 14 is a storage element whose data does not disappear even when the power is turned off.
For example, E2FROM (electrically erasable and writable ROM)
). However, such a memory element has a sufficiently fast read speed, but a write speed of about 10 m5eC, which is very slow compared to the read speed. Therefore, it is necessary to process the contents of the first frame memory 14 using the second frame memory 18, which is capable of high-speed processing like the conventional device. Therefore, a memory having the same capacity as the first frame memory 14 is required, resulting in an increase in cost and a larger circuit scale. In view of this point, the present invention provides a digital convergence device that reduces the memory capacity of the second frame memory 18.

Means for Solving the Problems The present invention provides a channel memory that stores correction data for only a specified color when adjusting convergence correction, and a correction pattern selection circuit that displays the specified color and a reference color. , a digital convergence device that includes a correction pattern selection circuit that controls reading and writing of the channel memory, and a switching circuit that switches the output of the first frame memory and the channel memory.

Operation The present invention has the above-described configuration, and includes a correction pattern selection circuit and a correction pattern generation circuit that display a color specified on the control panel 4 and a reference green crosshatch;
A channel memory and a channel control circuit are provided to read and store the correction data of the specified color from the first frame memory, and when making adjustments, write the correction data of the color you want to adjust to the channel memory, rewrite the correction data, perform the correction, and make the adjustment. After completion, the convergence device reads the correction data from the first frame memory and obtains the convergence correction signal.

Embodiment FIG. 1 shows a configuration diagram of a digital convergence device in an embodiment of the present invention. In FIG. 1, components that operate in the same manner as in the prior art are given the same numbers, and their explanations will be omitted. Reference numeral 22 denotes a correction pattern selection circuit that displays a correction pattern of the color specified on the control panel 4 and a reference green, and a channel memory 24 that reads correction data for only the color specified at the time of convergence adjustment from the first frame memory 14. 24 is a channel memory that stores correction data only for a specified color and is read out in synchronization with scanning; 25 is a channel memory for convergence adjustment; 24 and the output of the first frame memory 14 after adjustment is completed.

The operation of the digital convergence device of this embodiment configured as described above will be described below.

First, a color to be adjusted is designated on the control panel 4, and a color designation signal is supplied to the correction pattern selection circuit 22, the first frame memory control circuit 11, and the channel memory control 23. The correction pattern selection circuit 22 controls the correction pattern generation circuit 8 to display a correction pattern of the specified color and the standard green, and the correction pattern generation circuit 8 controls the correction pattern generation circuit 8 to display the specified color and the reference green correction pattern. A crosshatch pattern of red) and standard green is displayed on the screen. The first frame memory control circuit 11 and the channel memory control circuit 23 control the transfer of correction data of a specified color from the first frame memory 14 to the channel memory 24. After the transfer is completed, the switching circuit 26 switches the channel memory 24 so that it is output, and the convergence correction signal of only the specified color is supplied to the convergence coil, and thereafter the adjuster performs the convergence correction in the same manner as before. . After the adjustment is completed, the correction pattern selection circuit 22 and the correction pattern generation circuit 8 select red.

At the same time that green and blue are displayed, the 1 switching circuit 25 is switched so that the first frame memory 14 is output, and a convergence-corrected signal is supplied to the convergence coil. This switching circuit 26 may be controlled manually from the control panel 4, but the output of the channel memory 24 is sent out only when a color is specified and an increase/decrease key (not shown) is controlled. It is also possible to automatically control the

As described above, according to this embodiment, the channel memory 24
and a correction pattern selection circuit 22 and a switching circuit 26,
During convergence adjustment, only the color to be adjusted and the reference green are projected, and only the correction data for that color is transferred to the channel memory 24, the correction data is rewritten, convergence correction is performed, and after the adjustment is completed, the first frame By reading the correction data from the memory 14, it is possible to reduce the number of channel memories 24 used as the first frame memory 140 and the back 7 memory.

As described in detail, according to the present invention, it is possible to reduce the memory, reduce the cost, and downsize the circuit, which has great practical effects.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a digital convergence device according to an embodiment of the present invention, FIG. 2 is a diagram of a correction pattern for performing convergence correction, and FIG. 3 is a block diagram of a conventional digital convergence device.

Claims (1)

[Claims] a first frame memory that stores convergence correction data at a predetermined convergence adjustment point as nonvolatile information;
A correction pattern generation circuit that projects a convergence correction pattern, a control panel that instructs color selection during convergence adjustment, and a correction pattern selection that selects and controls the color of the projected convergence correction pattern by color selection. a channel memory for reading out and storing the correction data specifying the color from the first frame memory, and a switching circuit for switching the output of the first frame memory and the channel memory, and the correction data of the channel memory is read out during convergence adjustment. A digital convergence device characterized in that after adjustment is completed, the correction data in the first frame memory is used as a convergence correction signal.