JPH02154375A - Method and device for controlling mute - Google Patents

Abstract

PURPOSE:To prevent fluttering of mute control by performing the mute control when the number of code errors at every prescribed period of time detected at every prescribed number of data blocks exceeds the 1st value and canceling the mute control when the number becomes the 2nd value. CONSTITUTION:The number of code error detecting signals (b) at every prescribed number of data blocks is fetched to a latch circuit 15 and the value (e) of the circuit 15 is compared with a prescribed number (m) at the 1st comparator 16. When e>=m, 'L' is outputted as the 1st comparison output (f) and, when e<m, 'H' is outputted. The 2nd comparator 17 outputs 'L' when e<=n (n<m) and 'H' when e>n. A delaying device 18n delays the 2nd comparison output (g) by prescribed time and an SR flip flop 19 is set when the 1st comparison output (f) is 'L' and reset when the output (g') of the device 18 is 'L'. Thus mute control is performed when code errors occur more than a prescribed number of times (m) and canceled when the occurring frequency of the code errors becomes smaller than the number (n). Therefore, fluttering of the mute control can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a mute control method and control device during playback of a digital audio playback device.

Conventional technology Conventionally, in digital audio playback devices.

If a code error in the reproduced digital audio data is detected and the erroneous data cannot be corrected, the average value of the previous and subsequent digital audio data is used, or the previous value is held and digital-to-analog conversion is performed and output. Furthermore, if code errors occur frequently and the frequency of the above-mentioned mean value interpolation and previous value hold increases, distortion becomes noticeable in the analog audio signal after digital-to-analog conversion, making it undesirable for the auditory sense. Therefore, control was carried out to mute the output of analog audio signals when code errors occurred more than a certain frequency (Japanese Patent Application Laid-Open No. 1103-1983).
(See Publication No. 80).

A conventional mute control method will be described below with reference to the drawings. FIG. 3 is a block diagram showing a digital audio signal reproducing device, FIG. 4 is a block diagram showing a conventional mute control device, and FIG. 6 is a timing chart showing the operation of the conventional mute control device.

In FIG. 3, 21 is an input terminal for a reproduced digital audio signal, 22 is a deinterleaf decoder, 23 is a time axis converter, and 24 is a digital to analog converter (DA
C), 26 is a mute control device, and 26 is an audio output terminal. In FIG. 4, 11 is an input terminal for a clock synchronized with the error correction processing cycle, 12 is an input terminal for a code error detection signal, 13 is a counter, 14 is a frequency divider, 1
6 is a latch circuit, 36 is a comparator, a and b are each third
A first clock synchronized with the error correction processing cycle output from the deinterleaf decoder 22 in the figure, a code error detection signal, C a second clock obtained by dividing the first clock by a predetermined number, d is the count value of the counter 13, e
is the output of the latch circuit 16, and i is the output of the comparator, that is, the mute control signal.

First, a predetermined interleaf during recording is removed from the reproduced digital audio signal by a deinterleaf decoder 22, and error detection and correction during reproduction is performed for each predetermined data block. The time axis converter 23 restores the digital audio signal output from the deinterleaf decoder 22 to its original sampling period and sends it to the DAC 24 . The DAC 24 converts the digital audio signal into an analog signal and outputs it. In the mute control device 25, when a code error detected by the deinterleaf decoder occurs in a predetermined number of positions at a predetermined time,
A control signal for muting the output of 24 is output.

Figures 4 and 6 are mute control% f4 in Figure 2.
An example of the configuration and its operation is shown below.

4 and 5, the counter 13 outputs the first signal only when the code error detection signal is at a high level (hereinafter abbreviated as H).
The number of code errors for each predetermined data block is counted by counting the clock a of . The frequency divider 14 divides the first clock a by a predetermined number and generates a second clock C.
Output.

At the timing of the rising edge of the second clock C, the count value d of the counter 13 is set in the latch circuit 16.
By clearing the counter 13 at the same time as taking in the number of code error detection signals for each predetermined number of data blocks, the latch circuit 15 can take in the number of code error detection signals for each predetermined number of data blocks.

The numerical value e of the code error detection signal for each predetermined number of data blocks outputted from the latch circuit 15 is compared with a predetermined number m in the comparator 36, and when the value is 02m, H is output as the comparison output 1. Further, when e(m), a low level /L/ (hereinafter abbreviated as below) is output as a comparison output l.

In this way, when code errors occur at a predetermined frequency m or more,
The comparator 38 outputs H, and then outputs L only when it becomes smaller than m. The DAC 24 performs mute control when the output of the comparator 36 is H, and cancels it when the output is L.

Problems to be Solved by the Invention However, when reproducing digital audio signals using two magnetic heads on a rotating cylinder in a helical scan type VTR, for example, variations in the performance of the two magnetic heads (A head, B head) may occur. The frequency of occurrence of code errors during playback may vary.

Furthermore, the reproduction state changes over time due to tension fluctuations in the magnetic tape running system, and the frequency of occurrence of code errors changes over time.

Due to the above two factors, helical scan VTR
When the tracking state of m is removed, the frequency of occurrence of code errors may fluctuate above and below m over time. At this time, the mute control signal i fluctuates between H and L, and at the same time, the output of the DAC 24 has the problem of repeating mute control and mute release operations in a normal VTR state, which is undesirable for the audibility. Ta.

Means for Solving the Problems In order to solve the above problems, the mute control method of the present invention encodes a digital audio signal, applies a predetermined interleaf, reproduces the recorded data, and detects and corrects code errors. In this process, code errors are detected for each predetermined data block, and when the code error frequency reaches a predetermined first value m or more, muting control is performed, and the code error frequency is set to a predetermined second value n(m). The present invention is characterized in that the mute control is canceled when the condition becomes n).

According to the present invention, with the above-described configuration, it is possible to realize mute control without fluctuating mute control even when the reproduction condition of the digital audio signal reproduction apparatus is poor.

EMBODIMENTS Below, a mute control device of the present invention will be described with reference to the drawings. FIG. 1 shows a mute control device according to an embodiment of the present invention. FIG. 2 shows a timing chart showing the operation of the mute control device according to one embodiment of the present invention. In FIG. 1, 11 is an input terminal for a clock synchronized with the error correction processing cycle, 12 is an input terminal for a code error detection signal, 13 is a counter, 14 is a frequency divider, 16 is a latch circuit, and 16 is a first a comparator, 17 is a second comparator,
18 is a delay device, 19 is an SR flip-flop, and a and b are deinterleaf decoders 22 in FIG. 3, respectively.
A first clock synchronized with the error correction processing cycle outputted by the code error detection signal, C is a second clock obtained by dividing the first clock by a predetermined number, and d is the count value of the counter 13. , e are the outputs of the latch circuit 15, f and q are the first and second comparison outputs, respectively, and l is the SR flip-flop 1.
19 shows the output of step 19, that is, the mute control signal.

The operation of the mute control device configured as described above will be described below with reference to the drawings.

In FIGS. 1 and 2, the counter 13 counts the first clock a only when the code error detection signal is at a high level (hereinafter abbreviated as H), thereby detecting code errors in each predetermined data block. Count the numbers. Frequency divider 14
Then, the first clock a is frequency-divided by a predetermined number and a second clock C is output.

At the timing of the rising edge of the second clock C, the count value d of the counter 13 is set in the latch circuit 16.
By clearing the counter 13 at the same time as the number of code error detection signals for each predetermined number of data blocks is taken in, the latch circuit 16 can take in the number of code error detection signals for each predetermined number of data blocks.

The numerical value e of the code error detection signal for each predetermined number of data blocks output from the latch circuit 16 is determined by the first comparator 1.
6, it is compared with a predetermined number m, and when it is 02m, L is output to the first comparison output f.

Further, when e (m), H is output to the first comparison output f.

The second comparator 17 outputs L as the second comparison output q when e≦n(n(m), and outputs H when e ) n. The delay device 18 delays the second comparison output by a predetermined time. The SR flip-flop 19 is set when the first comparison output f is L, and is reset when the output q' of the delay device 18 is L.

In this way, when code errors occur at a predetermined frequency m or more,
The SR flip-flop 19 outputs H, and then outputs L only when the value becomes smaller than n. The DAC 24 performs mute control when the output of the SR flip-flop 19 is H, and cancels it when the output is L.

Effects of the Invention As described above, according to the present invention, even if the frequency of occurrence of code errors changes over time due to variations in performance or tension fluctuations of the two magnetic heads when the playback condition of the digital audio signal playback device is poor, Mute control without fluctuating mute control can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a mute control device according to an embodiment of the present invention, FIG. 2 is an operation timing chart of the device,
FIG. 3 is a block diagram of a digital audio signal reproducing device, FIG. 4 is a block diagram of a conventional mute control device, and FIG. 5 is a timing chart showing the operation of the conventional mute control device. 11... Code error detection signal output, 12...
...first clock input, 13...counter,
14... Division cycle, 16... Latte circuit, 16... First comparator, 17... Second comparator, 18...・・・Delay device, 19----“
SR flip-flop, pump. Name of agent Patent attorney Shigetaka Awano and 1 other person

Claims (2)

[Claims] (1) Used in a digital signal processing device that encodes a digital audio signal, applies a predetermined interleaf, reads the recorded data, detects code errors, and corrects them. Mute control is performed when the number of code errors per time exceeds a predetermined first value m, and mute control is performed when the number of code errors reaches a predetermined second value n (m>n). A mute control method characterized by canceling the mute. (2) A mute control device used in a digital signal processing device that encodes a digital audio signal, applies a predetermined interleaf, and reproduces and decodes recorded data, the mute control device is a mute control device that reproduces and decodes data recorded by encoding a digital audio signal and applying a predetermined interleaf. an error detector that detects code errors and outputs an error determination signal; and an error detector that receives the error determination signal, counts the number of code errors for each data field consisting of a predetermined number of data blocks, and outputs the count value. a first comparator that outputs a first detection signal when the count value is greater than or equal to a predetermined value m;
m>n) a second comparator that outputs a second detection signal when the following: a delay device that delays the second detection signal by a predetermined time; A mute control device comprising a set-reset flip-flop that is reset from the output of the flop and outputs a mute control signal.