JPH02152319A - Phase comparing circuit - Google Patents

Abstract

PURPOSE:To shorten a synchronous pulling-in time and to generate phase difference information by obtaining an exclusive logical sum between a timing clock at the change point of an input signal and the identifying signal of a logical level, and executing phase comparison between this exclusive logical sum and the input signal. CONSTITUTION:The logical level of a timing clock 102 at the rising point of an input signal 101 is identified by a D-FF1 and an identified output signal 103 and the clock 102 are outputted as an exclusive logical sum signal 104 by an EX-OR 2. The signal 104 and input signal 101 are outputted as an exclusive logical signal 105 by an EX-OR 3. The signal 105 is passed through a NOT gate 4 and defined as a logical refusing signal 106. For the signals 105 and 106, a difference signal 107 of those signals is obtained as a phase comparing signal by a differential amplifier 5. As a result, an instable pulling-in phase is changed to a stable pulling-in phase.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase comparison circuit that compares the phase difference between an input signal and a timing clock in digital communication and generates an output corresponding to the phase difference.

``Prior Art'' Conventionally, there is a circuit shown in FIG. 9 as a phase comparison circuit that compares the phase difference between an input signal and a timing clock and generates an output corresponding to the phase difference. The circuit of FIG. 9 includes an exclusive OR gate EX-OR which outputs an exclusive OR of an input signal and a timing clock, and the exclusive OR gate
Logical negation gate N that outputs the logical negation of the output of X-OR
OT, and a differential amplifier AMP which takes the difference between the output of the exclusive OR gate 1EX-OR and the output of the logical NOT gate 1EX-OR. The phase comparison signal which is the phase difference information between the input signal and the timing clock is 1ii
It is obtained as the output of the J differential amplifier AMP.

FIG. 10 is a time chart showing the operation of the circuit in FIG. 9 when an input signal having a phase difference of π/2 from the timing clock is input as the input signal in FIG. As can be seen from the time chart of FIG. 10, in the circuit of FIG. 9, when the phase difference between the input signal and the timing clock is π/2, the average value of the phase comparison signal for each cycle becomes zero. Also, the first
FIG. 1 is a time chart showing the operation of the circuit in FIG. 9 when an input signal having a phase difference of 3π/2 from the timing clock is manually input as the input signal in FIG. As can be seen from the time chart of FIG. 11, in the circuit of FIG. 9, even when the phase difference between the input signal and the timing clock is 3π/2, the average value of the phase comparison signal for each round FJI becomes zero. Therefore, the phase difference between the input signal and the timing clock is π/2.
It can be seen that in the two phase states of and 3π/2, the average value of the phase comparison signal for each cycle becomes zero.

Consider the case where the above phase comparison circuit is applied to a PLL1 circuit. The PLL circuit controls the phase of the timing clock using a signal obtained by averaging the phase comparison signal, which is the output signal of the phase comparison circuit, over several cycles. Specifically, the phase comparison signal is passed through a low-pass filter to remove alternating current components of the phase comparison signal. Here, the signal obtained by this operation will be referred to as a DC level signal. The DC level signal of the phase comparator circuit in Figure 9 is the DC component of the output of the differential amplifier AMP, and in the case of the phase comparison signals in Figures 10 and 11, the area of the pulse above "0" level is “
Corresponds to the difference in area of the pulses below the 0'' level.

The graph in FIG. 12 shows the relationship between the phase difference between the input signal and the timing clock and the DC level signal. As can be seen from Fig. 12, in the section where the phase difference is from O to π, as the phase difference increases, the DC level signal also increases;
In the interval from 2π to 2π, the DC level signal becomes smaller as the phase difference becomes larger. 0 and 1I, the DC level signal becomes zero at two locations where the phase difference is π/2 and 3π/2, as described in the explanation.

The PLL circuit performs control by comparing the DC level signal with a certain reference level.

Therefore, the phase where the DC level signal becomes equal to the reference level becomes the pull-in phase.

For example, FIG. 12 shows the case where the atmosphere level is used as the reference level. Further, as shown in FIG. 12, two pull-in phases occur no matter where the reference level is set.

Control of a normal PLL circuit is set as follows.

(1) When the DC level signal becomes larger than the reference level, the phase difference is reduced.

(2) When the DC level signal becomes smaller than the reference level, the phase difference is increased.

Therefore, according to the characteristics shown in Fig. 12, in the section where the phase difference is from 0 to π, the DC level signal increases as the phase difference increases, so the PLL circuit operates to reduce the phase difference and the reference level pull-in phase in this section. to lock. However, in the section where the phase difference is from π to 2π, as the phase difference increases, the DC level signal becomes smaller, so the PLL circuit operates to increase the phase difference, and instead of using the bow phase of the reference level in this section, the PLL circuit operates to increase the phase difference. Locks to the pull-in phase of the reference level in the interval from π to π. In this way, only one of the two pull-in phases becomes the actual pull-in phase. Generally, the one that becomes the actual attraction phase is called the stable attraction phase, and the other is called the unstable attraction phase. In this way, in the conventional phase comparator circuit, an unstable pull-in phase occurs. The phase difference shifts by about π around this unstable pull-in phase, and it is necessary to lock to a stable pull-in phase, so it takes a very long time to synchronize the P L 1 circuit, and the phase difference becomes unstable. If the system fails in a certain pulling phase, it becomes a pseudo-synchronized state, which has the disadvantage of locking onto an unstable pulling phase.

A PLL circuit used in digital communication has the function of fixing the phase of an input signal and a timing clock to a certain constant phase. Therefore, a phase comparator circuit that generates phase difference information between the input signal and the timing clock is required. The present invention relates to this phase comparison circuit, and an object of the present invention is to provide a phase comparison circuit that has a short synchronization pull-in time and generates phase difference information without falling into a pseudo-synchronization state.

"Means for Solving the Problem" The configuration of the present invention is such that, in a phase comparison circuit that outputs a phase comparison signal between an input signal and a timing clock, the logic level of the timing clock at a rising point or a falling point of the input signal is determined. a first logic circuit that outputs an output signal; a second logic circuit that outputs an exclusive OR of the output signal of the first logic circuit and the timing clock; and an output of the input signal and the second logic circuit. a third logic circuit that outputs an exclusive OR with the output signal of the third logic circuit; a fourth logic circuit that outputs the logical negation of the output signal of the third logic circuit; and a fifth circuit that outputs a difference between the output signal and the output signal of the logic circuit.

This method differs from conventional technology in that the exclusive OR is performed between the timing clock and a signal that identifies the logic level of the timing clock at the change point of the input signal, and the phase of this exclusive OR signal and the input signal is compared. .

"Embodiments" Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram for explaining this invention,
lot is an input signal, 102 is a timing clock, 1 is a first logic circuit that outputs the logic rail of the timing clock 102 at the rising or falling point of the input signal 101, and 103 is the output of the first logic circuit 1 2 is a second logic circuit that outputs the exclusive OR of the output signal 103 of the first logic circuit 1 and the timing clock 102; 104 is the output signal of the second logic circuit 2; 3 is the second logic circuit A third logic circuit that outputs the exclusive OR of the output signal 104 of the logic circuit 2 and the input signal 101, 105 is the output signal of the third logic circuit 3, and 4 is the output signal 105 of the third logic circuit 3. A fourth logic circuit that outputs the logical negation of 1
06 is the output signal of the fourth logic circuit 4, 5 is the output signal 105 of the third logic circuit 3 and the output signal 1 of the fourth logic circuit 4
The fifth circuit 107 outputs the difference between the signal and the signal 06.

FIG. 2 is a time chart showing the operation of the circuit shown in FIG. It shows the case. The operation of the circuit shown in FIG. 1 will be explained using FIG. 2. The timing clock 102 (FIG. 2(b)) identifies the logic level at the rising point of the input signal 101 (FIG. 2(a)) in the first logic circuit 1, and outputs its output signal 103 (FIG. 2(C) )) is sent to the second logic circuit 2. The output signal 103 (FIG. 2(C)) of the first logic circuit l and the timing clock 10
2 (Fig. 2(b)) is an exclusive OR in the second logic circuit 2, and its output signal 104 (Fig. 2(d)
)) is sent to the third logic circuit 3. Here, the output signal 103 (FIG. 2(C)) of the first logic circuit 1 is "0".
” level, so the output signal 104 of the second logic circuit 2
(FIG. 2(d)) is equal to the phase of the timing clock 102 (FIG. 2(b)). The output signal 104 of the second logic circuit 2 (FIG. 2(d)) and the input signal lot
(FIG. 2(a)) shows tJF in the third logic circuit 3.
The output signal 105 (FIG. 2(e)
)) is sent to the fourth logic circuit 4 and the fifth circuit 5.

The output signal 105 (FIG. 2(e)) of the third logic circuit 3 is logically negated in the fourth logic circuit 4, and the output signal 106 (FIG. 2(f)) is output to the fifth circuit 5. sent to. Output signal 105 of third logic circuit 3 (Fig. 2(e)
)) and the output signal 106 of the fourth logic circuit 4 (Fig. 2(t
)) is taken in the fifth circuit 5, and its output signal 107 (FIG. 2(g)) becomes the phase comparison signal.

FIG. 3 shows the input signal 101 (third input signal) in the circuit of FIG.
Figure 3(a)) and timing clock 102 (Figure 3(b)
))) is a time chart when the phase difference from π to 2π ranges from π to 2π. The operation of the circuit shown in FIG. 1 in this case will be explained using FIG. 3. The timing clock 102 (FIG. 3(b)) identifies the logic level at the rising point of the input signal 101 (FIG. 3(a)) in the first logic circuit 1, and outputs its output signal 103 (FIG. 3(C) )) is sent to the second logic circuit 2. Output signal 103 of first logic circuit 1 (FIG. 3(C)) and timing clock 1
02 (FIG. 3(b)) is subjected to an exclusive OR in the second logic circuit 2, and its output signal 104 (FIG. 3(d)) is sent to the third logic circuit 3. here,
Since the output signal 103 (FIG. 3(C)) of the first logic circuit 1 is at the "1" level, the output signal 1 of the second logic circuit 2 is
04 (FIG. 3(d)) is the timing clock 102 (
It becomes equal to the negative phase of FIG. 3(b)). For this reason,
Since the phase relationship between the input signal 101 (FIG. 3(a)) and the signal 104 (FIG. 3(d)) of the third logic circuit 3 is equal to that in FIG. The fourth logic circuit 4 and the fifth circuit 5 exhibit the same operation as the time chart shown in FIG. Therefore, as shown in Figures 2 and 3, the relationship between the phase difference between the input signal and the timing clock and the DC level signal obtained by passing the output signal of this phase comparison circuit through a low-pass filter is as shown in Figure 4. It becomes a graph. It can be seen from FIG. 4 that exactly the same output is obtained in the section where the phase difference is from 0 to π and the section where the phase difference is from π to 2π, and that the unstable pull-in phase that existed in the past becomes a stable pull-in phase. Therefore, it is not necessary to shift the phase of the input signal and the timing clock by more than π, and a suspicious synchronization state can be prevented.
The circuit synchronization pull-in time can be shortened.

FIG. 5 shows a circuit diagram of a specific embodiment of the present invention, and FIG. 6 shows a time chart thereof. Here, input signal 10
It is assumed that the phase difference between the timing clock 102 (FIG. 6(a)) and the timing clock 102 (FIG. 6(a)) is in the range from 0 to π. The first logic circuit 1 is a D flip-flop D-F
It outputs the result of identifying the logic level of the timing clock 102 (FIG. 6(b)) at the rising point of the input signal 1ot (FIG. 6(a)). The second logic circuit 2 is composed of a tJ and altruistic OR gate EX-OR, and includes an output signal 103 (FIG. 6(C)) of the first logic circuit 1 and a timing clock 102 (FIG. 6(B)). )
Outputs the exclusive OR with Here, since the output signal 103 (FIG. 6(C)) of the first logic circuit 1 is at the "0" level, the output signal 104 (FIG. 6(d)) of the second logic circuit 2 is the timing clock. 102 (Figure 6(b)
) is equal to the phase of The third logic circuit 3 is an exclusive OR game 1-EX-Or? It outputs the exclusive OR of the output signal 104 (FIG. 6(d)) of the second logic circuit 2 and the input signal 101 (FIG. 6(a)).

The fourth logic circuit 4 is composed of a negation game 1 NOT,
Output signal 105 of third logic circuit 3 (Fig. 6(e))
Outputs the logical negation of . The fifth circuit 5 is a differential amplifier AM
I), the output signal 105 of the third logic circuit 3
(FIG. 6(e)) and the output signal of the fourth logic circuit 4 (the sixth
Output the difference from figure (f)). The output signal 107 (FIG. 6(g)) of this fifth circuit is obtained as a phase comparison signal.

Furthermore, the phase difference between the input signal 101 (FIG. 7(a)) and the timing clock 102 (FIG. 7(b)) is from π to 2.
FIG. 7 shows a time chart in the case of the period of π.

The first logic circuit l has an input signal 101 (Fig. 7 [al)]
The result of identifying the logic level of the timing clock 102 (FIG. 7(b)) at the rising point of is output.

The second logic circuit 2 is the output signal 103 of the first logic circuit l.
(FIG. 7(C)) and the timing clock 102 (FIG. 7(C))
The exclusive OR with (b) in the figure is output. Here, the output signal 103 (FIG. 7(C)) of the first logic circuit 1 is “
I" level, so the output signal 10 of the second logic circuit 2
4 (FIG. 7(d)) is equal to the negative phase of the timing clock 102 (FIG. 7(b)). Therefore, since the phase relationship between the input signal 101 (FIG. 7(a)) and the signal 104 (FIG. 7(d)) of the third logic circuit is equal to that in FIG. , fourth logic circuit 4, fifth logic circuit
Circuit 5 shows the same operation as the time chart shown in FIG. As shown in Figures 6 and 7, the relationship between the phase difference between the input signal and the timing clock and the DC level signal obtained by passing the output signal of this phase comparison circuit through a low-pass filter is shown in the graph in Figure 8. Become.

Therefore, the phase difference is between O and π in the interval and the phase difference is in the range from π to 2π (it can be seen that equal outputs are obtained).

I-Effects of the Invention As explained above, the present invention calculates the exclusive OR of a signal that identifies the logic level of the timing clock at the rising or falling point of the input signal and the timing clock. By comparing the phases of the OR signal and the input signal, an unstable pull-in phase is changed to a stable pull-in phase, so when applied to a PLL circuit, the synchronization pull-in time of the PLL circuit can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the invention in detail,
Figures 2 and 3 are time charts for explaining the invention in detail, Figure 4 is a graph for explaining the invention in detail, and Figure 5 is for explaining a specific embodiment of the invention. 6 and 7 are time charts for explaining a specific embodiment of this invention, FIG. 8 is a graph for explaining a specific embodiment of this invention, and FIG. 9 is a conventional diagram. Figures 10 and 11 are time charts for explaining the operation of the circuit in Figure 9 and its drawbacks, and Figure 12 is a diagram for explaining the operation of the circuit in Figure 9. It is a graph. Patent applicant Nippon Telegraph and Telephone Corporation

Claims (1)

[Claims] (1) In a phase comparison circuit that outputs a phase comparison signal between an input signal and a timing clock, a first logic circuit that outputs a logic level of the timing clock at a rising point or a falling point of the input signal; a second logic circuit that outputs an exclusive OR of the output signal of the logic circuit and the timing clock; and a third logic circuit that outputs an exclusive OR of the input signal and the output signal of the second logic circuit. a fourth logic circuit that outputs the logical negation of the output signal of the third logic circuit; and a difference between the output signal of the third logic circuit and the output signal of the fourth logic circuit. A phase comparator circuit comprising a fifth circuit that outputs an output.