JPH02148145A - Check circuit for vector arithmetic unit - Google Patents

Abstract

PURPOSE:To reduce the number of check circuits by calculating vector data for check as first vector data and checking the coincidence between the calculation result and a correct answer value. CONSTITUTION:When a vector calculation start signal is inputted, a set signal of vector data for check is sent to registers 103 and 104 with selectors, and vector data for check is stored in these registers 103 and 104, and vector data in registers 103 and 104 with selectors is calculated by a vector computing element 105, and the result is stored in a register 106. This vector calculation result is compared with the correct answer value sent from a register 107 in a comparing circuit 108 by the comparison execution signal sent from the circuit 102. Since the coincidence of only the calculation result is checked in this manner, the number of check circuits is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vector arithmetic device, and more particularly to a check circuit for a vector arithmetic unit.

[Conventional technology]

Conventionally, this type of check circuit has been a parity check circuit, a modulo three-channel circuit, and the like.

FIG. 2 is a block diagram showing a parity check circuit. A parity check circuit means that the input vector data is
Registers 201 and 202 that store input vector data
The parity data generated by the circuits 205 and 206 that predict the parity of the input vector data is input to the circuit 205 and 206 for predicting the parity of the input vector data. 205
．． Registers 201 and 20 that store data are input to registers 207 and 208 that store data of 206, respectively.
The data sent from the circuits 2, 207, and 208 are subjected to a parity operation in a circuit 209 that performs a parity operation, and are input to a register 210 that stores data in the circuit 209.

Next, a circuit 211 generates parity using the vector data in the register 106 that stores the vector operation result.
A comparison circuit 212 performs a match check with the data.

FIG. 3 is a block diagram showing a modulo three-channel circuit. A modulo three-chip circuit is a circuit in which input vector data is connected to a register 201 that stores the input vector data.
, 202, is computed by the vector arithmetic unit 105, and is stored in the register 106 that stores the vector computation result.
The modulo-ternary values generated by the circuits 305 and 306 that generate ternary values are input to the registers 307 and 308 that store data in the circuits 305 and 306, respectively, and the data sent out from the registers 307 and 308 that store the data ,
A modulo-3 operation is performed by a circuit 30 that performs a modulo-3 operation, and the result is input to a register 310 that stores data from the circuit 309. Subsequently, a comparison circuit 312 performs a match check with the data of the circuit 311 that generates a modulo-ternary value using the vector data of the register 106 that stores the vector operation result.

[Problem to be solved by the invention] In the conventional check circuit described above, the check bit must be carried around from the input to the output, and if necessary, a coincidence check circuit may be inserted in the middle. Therefore, it has the disadvantage of having a check circuit that requires a large amount of hardware in the arithmetic circuit.

[Means to solve the problem]

The configuration of the check circuit of the present invention includes: a circuit that sends a check vector data set signal and a comparison execution signal based on a vector operation start signal; a register that holds one check vector data and a correct value; a comparison circuit that inputs the comparison execution signal and compares the calculation result of the vector calculation unit with the correct value, calculates the check vector data as initial vector data, and matches the calculation result with the correct value. It is characterized by checking.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. a register 101 that holds one piece of check vector data;
A circuit 102 that sends out a check vector data set signal and a comparison execution signal, and a register 103 with a selector that can input check vector data using the check vector data set signal sent from the circuit 102.
04, a vector calculator 105 that calculates the vector data of registers with selectors 103 and 104, a register 106 that stores the calculation results of the vector calculator 105, a register 107 that holds the correct value, and a comparison execution signal sent from the circuit 102. , includes a comparison circuit 108 that compares the correct value of the register 107 and the calculation result of the register 106,
When the vector calculation start signal is input, the check vector data set signal is sent to the register with selector 103, 1.
04, vector data for check is stored in registers with selectors 103 and 104 in registers with selectors 103 and 104, vector data in registers with selectors 103 and 104 are calculated by vector calculator 105 and stored in registers. A comparison circuit 108 compares the correct value stored in 106 and sent out from register 107 with a comparison execution signal sent out from circuit 102 .

FIG. 4 is a timing chart of FIG. 1.

1. At time 11, a check vector data set signal is sent out based on the vector calculation start signal.

At 2° time t2, check vector data is input to the selector registers 103 and 104 by the check vector data set signal.

3. At the next timing, the check vector data set signal becomes invalid (time t3), so normal vector data is input to the selector registers 103 and 104 (time t4! t5) -4, calculation time t,
After the elapse of , the vector operation result is input to the register 106 at time 0, and a comparison execution signal causes the comparison circuit 106 to perform a match check with the correct value.

5. At the next timing, the comparison execution signal becomes invalid,
The comparison circuit ends its operation.

〔Effect of the invention〕

As explained above, the present invention can significantly reduce the number of check circuits by performing a match check only on the calculation results. This has the effect of increasing speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is a block diagram of a conventional parity check circuit, and FIG. 4 is a block diagram of a modulo-3 check circuit. 101... A circuit that sends out a check vector data set signal, 102... A circuit that sends out a comparison execution signal, 103, 104... A register with a selector that can input check vector data, 105... Vector calculation device, 106... register for storing calculation results, 10
7...Register for holding correct value, 108...Comparison circuit, 201.202...Register for storing input data, 205, 206...Circuit for predicting parity of input data, 207.208. ...Register for storing parity of input data, 209...Circuit for performing parity operation from input data and the same parity, 210...Register for storing parity operation result, 211...Generating parity for vector operation result circuit, 212...
Comparison circuit for checking parity consistency, 305.3
06...Circuit that performs modulo-3 calculation of input data,
307, 308...Register for storing the modulo 3 values of input data, 309...Modulo of input data.
A circuit that performs a modulo-3 operation from three values, 310...A register that stores the modulo-3 value of the circuit 309, 311
. . . A circuit that performs a modulo-3 operation from the vector operation result, 312 . . . A comparison circuit that performs a modulo-3 match check.

Claims (1)

[Claims] Based on the vector operation start signal, there is a circuit that sends out a check vector data set signal and a comparison execution signal, a register that holds one check vector data and a correct value, and a circuit that inputs the comparison execution signal and outputs a vector data set signal and a comparison execution signal. A vector characterized in that it includes a comparison circuit that compares the calculation result of the arithmetic unit with the correct value, calculates the check vector data as initial vector data, and checks the calculation result for matching with the correct value. Check circuit for arithmetic unit.