JPH03256134A - Checking circuit for vector computing element - Google Patents

Abstract

PURPOSE:To reduce the capacity of hardwares and to improve the integration property of an arithmetic circuit due to the reduction of the hardwares by checking the coincidence of only operation results. CONSTITUTION:A checking vector data setting signal 113 is outputted based upon a vector operation starting signal 115. Checking vector data 111, 112 are respectively inputted to registers 103, 104 including selectors based upon the signal 113. Since the signal 113 is invalidated at the succeeding timing, normal vector data 109, 110 are inputted to the registers 103, 104. After the lapse of a prescribed operation time, a vector operation result is inputted to a register 106, a comparison executing signal 114 is sent and the coincidence between the vector operation result and a correct answer value is checked by a comparator 108. A signal is invalidated at the succeeding timing to end the operation of the comparator 108. On the other hand, the signal 113 is outputted based upon a vector operation end signal 116 so that the data 111, 112 are inputted to the registers 103, 104 at the succeeding timing of the input of (n+1) the vector data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a check circuit, and particularly to a check circuit for a vector arithmetic unit.

[Conventional technology]

Conventionally, this type of check circuit has been a validity check circuit, a modulo three-channel circuit, and the like.

FIG. 3 is a block diagram showing a parity check circuit.

Human vector data register 2
01 and 202, the vector calculation unit 105 performs a vector calculation, and the vector calculation result is stored in the vector calculation result register 106. In parallel, the parity generated by the parity prediction circuits 205 and 206 is stored in the data register 207. 208 and sent from registers 201, 202, 207, and 208,
A parity calculation circuit 209 performs a parity calculation, and the calculation result is manually input to a data register 210. Subsequently, the calculation result of the data register 210 is sent to the parity generation circuit 21 by the vector data of the vector calculation result register 106.
A comparison circuit 212 performs a match check with the parity data generated in step 1.

FIG. 4 is a block diagram showing the Mozierlow 3 check circuit.

The input vector data is input to the human vector data register 20.
1,202 and is vector-operated by the vector arithmetic unit 105 is stored in the vector arithmetic result register 106. In parallel, the vector arithmetic result is generated from the human data by the modulo-ternary value generation circuits 305, 306. The resulting modulo-3 values are manually entered into the data registers 307 and 308, respectively, and the modulo-3 values are inputted into the data registers 307 and 308, and the modulo-3 arithmetic circuit 309 uses the data sent from the data registers 307 and 308.
3 calculations are performed, and the calculation results are manually entered into the data register 310. Subsequently, a comparison circuit 312 performs a match check between the calculation result of the data register 310 and the modulo-ternary value generated by the modulo-ternary value generating circuit 311 based on the vector data of the data register 106 .

[Problem to be solved by the invention]

In the conventional check circuit described above, the check bits have to be carried around from the manual input to the output, and if necessary, a match check circuit is inserted in the middle, which requires a large amount of hardware. It has the disadvantage of having.

An object of the present invention is to provide a check circuit for a vector arithmetic unit with a small amount of hardware.

[Means to solve the problem]

The check circuit of the vector arithmetic unit of the present invention executes a comparison with a check vector data set signal based on a register holding check data, a register holding a correct value, a vector calculation start signal, and a vector calculation end signal. A control circuit that outputs a signal, and when a check vector data set signal is output, selects the check vector data and outputs it to a vector calculator, and when the check vector data set signal is no longer output, normal vector data is output. It has a register with a selector that selects and outputs it to the vector calculator, and a comparison circuit that compares the vector calculation result of the vector calculator and the correct value when a comparison execution signal is output.

[For production]

Since a match check is performed only on the calculation results, the amount of hardware can be significantly reduced.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a check circuit of a vector arithmetic unit according to an embodiment of the present invention.

Register 101 contains check vector data 111.1
Hold 12. The control circuit 102 outputs a check vector data set signal 113 and a comparison execution signal 1 using a vector calculation start signal 115 and a vector calculation end signal 116.
14 is sent.

When the check vector data set signal 113 is sent from the control circuit 102, the selector registers 103 and 104 select and hold the check vector data 111 and 112, and transmit the check vector data set signal 113.
is not sent, normal vector data 109,1
Select and hold 10. A vector calculator 105 calculates vector data in selector registers 103 and 104. The register 106 stores the calculation result of the vector calculation unit 105. Register 107 holds the correct value. The comparison circuit 108 compares the correct value in the register 107 and the calculation result in the register 106 in response to a comparison execution signal 114 sent from the control circuit 102 .

FIG. 2 is a timing chart of this embodiment.

1. Based on the vector calculation start signal 115, a check vector data set signal 113 is sent out.

2. Check vector data 111° and 112 are input to the selector registers 103 and 104, respectively, by the check vector data set signal 113.

At the 33rd timing, the check vector data set signal 113 becomes invalid, so the registers with selectors 103 and 104 are filled with normal vector data 109 and 11.
0 is done manually.

4. After a predetermined computation time has elapsed, the vector computation result is input to the register 106, a comparison execution signal 114 is sent out, and the comparator circuit 108 checks whether the correct value of the vector computation result matches.

5. At the next timing, the comparison execution signal 114 becomes invalid, and the comparison circuit 108 ends its operation.

6. Also, at the next timing when the (n+1)th vector data is manually input, the check vector data 111
, 112 are manually input to the selector registers 103 and 104, a check vector data set signal 113 is sent out based on the vector operation completion signal 116.

7. The following operations 2 to 5 are repeated.

〔Effect of the invention〕

As explained above, the present invention can significantly reduce the amount of hardware by performing a match check only on the calculation results. This has the expected effect of

[Brief explanation of drawings]

FIG. 1 is a block diagram of a check circuit of a vector arithmetic unit according to an embodiment of the present invention, FIG. 2 is a timing chart of the embodiment of FIG. 1, FIG. 3 is a block diagram of a parity check circuit, and FIG. FIG. 2 is a block diagram of a modulo three-chip circuit. 101...Register that holds check vector data,...Control circuit, 104...Register with selector,...Vector arithmetic unit,...Register that stores calculation results,...Register that holds correct value. , . . . Comparison circuit, 102 ・ 103 ゜ 105 ・ 106 ・ 107 ・ 108 ・ 109. 110 . . . Ordinary vector data, 111.
112... Vector data for check, 113... Vector data set signal for check, 114... Comparison execution signal, 115... Vector calculation start signal, 116... Vector calculation end signal.

Claims (1)

[Claims] 1. A register that holds check data, a register that holds correct values, and outputs a check vector data set signal and a comparison execution signal based on a vector calculation start signal and a vector calculation end signal. a control circuit that selects the check vector data and outputs it to a vector arithmetic unit when the check vector data set signal is output, and selects normal vector data when the check vector data set signal is no longer output. A check circuit for a vector arithmetic unit, comprising: a register with a selector that outputs the vector arithmetic unit to the vector arithmetic unit; and a comparison circuit that compares the vector arithmetic result of the vector arithmetic unit and the correct value when a comparison execution signal is output.